STM32H725 SRAM1 vs SRAM2 in D2 domain

[Aleks]

Hi!

I use SRAM 1 (0x30000000 - 0x30003FFF) in D2 domain for USART2, USART3 DMA buffers. All work clean. If I use SRAM2 (0x30004000 - 0x30007FFF) just after running debug it's all right. But after "Reset chip and restart debug session" the first access into SRAM2 is a cause of system fail. There is no Error Handler or bus fault, but SysTick stop, system slip.

There is no problems with SRAM1.

If switch off D-cache or disable cache for SRAM2 region in MPU system work perfect.

So what differece betwen SRAM1 and SRAM2 in D2?

[Piranha]

> If switch off D-cache or disable cache for SRAM2 region in MPU system work perfect.

Then most likely the cache management is broken. How are you doing it?

EDIT: Oh, it's a duplicate of this:

https://community.st.com/s/question/0D53W00001UZLndSAH/stm32h7-cache-and-dma-transfer-error-rate

So you ignored both issues I pointed out to you and are still "wondering" why it doesn't work?

[Aleks]

Piranha, thank you for responce.

​

I try different configurations of MPU settings.

1) Good configuration is TEX=0:

TEX= 000 | C=1 | B=1 | Type=Normal Write-back | Descr= no write allocate | Isshare=S bit

MPU_InitStruct.Number = MPU_REGION_NUMBER9;
 MPU_InitStruct.BaseAddress = 0x30000000;
 MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;

2) Bad is:TEX = 1

TEX=001 | C=1 | B=1 | Type=Normal Write-back | Descr=write and read allocate | Isshare= S bit

MPU_InitStruct.Number = MPU_REGION_NUMBER9;
 MPU_InitStruct.BaseAddress = 0x30000000;
 MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;

3) Good is any variation of MPU_TEX_LEVEL if MPU_ACCESS_SHAREABLE.

4) Good is MPU ON (any configuration) and SCB_DisableDCache().

5) Good is MPU OFF and SCB_DisableDCache().

> https://community.st.com/s/question/0D53W00001UZLndSAH/stm32h7-cache-and-dma-transfer-error-rate

>So you ignored both issues I pointed out to you and are still "wondering" why it doesn't work?

I resolved both issues with SPI according your advice. Thanks a lot!

But seems some other issue is grown when I work with USART.

Problem is solved, but when I use "bad" configuration I have a fault. Is "bad" configuration acceptable, isn't it? Of course invalidating and cleaning is done according to your advice.

There is no problem with data corruption, there is problem with DMA fault. SRAM1 D2 is working, SRAM2 D2 not. Is there difference?