STM32H7 max SDRAM clock speed for 480MHz

[Dat Tran]

ST example uses 400MHz / 4 = 100MHz for SDRAM. What should the SDRAM clock be when the system is running at 480MHz? If we use 480/4 then it is 120Mhz for SDRAM, but datasheet shows max of 100MHz for SDRAM! Are we stuck running SDRAM at 60Mhz? Or run the system at 400Mhz?

What is the best way to get the max system performance?

[TDK]

The clock options are more complicated than just SDRAM clock = SYSCLK / prescaler. You should be able to find one at which SYSCLK=480 and SDRAM=100 by using the clock mux.

You don't mention which chip you're using, but here is one such configuration:

 

[Dat Tran]

Hi, we are using STM32H743 which is 480MHz max.

[TDK]

Okay, so you should be able to find a solution using the clock mux. The screenshot I posted is relevant for the STM32H743.

[Tesla DeLorean]

Doesn't it have a DIV2 and DIV3 option, so 120 MHz or 80 MHz (not 60 MHz) are viable? Stuff is also cached, so may mask the clock and latency inherent in the devices. Could also play with "what-blends" options with clocks to pick optimal mix for given application, which might be below maximum, but fits better with wait states or other combinations, CAS timing, etc. If you're willing to characterize your own design thoroughly, you might probably be able to hit 120 MHz on the SDRAM bus/devices.

https://www.st.com/resource/en/reference_manual/dm00314099-stm32h742-stm32h743-753-and-stm32h750-value-line-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf

Section 22.9

SDRAM clock can be fmc_ker_ck/2 or fmc_ker_ck/3

[David Littell]

Hopefully there's a PLL available in the clock tree you can use to generate the FMC clock rate you need.