STM32H7 External 8mHz osc & PLL to 400mHz settings
Hi everyone,
I've been using the STM32H7 Nucleo board (STM32H743ZI) for a project I'm working on. I'm using plain CMSIS (no HAL solutions please ) and I'm having a bit of trouble setting the clock settings to use the external oscillator included on the board (8mHz). The initialisation function below is called from the main function on startup.
Running the software hangs and never cycles. Stepping through with the debugger causes it to drop the debug connection. It won't reconnect the next attempt either, it triggers a 'wrong target' error. Clearly I'm doing something wrong but I've spent a solid day pouring over the datasheet and I can't work out what the issue is. Wondering if anyone can see the issue?
*Edit* I followed the PLL initialisation flowchart (figure 44 pg. 329 STM32H743/753 reference manual)
Regards,
Branyon
void CLK_Init() {
//Activate HSE
SET_BIT(RCC->CR, RCC_CR_HSEON);
//Wait till HSE Ready
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0) {
__NOP();
}
//Use HSE External OSC (8mHz)
CLEAR_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk);
SET_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_HSE);
//Prescaler: /1
CLEAR_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk);
SET_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_0);
//Leave PLLxVCOSEL
//PLL Range 4-8mHz
CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk);
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_2);
//Fraction Default off
//Enable clock output
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
//Multiply by 100
CLEAR_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1_Msk);
SET_BIT(RCC->PLL1DIVR, 0x63);
//Divides by 2 by default
//Activate PLL1
SET_BIT(RCC->CR, RCC_CR_PLL1ON);
//Wait till PLL1Ready
while(READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0) {
__NOP();
}
//Set System Clock to PLL
CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
SET_BIT(RCC->CFGR, RCC_CFGR_SW_PLL1);
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