STM32F407 FSMC physical addressing

[Bertrand PICARD]

Posted on July 04, 2017 at 12:56

Hello everybody,

I am a new ARM microcontroller user.

I drive a winstar 3,5' display (SSD1963 embedded) with a STM32F4-discovery board.

I use FSMC to drive the display with 8080 mode.

To drive the input D/C# (Data / Command) I use FSMC address A19 (PE3).

It works fine if i use the code below :

#define LCD_REG (*((volatile unsigned short *) 0x60000000)) /* DC = 0 */

#define LCD_RAM (*((volatile unsigned short *) 0x60100000)) /* DC = 1 */

The questions are:

- Why I need to write '1' to bit #20 to switch A19 to '1' ?

- Why I cannot use bit #19 rather than bit #20 ?

Thanks in advance

Regards

BP

#stm32f407-fsmc-physical-addressing

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[Bertrand PICARD]

Posted on July 05, 2017 at 16:19

Hello everybody,

No answer since yesterday ... ?

I can add precision :

- To write data to the display, I write bytes at address 0x60100000 to switch D/C display input to '1'.

(Input D/C is connected to PE3 = FSMC A19)

Why I need to use the software code address 0x60100000 to switch A19 to '1' rather than address 0x60080000 ?

What is this mistery ?It seems that FSMC A0 equal to 0x60000002 rather than 0x60000001 !!!Thanks in advance

Regards

BP

[Tesla DeLorean]

Posted on July 05, 2017 at 17:30

>>

No answer since yesterday ... ?

Some people are on vacation.

>>

What is this mistery ?

With a 16-bit bus the external address bus shifts, as A0 is not needed, it becomes a byte lane selection. Therefore A1 from the core's perspective is Pin A0 at the external interface. It's one of those mysteries debunked in the manual.

[Bertrand PICARD]

Posted on July 05, 2017 at 19:08

Hi Clive,

Thank you very much for your answer.

I am a 8 bit microcontroller user !

I suspected that 'the mystery' had to be on the 16-bit bus side

...

Of course, I have read that STM32 used a 16-bit external address bus, but I've not understand the information in the Reference manual (RM0090).

Of course, I've read before to ask my question the chapter 36 Flexible static memory controller (FSMC)

It's written :

The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the

accessed external device has a fixed data width....

...And there are 2 lines, NBL[1:0], for the byte lane selection.

It's not clearly written that A1 from the core's perspective is Pin A0 at the external interface.

So again, Thank you for your answer

B.PICARD

PS : Sorry for my poor english writing... I'm French !

[waclawek.jan]

Posted on July 05, 2017 at 23:41

I believe it may be not entirely clear especially for those who don't have much experience with 16/32-bit buses interfacing, but the following remark is relevant to the case (an older v11 of RM0090, but I believe the current v15 has it in the same way):

JW

[Daniel Studer]

Posted on November 23, 2017 at 16:28

Hi JW,

I'm using the FMC bus on a STM32F7 for an SRAM in 32-bit width.

In the RM there is the same mark, that FMC_A[0] should be connected to A[0] from external memory. My problem is now I should address the external SRAM in byte-address mode, bit with this address-shifting, it is a 32-bit-address mode.

Therefore I should connect FMC_A[2] to A[0] from external memory. Is this correct?

[Bertrand PICARD]

Posted on July 07, 2017 at 16:15

Hi JW,

Thank you very much for your anwer.

OK I've read too quickly the chapter and I've missed this important remark !

The remark is written in section 36.4.1 table 213 inside RM0090 rev. 14 manual dated of april 2017

I don't know why this section (36.4.1) is named NOR/PSRAM rather than NOR/PSRAM/SRAM...

Have a nice WE

BP