STM32F407 - 2 RAM banks

[alexandr]

Posted on June 11, 2013 at 23:11

I have a stupid question:

F407 has 2 RAM banks - 128K with DMA access, and 64K no DMA access.

1) I saw that in all examples only the 1st bank used.

2) I saw that in all IAP Firmware Upgrade exampler, bootloader search for 02xxxxxxh value at ''APPLICATION_START''.

3) The first bank (IRAM1) is set as default in Keil.

So, what is the better way to use both banks?

Some  of my applications needs the big buffers with DMA access, and I make all efforts to give max. as possible memory for this.

I set IRAM2  (64k CCM) as default, make one .c file, where my buffers are described, and set in this file properties - to use IRAM1.

So only buffers are in the DMA-accessable memory (IRAM1) and all other variables, stack  and heap are located in IRAM2.

(in supposition, that 64k is enough for this)

And, of course, I search 01xxxxxxh instead of 02xxxxxxh in the bootloader.

Quiestions:

1) Am I right?

2) May be there is a better way(s) ?

3) What other peoples doing?

4) Is any diference in CPU performance, when the stack and variales are in IRAM2 vs IRAM1 ?

Thanks,

Alex.

#arm-cortex-m4 #iram1 #iram2 #sram-ccm

[Tesla DeLorean]

Posted on June 12, 2013 at 03:14

The way one normally attacks this is to describe the two IRAM areas. Use a scatter file to describe where sections fall, and direct the output of specific objects or function to these areas. Within the source you should be able to use pragmas/directives to utilize different sections/segments.

If you're feeling like implementing a dynamic allocator, have that serve up regions of memory from the available pool(s)

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Make%20use%20of%20the%2064k%20CCM&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=1207

[Tesla DeLorean]

Posted on June 12, 2013 at 03:34

4) Is any diference in CPU performance, when the stack and variales are in IRAM2 vs IRAM1 ?

It's complicated. As I read the docs I get the sense CCM is a cycle slower, but if you're doing a lot of DMA the accesses to CCM won't have any contention, and thus will be far more predictable.

On the F4 there are other issues too, you can't execute code from the CCM and you can't use bit-banding on it. On the F3 you can use it for code.

The Cortex-M3/4 architectures are somewhat different to the ARM9, which would typically have TCM (tightly coupled memory) or I/D-Caches to mitigate the slowness, burst length or widths of external memories. The M3/4 don't have an architected scheme for caching, so you end up with things like ART, and tricks to service prefetch requests.

If you have an RTOS with many stacks/tasks, then the CCM is a good place to put them. You'll need to be conscious not to allocate DMA buffers from the stack/locals, but that shouldn't be hard because it's usually a dangerous/stupid thing to be doing anyway. Watch what file system threads are doing.

From a dynamic allocated view you could specify which pool you want to draw from, or flag if you expect to use the buffer for DMA operations.

There are very easy ways to benchmark code, doing some quick tests on proposed algorithms and memory usage will allow you to make appropriate decisions.

[alexandr]

Posted on June 12, 2013 at 23:10

Thanks.

[Fristedt.Jan]

Posted on August 20, 2013 at 11:52

''4) Is any diference in CPU performance, when the stack and variales are in IRAM2 vs IRAM1 ?

It's complicated. As I read the docs I get the sense CCM is a cycle slower, but if you're doing a lot of DMA the accesses to CCM won't have any contention, and thus will be far more predictable.''

I have noreason to doubt that you are right in this since information from you is usually accurate. However, I can't find any documentation on this topic so I'm not able to verify the info. Can you please provide a link to this documentation or at least some general pointer to where I may find it.

TIA

[jpeacock2399]

Posted on August 20, 2013 at 16:12

There are actually three SRAM banks in the 'F40x: the 64KB CCM, a 112KB SRAM1, and a 16KB SRAM2.  And there's the 4KB backup SRAM, slow access but it persists across resets and power down cycles.  All three SRAM banks have different uses. 

In my appliction there are several DMA streams so I need to optimize for memory bus contention.  I map the FreeRTOS RAM into CCM so task heap and stacks plus the large system stack for nested interrupts are all located in CCM.  For large buffers (USARTs, ADC, SPI) I use SRAM2 since DMA has a separate path that can overlap with SRAM1 access, plus the DMA buffers don'tsuffer from a lack of data caching.  SRAM1 I use for globals, small DMA (I2C) and some large arrays, where the data cache has some benefit.

My rule of thumb:

    Heap and stacks to CCM

    globals and alrge arrays to SRAM1

    DMA to SRAM2

    non-volatile variables to BKPSRAM

All of this can be accomplished in the linker (I use GCC) and by allocating variables to named sections in the C code.

  Jack Peacock