STM32F303VCT6 don't have MCO-PLL divider ?

[placidity.master_gmail.com]

STM32F303VCT6 don't have MCO-PLL divider ?

but gpio have 50 MHz band.; how i output 72 MHz ?

[TDK]

You can output SYSCLK instead of PLLCLK you avoid the divider. Note than 72 MHz is above the specification on GPIO pins, but it may work to some extent.

[placidity.master_gmail.com]

this is a search for crutches. definitely a flaw.

[TDK]

You're saying that MCOPRE not existing on the STM32F303VCT6 is a flaw? I mean, you can wish it was another way, but it's described correctly in the RM so what exactly are you expecting here?

[placidity.master_gmail.com]

I think that the MCU should have a divider, for example, to output a frequency below 2 MHz when the outputs are set to low speed. And the source may well be PLL. note that SYSCLK can also be 72 MHz.

before, I didn't understand why people study other MCUs when there is such a cool ST. now I want to see documents from other manufacturers.

[waclawek.jan]

You can output PLLCLK/N through TIM1/TIM8.

JW

[placidity.master_gmail.com]

this is a search for crutches