STM32F091 how to detect suspected CPU stall through Flash access?
I'm having trouble with my IAP erase and write of Flash in my custom bootloader. I need to overlap comms activity with Flash erase so comms doesn't time out, but despite attempts to force the bootloader code, ISRs and vector table into SRAM, my suspicion is that I'm still getting a CPU/bus stall, as described in RM0091 section 3.2.2. What I see is ISRs not being entered to service the UART, giving me read overruns. So my questions is, "How can I tell if the CPU/bus is stalling, and what code is initiating the Flash access?"
Is there any chance the prefetch controller is the culprit?