Single bank mode for STM32L471RxE devices

[DWyde.1]

Hi Everyone

I'm having some trouble with the reference manuals description of single bank mode for the STM32L471RxE devices. In the attachments you can see that the page number for bank 2 always starts with 256, regardless of the flash size. What I couldn't figure out was, what happens with the page numbers if I disable dual bank mode for these devices? Especially for the types which only have 512kB flash. Is the page numbering still with a gap from 127 to 256 (in 512kB devices)? Or will they change to contiguous numbers (e.g 127, 128, ect.)?

Thanks in advance for your help

[Peter BENSCH]

Welcome, @DWyde.1​, to the community!

It is important to know that there is not a separate chip for each flash variant, so all current STM32L471 have the same die and thus the same physical amount of flash.

But before you get thievingly excited and think you can get an STM32L471xG with 1MB by bying a cheaper STM32L471xE with 512KB, you must realise that no guarantee is given for the untested area, neither functionally nor over the temperature range! For professional use, for which the respective manufacturer must also provide a guarantee, the only option is to use the guaranteed range.

Now to the limit between the two 512KB blocks: with Dual Bank Flash, there must be two charge pumps to supply one block each, which is why you cannot simply scale the total flash size. So if an STM32 with dual bank flash is guaranteed less flash, in this case 512K instead of 1MB, there is inevitably a gap of 256KB between the first and the second block - if bit 21 (DUALBANK) of the User and read protection option bytes is set.

However, if you reset the bit DUALBANK mentioned above, you have a continuous address range in the first block of the STM32, so the second block is logically appended to the first.

Does it answer your questions?

Regards

/Peter

[DWyde.1]

Hi Peter

Thank you very much for the warm welcoming and help. I think I understand it now but just to be sure if my assumption is correct: So for the 512kB device, if I reset the bit DUALBANK to 0, then the page numbers won't have a gap between 127 and 256 but rather continue with 128, 129 and so on. So the page which starts at 0x0804 0000 has the page number 128 if I set the bit DUALBANK to 0 and otherwise, if the DUALBANK bit is set to 1, it would have the page number 256. Is that correct? And if I set the bit DUALBANK to 0, does this also mean that there isn't a bank 2 anymore but only bank 1? I'm asking this because if I want to erase a page, I saw that I have to set the page number that I want to erase and also the corresponding bank.

Best regards and thank you again

Daniel

[Peter BENSCH]

I assume that this is exactly how it behaves, but I cannot double check and confirm it at the moment due to a lack of hardware. Until we get final confirmation from someone else, you are welcome to check it out.

Regards

/Peter

[DWyde.1]

Thank you very much. Unfortunately I also can't double check it at the moment because I don't have the proper hardware. I'm already trying to get the right controller to test it but if someone already tried it I'd be happy to know if the described behavior is correct.

Best regards

Daniel