Re: port uclinux on stm32f7?

[sheng yang]

Posted on April 14, 2018 at 15:23

I add earlyprintl support for stm32f767igt,and it seems success.i modified the start_kernel() function as below

extern void printascii(const char *);

asmlinkage __visible void __init start_kernel(void)

{

char *command_line;

char *after_dashes;

printascii('iysheng debug!!!!');

}

i get the console output

iysheng debug!!!![ 0.000000] Booting Linux on physical CPU 0x0

[ 0.000000] Linux version 4.4.0-uc0-g17edafa-dirty ([e-mail]) (gcc version 5.4.0 (GCC) ) #64 PREEMPT Sat Apr 14 20:21:44 CST 2018

[ 0.000000] CPU: ARMv7-M [411fc270] revision 0 (ARMv7M), cr=00000000

[ 0.000000] CPU: unknown data cache, unknown instruction cache

[ 0.000000] Machine model: STMicroelectronics STM32429i-EVAL board

[ 0.000000] bootconsole [earlycon0] enabled

[ 0.000000] debug: i.....

But when i debug  timer function,i add one line code in file uClinux/linux/drivers/clocksource/timer-stm32.c as

static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)

{

struct stm32_clock_event_ddata *data = dev_id;

writel_relaxed(0, data->base + TIM_SR);

data->evtdev.event_handler(&data->evtdev);

printk('iysheng *******\n');

return IRQ_HANDLED;

}

then i get nothing from console,i get confuzed,why could this happen,clk and timer will init after these code i add in start_kernl().So why that happed ,why could i get nothing from the console? 

[stm322399]

Posted on April 15, 2018 at 13:10

My better advice for you is to go for a newer kernel first. 4.4.0 is more than two year old, and STM32 port had a lot of improvement since.

IMHO, the easiest way to go is to try buildroot, carefully avoiding binutils >=2.29

[sheng yang]

Posted on April 18, 2018 at 18:53

 ,

 ,

thanks for your advice,i use a dsb code here to solve this bug,code in arch/arm/mm/proc-v7m.S.

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S

 ,

old mode 100755

 ,

new mode 100644

 ,

index b390d32..67d9209

 ,

--- a/arch/arm/mm/proc-v7m.S

 ,

+++ b/arch/arm/mm/proc-v7m.S

 ,

@@ -81,12 +81,11 @@ ENDPROC(cpu_v7m_do_resume)

 ,

* This should be able to cover all ARMv7-M cores.

 ,

*/

 ,

__v7m_setup:

 ,

-

 ,

@ Configure the vector table base address

 ,

ldr r0, =BASEADDR_V7M_SCB

 ,

ldr r12, =vector_table

 ,

str r12, [r0, V7M_SCB_VTOR]

 ,

-

 ,

+

 ,

@ enable UsageFault, BusFault and MemManage fault.

 ,

ldr r5, [r0, ♯ V7M_SCB_SHCSR]

 ,

orr r5, ♯ (V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)

 ,

@@ -105,25 +104,22 @@ __v7m_setup:

 ,

mov r6, lr @ save LR

 ,

mov r7, sp @ save SP

 ,

ldr sp, =__v7m_setup_stack_top

 ,

- dsb @ ensure data Synchronization Barrier <,

mailto:[e-mail]

>,

 ,

- cpsie i @ enable interrupt

 ,

+ cpsie i

 ,

svc ♯ 0

 ,

-

 ,

-1: cpsid i @disable interrupt

 ,

-

 ,

+1: cpsid i

 ,

str r5, [r12, ♯ 11 * 4] @ restore the original SVC vector entry

 ,

mov lr, r6 @ restore LR

 ,

mov sp, r7 @ restore SP

 ,

-

 ,

+

 ,

@ Special-purpose control register

 ,

mov r1, ♯ 1

 ,

msr control, r1 @ Thread mode has unpriviledged access

 ,

 ,

- @ Configure the System Control Register to ensure 8-byte stack alignment

 ,

+ @ Configure the System Control Register to ensure 8-byte stack alignment

 ,

@ Note the STKALIGN bit is either RW or RAO.

 ,

- @ ldr r12, [r0, V7M_SCB_CCR] @ system control register

 ,

- @ orr r12, ♯ V7M_SCB_CCR_STKALIGN @ bit 9 of V7M_SCB_CCR if read only

 ,

- @ str r12, [r0, V7M_SCB_CCR]

 ,

+ ldr r12, [r0, V7M_SCB_CCR] @ system control register

 ,

+ orr r12, ♯ V7M_SCB_CCR_STKALIGN

 ,

+ str r12, [r0, V7M_SCB_CCR]

 ,

ret lr

 ,

ENDPROC(__v7m_setup)

 ,