I am learning the adv_timer module in the RM0440 document. Is there any error in the OR logic gate in the screenshot?

[Cfang.1]

[waclawek.jan]

Why do you think so?

If any of the break signals is active, the result is active. That's OR for me.

JW

[Cfang.1]

Because we think TIMx_BKIN , tim_brk_cmp1..4,tim_brk_cmp5..7 is active low after system reset.