Has anyone ever had trouble with STM32 communicating info to another processor through the SPI?

[TMeye.2]

I have an STM32F101V8 communicating with a AT91SAM9260. The Atmel is the master to the STM32. Upon start up, our device checks for communication between these two processors, it does so by using a set of samples. The Atmel sends the samples, the STM32 retrieves them and sends it back to the Atmel. We are seeing an issue with the incorrect number of samples being returned from the STM32 to the Atmel. I know other scenarios would not relate to this exactly, but are there any known communication issues between these two processors? or has anyone ever come across issues with their STM32 SPI? I'm no sure if this is the right place to be asking this question, any help is greatly appreciated!

[Tesla DeLorean]

The forum is full of people who have trouble doing stuff, it's not a yardstick I use to measure anything.

None of this stuff is inherently broken, but there are lots of settings, expectations, and complexity.

Check the Errata.

Get a Logic Analyzer, understand what the actual issue is. Likely with timing, and synchronization, and recovery in situations when it fails.

Come up with a protocol that's robust.

Use timing you know both ends can meet.

[S.Ma]

"Use timing you know both ends can meet" I think this is the key and drives the protocol. Got 12 mcu on a single tweaked spi, slave mode uses dma in cyclic mode and exti on nss to operate. Spi fifo may require workaround to be flushed. Some delays need to be inserted on master side to let the slave properly process the interrupts.

[gbm]

What do you exactly mean by "sending back the samples"? The SPI slave implemented with a microcontroller may actively respond in the 3rd frame sent in single SPI session. The first frame to be sent by a slave must be written to SPI data register in preparation to the transfer. The second - during receiving the 1st frame from the master, so still without a chance to interpret it. The 3rd frame sent may be a response to the 1st frame received (like, for example, an echo of the 1st one). Generally, a smart state machine implemented in software is required to implement the SPI slave functionality. This should also implement the NSS handling. Not a trivial thing to do.

[Javier1]

as @Community member​ said, there are 4 different SPI modes, which one are you using? Are both chips using the same SPI mode?

Extra ball: did you placed your pullup resistors in the MISO MOSI SCK and CS lines?