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DChen.7
Associate II
April 20, 2021
Solved

Dear all, What is the meaning of CNT_INIT in the Figure 120 of Reference manual RM0008 of showing the Internal clock source mode of STM32F103? The tile of this figure is 'Control circuit in normal mode', is it right? Thanks.

  • April 20, 2021
  • 4 replies
  • 3054 views

0693W00000901HiQAI.jpg

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Best answer by Imen.D

@DC.18hen​  you are welcome :)

This bit is set by the UG flag.

You can more check the RM0008, in the timer section that you are using.

For example for (TIM2 to TIM5) section:

"Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)."

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.

0693W00000AM5hyQAD.jpgPlease mark my answer as best by clicking on the "Select as Best" button if it helped :smiling_face_with_smiling_eyes:.

Imen

4 replies

Technical Moderator
April 20, 2021

Hello @DC.18hen​ and welcome to the STM32 Community =)

CNT_INIT is an internal signal.

I will ask our team to add a description for the CNT_INIT bit.

Please mark my answer as best by clicking on the "Select as Best" button if it helped :smiling_face_with_smiling_eyes:.

Imen

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
DChen.7
DChen.7Author
Associate II
April 20, 2021

Hello @Imen DAHMEN​ 

Thank you for your help. And where is the CNT_INIT bit? What is its completely English words stands for?

Best regards,

Dchen

Technical Moderator
April 20, 2021

CNT_INIT means counter initialize. and when this bit is set, the counter clock is reset.

Imen

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
DChen.7
DChen.7Author
Associate II
April 20, 2021

Thanks Imen.

And is this bit set by user or the UG flag?

Sorry for having so many questions.

DChen

Imen.DBest answer
Technical Moderator
April 21, 2021

@DC.18hen​  you are welcome :)

This bit is set by the UG flag.

You can more check the RM0008, in the timer section that you are using.

For example for (TIM2 to TIM5) section:

"Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)."

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.

0693W00000AM5hyQAD.jpgPlease mark my answer as best by clicking on the "Select as Best" button if it helped :smiling_face_with_smiling_eyes:.

Imen

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
DChen.7
DChen.7Author
Associate II
April 21, 2021

Thank you Imen. I got it from your answer.

DChen