@DC.18hen you are welcome :)
This bit is set by the UG flag.
You can more check the RM0008, in the timer section that you are using.
For example for (TIM2 to TIM5) section:
"Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)."
The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.
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Imen
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