After reset I see that both PRIMASK and FAULTMASK registers have the value of 0. In my understanding (I could be wrong...) this means that the interrupts are enabled. Is this normal? I would expect the interrupts to be disabled after reset... thanks

[EGonc.1]

..

[Uwe Bonnes]

It is good habit to write a short title and the real description in the text.

Are you sure you evaluated both masks really before any initialization was done?

[EGonc.1]

I just put a breakpoint at:

Reset_Handler:  

 ldr  sp, =_estack   /* set stack pointer */

and at this point using the Eclipse registers window I can see that both PRIMASK and FAULTMASK are 0.

[Uwe Bonnes]

As answered in your repeated question:

https://developer.arm.com/documentation/dui0646/b/the-cortex-m7-processor/programmers-model/core-registers?lang=en

[Pavel A.]

Yes, by contrast with some other architectures in Cortex-M the 'global' core interrupts are enabled after reset.

Most of interrupt sources are vendor-specific and controlled via NVIC. In the NVIC all vectors are disabled after reset.

So just be careful not to get a fault (exception) and you can safely set up your interrupts after reset.

Call __disable_irq() and __enable_irq() around configuration of NVIC and peripherals, if this comforts you.

-- pa