How to obtain the maximum USB-Transfer-Speed of STM32F4 with ULPI in Device-Mode [solved]

[andre23]

Posted on August 26, 2016 at 19:39

Hardware / Configuration:

 STM32F407vgt6 @168MHz

 USB3300 ULPI (waveshare) @24MHz

 USB HS + DMA

 Bulk Transfer (IN-Transfer)

 Modified cdc-Example (STM32_USB-Host-Device_Lib_V2.1.0)

 libusb-1.0.19-10903

Hello ,

I try to obtain the maximum Transfer-Speed for the STM32 in Device-Mode. I Try to Transfer 15MiB from Device to Host over libusb as fast as possibile.

Every time a ''DataInComplete'' occures, I start another 512-Byte ''DCD_EP_Tx()''-Transfer of generated Data.

My Problem is, that my logic-Analyzer detect every 3 Transfers a Error, probaly because the Data is not complete prebuffered.

What could be the Problem  / What could I try ?

#stm32-ulpi-usb-hs-bulk-libusb #usb #fifo #device

[tsuneo]

Posted on August 29, 2016 at 06:19

In your trace, two problems are seen,

1) transaction error 2) NAK appears too often

1) transaction error

> My Problem is, that my logic-Analyzer detect every 3 Transfers a Error,

Maybe, it's a problem of endpoint FIFO allocation?

Recommended FIFO allocation is,

usb_conf.h
line:119
/****************** USB OTG HS CONFIGURATION **********************************/
#ifdef USB_OTG_HS_CORE
#define RX_FIFO_HS_SIZE 384 // (in DWORD = 1536 bytes)
#define TX0_FIFO_HS_SIZE 32 // (in DWORD = 128 bytes)
#define TX1_FIFO_HS_SIZE 16 // (in DWORD = 64 bytes)
#define TX2_FIFO_HS_SIZE 512 // (in DWORD = 2048 bytes)
#define TX3_FIFO_HS_SIZE 0
#define TX4_FIFO_HS_SIZE 0
#define TX5_FIFO_HS_SIZE 0
// total 934, 90 DWORD is reserved

2) NAKs While the device is NAKing, transfer speed drops.

> Every time a ''DataInComplete'' occures, I start another 512-Byte ''DCD_EP_Tx()''

You may pass transfer size greater than 512 (one packet) to DCD_EP_Tx(). For example, 4K bytes or more, as much as your data RAM size allows. In this way, you can reduce the NAK ''gap'' between the transactions.

3) RM description

The decision of endpoint FIFO size is complicated.

- While DMA is applied, the USB core reserves one DWORD per each TX endpoint at the end of FIFO - TX0_FIFO_HS_SIZE requires at least 32 DWORD Unfortunately, the OTG_FS/OTG_HS sections of STM32 Reference manuals don't describe it fully.

SiLabs (Energy Micro) EFM32 family has almost the same USB IP as STM32F4/L4/F7, provided by Synopsys. Around 85% of USB description on the reference manuals is common in word by word, but the EFM32 description is much revised from STM32's. Compare ''FIFO RAM Allocation'' section of STM32 withEFM32's,

http://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031pdf/files/DM00031pdf/jcr:content/translations/en.DM00031pdf

, 10 FIFO RAM allocation (p1396)

http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32WG-RM.pdf

, 4.7 FIFO RAM Allocation (p329) ST should claim revised USB IP description for the RM's to Synopsys, at least those they had provided to SiLabs (in 2014-07-02).

Tsuneo

[andre23]

Posted on August 29, 2016 at 10:18

Thanks,

the Problem is solved. When I use the ''DCD_EP_Tx()'' Function for a larger Block (3*1024) no Errors occur on the Bus.