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PMath.4
PMath.4
Senior III
September 7, 2019
Solved

STM32H743: FMC SDRAM access too slow for LTDC @ 25MHz

  • September 7, 2019
  • 2 replies
  • 1947 views

I've copied all the various examples of using LTDC to drive a VGA screen and implemented them on the STM32H743II with 64Mbit SDRAM using the normal SDRAM timings. Everything works except that the RAM reading is too slow to keep up with the LTDC requests resulting in data corruption on the screen. This is proved by slowing down the request rate when everything works perfectly (12.5MHz). I've looked at the reference manual and the datasheet but can't work out what drives the FMC clock - is it fixed frequency , if so what?

Any pointers appreciated - surely an H743 @ 400MHz should be able to do this when lot of people have it working on the STM32F429.

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Best answer by waclawek.jan

> I've looked at the reference manual and the datasheet but can't work out what drives the FMC clock

And what exactly did you look at?

0690X00000AQsogQAD.png

0690X00000AQsolQAD.png

0690X00000AQsoqQAD.png

0690X00000AQsovQAD.png

> surely an H743 @ 400MHz should be able to do this when lot of people have it working on the STM32F429

This depends on several factors, the raw memory clock frequency vs pixel clock is just one of them. The main one is the used color depth. Bandwidth of SDRAM/FMC can be easily exhausted if there's a heavy fight for the resources (FMC access here) from various bus masters (LTDC, processor, DMA, DMA2D, maybe also others). Using FMC's other banks won't help either. IIRC, FMC in the 'F429 runs at the system clock, i.e. max. 180MHz, which is close to the max clock of FMC in the 'H7 (200MHz), so there's not much of a difference in this.

JW

PS. Have you read AN4861 ?

2 replies

waclawek.jan
waclawek.janBest answer
Super User
September 7, 2019

> I've looked at the reference manual and the datasheet but can't work out what drives the FMC clock

And what exactly did you look at?

0690X00000AQsogQAD.png

0690X00000AQsolQAD.png

0690X00000AQsoqQAD.png

0690X00000AQsovQAD.png

> surely an H743 @ 400MHz should be able to do this when lot of people have it working on the STM32F429

This depends on several factors, the raw memory clock frequency vs pixel clock is just one of them. The main one is the used color depth. Bandwidth of SDRAM/FMC can be easily exhausted if there's a heavy fight for the resources (FMC access here) from various bus masters (LTDC, processor, DMA, DMA2D, maybe also others). Using FMC's other banks won't help either. IIRC, FMC in the 'F429 runs at the system clock, i.e. max. 180MHz, which is close to the max clock of FMC in the 'H7 (200MHz), so there's not much of a difference in this.

JW

PS. Have you read AN4861 ?

PMath.4
PMath.4Author
Senior III
September 7, 2019

Many thanks

I found the reference to fmc_ker_ck but not the definition of where it comes from. In my application FMC was using the default clock which is in theory RCC_HCLK3 which is running at 200MHz. Changing this to PLL_q_clk which I have set for 200MHz has solved the issue ( RCC->D1CCIPR |=1;)

This doesn't make any sense but at least the problem is solved.

One additional confusion is the H743 Clock configuration page of CubeMX doesn't include FMC.

Asand.11
Asand.11
Associate
February 22, 2023

Sorry sir where i can set this in stmcubeide?

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