How can you validate that Independent WatchDog (IWDG) is resetting the processor ?

[mm.51]

Development Board: Nucleo-L476RG.

IDE version: STM Cube IDE 1.11.0

I have implemented this

"Configuring the IWDG when the window option is disabled When the window option it is not used, the IWDG can be configured as follows:

1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).

2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).

3. Write the prescaler by programming the IWDG prescaler register (IWDG_PR) from 0 to 7.

4. Write the IWDG reload register (IWDG_RLR).

5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).

6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA)."

I'm not sure as to how I can validate that my processor is resetting.

Any suggestions would be appreciated.

Thanks

[MM..1]

In main code start read reset flags and clear it.

[Pavel A.]

> how I can validate that my processor is resetting

Start the IWDG and don't refresh it (just spin) for a few minutes.

The MCU should reset. In your main() function read the reset reason and check that it is because of IWDG:

 uint32_t reset_flags = RCC->CSR;
 if (reset_flags & RCC_CSR_IWDGRSTF) {
 // This was IWDG 
 }
 else if (reset_flags & RCC_CSR_WWDGRSTF) {
 // This was WWDG
 }
 else if (reset_flags & RCC_CSR_SFTRSTF) {
 // Software reset (NVIC_SystemReset or by debugger)
 }