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STM32CubeIDE 1.9 HAL fails to enable ADC in stm32H743vit6 revision V

Senior III

It fails when called by `HAL_ADC_Start_DMA(&hadc2, &ADCbuf[0], 1)` exact position is at stm32h7xx_hal_adc.c `ADC_Enable()` depicted in the picture below.0693W00000Lz54JQAR.png I have no idea why this happening. Called by itself an internal error!

And complete project has been attached.

And pcb layout:



Accepted Solutions
Senior III

It seems we have hardware bug mentioned here:

stm32 - STM32H7 ADC Baremetal - ADC not ready - ADC no conversion - Electrical Engineering Stack Exchange

I will test ans report. Test report:

CubeIDE does not generate hadc2.Init.ClockPrescaler= .

Then I've added folloing line to `MX_ADC_Init()` function before `HAL_ADC_Init(&hadc2)`:


And all ASYNC prescaler prevent ADC for being enabled.

And the ADC got started, but why?

Could some employee please report this bug?

View solution in original post

Senior III

I've forgot to add ADC and stm32h7 and HAL to flag, I ask if employee's could do this.


Ensure the ADC clock mux is set to the correct value and that the clock is being enabled. CubeMX has a bug where this doesn't happen sometimes.

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Does the VDDA/VREF+ has the necessary capacitors and VCC3.3 some bigger with several uF?

Pavel A.
Evangelist III

@SeyyedMohammad​ Is your MCU H743 or H750VB as on the schema?

If the 750, is it by chance stepping Y? There's a difference in ADC behavior and errata for stepping Y.

No H743 is, but what is meaning stepping Y?

So wierdly ADC clock mux is grayed out in clock distribution gui and I think this is a bug*. but I've checked the register ADCSEL in Reference manual, named in cubeide as ADCSRC (another deficiet*) has correctly selected 00 means PLL2P.

As you can see VREF/VDDA has no cap on this chinees board, but VCC3.3 has also 22u.

I've added 0.1u 1u cap to VDDA/Vref+ but no thing changed.

I've added 0.1u 1u cap to VDDA/Vref+ but no thing changed.