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IWDG in STOP2

IHlot.1
Associate II

I'm using MCU STM32WB55CE. The issue is the following:

after putting MCU in STOP mode it looks like IWDG still running and reset the MCU.

Option byte: 0x3B79F1AA, means bit IWDG_STDBY and IWDG_STOP clear.

I'm using SEGGER J-Link for debugging. Ble stack version: 1.13.3

IWDG init:

void InitWatchDog()
{    
    FLASH_OBProgramInitTypeDef obInit;
    HAL_FLASHEx_OBGetConfig(&obInit);
    HAL_StatusTypeDef status = 0;
 
    if ( (obInit.UserConfig & OB_USER_IWDG_STOP) !=  OB_IWDG_STOP_FREEZE
            || (obInit.UserConfig & OB_USER_IWDG_STDBY) != OB_IWDG_STDBY_FREEZE )
    {
        status = HAL_FLASH_Unlock();
        if (status)
        {
            assert(false);
        }
        status = HAL_FLASH_OB_Unlock();
        if (status)
        {
            assert(false);
        }
 
        FLASH_OBProgramInitTypeDef OBInit =
        {
            .OptionType = OPTIONBYTE_USER,
            .UserType = OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY,
            .UserConfig = OB_IWDG_STOP_FREEZE | OB_IWDG_STDBY_FREEZE,
        };
        status = HAL_FLASHEx_OBProgram(&OBInit);
        if (status)
        {
            assert(false);
        }
 
        HAL_FLASH_OB_Launch();
        HAL_FLASH_OB_Lock();
        HAL_FLASH_Lock();
    }
 
    InternalWatchdog.Instance = IWDG;
    InternalWatchdog.Init.Prescaler = IWDG_PRESCALER_256;
    InternalWatchdog.Init.Window = 4095;
    InternalWatchdog.Init.Reload = 4095;
    if (HAL_IWDG_Init(&InternalWatchdog) != HAL_OK)
    {
        assert(false);
    }
}

Put MCU in sleep mode:

void EnterStopMode(void)
{
    LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
 
    HAL_SuspendTick();
 
    HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
 
    HAL_ResumeTick();
}

6 REPLIES 6
Mvill.17
Associate III

Hi

I'm working with STM32L0 and have the same problem: the uC enters the STOP mode and the IDWG reset the system though I config the watchdog hardware and clear IWDG_STOP in the option byte.

Why do they put this bit in the option byes if it the watchdog doesn't freeze in STOP?

Bye

IHlot.1
Associate II

This IWDG issue is odd, i've tried several solution suggested on this forum, but none of it help me.

I'm not sure as for the second core (M0) which is responsible for Ble stack.

Is it possible that core M0 won't allow MCu goes in to STOP mode?

I used the following macro for this :

LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);

but not 100% sure.

Remy ISSALYS
ST Employee

Hello,

You have the right configuration for the following option bytes:

  • IWDGSTOP = 0 : Independent watchdog counter frozen in Stop mode
  • IWDGSW = 1 : Software independent watchdog

It seems that you are not entering in stop mode as it should be done, I suggest you to

have a look on BLE_HeartRate example available in STM32CubeWB package which allow to go in stop mode using low power manager. In addition, when CPU2 is running, you shall not use LL_C2 command like the following: LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);

For debugging purpose, according to reference manual RM0434, there is a bit to configure in order to debug with IWDG:

When the CPU1 enters Debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on the configuration of the corresponding bit in debug freeze register.

See DBG_IWDG_STOP: IWDG stop in CPU1 debug

  • 0: Normal operation. IWDG continues to operate while CPU1 is in debug mode
  • 1: Stop in debug. IWDG is frozen while CPU1 is in debug mode

Best Regards

The guys are not asking for stopping IWDG in debug mode, which is a different feature. They are asking for stopping IWDG in low-power Stop mode.

Piranha
Chief II

By the way, in the code you posted in this topic, the line 8 must be after the line 11.

Piranha
Chief II

As you took the code from my article, did you define the NDEBUG for a non-debug build and tested that build?

Maybe you are entering the Standby mode from ISR (interrupt service routine)?