STM32H7B0 ULPI Timing in 1.8V and PHY Selection

[Cirno]

I am currently working on using the USB3320 ULPI PHY with the STM32H7B0VBT6. After reading the STM32 reference manual, I noticed that it mentions special attention should be paid to the hold time when operating at 1.8V.

Additionally, I came across a forum post discussing how to select a ULPI PHY:
https://community.st.com/t5/stm32-mcus/how-to-check-compatibility-on-usb-ulpi-transceivers-with-stm32/ta-p/657275

However, I found that the tDC/tDD for the STM32H7B0 at 1.8V is as high as 13ns, and 1s/60Mhz = 16.67ns, 16.67ns - 13ns = 3.67ns. I have not been able to find any PHY that meets this condition. For example, the setup time for the USB3320 (used on EVAL and Discovery boards, In ULPI Output Clock Mode) is 5ns, and most PHYs I have found seem to have a setup time of over 5ns, which clearly does not meet the ULPI timing requirements.

Is there any PHY available that can be used with the STM32H7B0 at 1.8V VDD and also meets the timing requirements? 

Thank you in advance for your assistance.

[FBL · Accepted solution]

Hi @Cirno 

Indeed, your analysis is correct. The only backup solution is to use:

• An LVDS voltage level shifting
• With the PHY placed as close as possible of the MEB connector (not on a daughter board)
• In CLKIN mode (CLKOUT mode won’t work)

[Cirno]

Thank you for your response. I think I will try using the PHY's ULPI Input Clock Mode and pay more attention to the layout.