STM32H7 SDRAM Speed Code and CAS Latency

[regjoe]

Hello,

SDRAMs are available in different speed option -5, -6 or -7. IMHO this specifies the max. SDRAM clock at CAS=3, but SDRAM can configured via CAS parameter to be used at a lower clock frequency.

Alliance Memory -7 for example can be configured CAS=3, 2 and 1, ISSI only with CAS=3 and2.

The lower the CAS value the lower the max. clock frequency, here for the -7 chip at CL3=133, CL2=100 and CL3=50MHz and the higher the access time.

According to the H7 datasheet, the max. FMC Clock is 100MHz. Regarding Alliance Memory, I would expect to configure CL=2 for 10ns clock.

The STM32H753_EVAL2 is equipped with ISSI speed option -6 and is configured CAS=2.

IMHO it should be no problem to run a SRAM at a lower clock but regarding SDRAM I am unsure because of the reduced access time of 5.4ns compared to the 6ns at speed option -6 with CAS=2. So I wonder if -7/CAS=2 would be also a valid option for running the FMC at 100MHz.

Regarding the ISSI read timing here

the shorter the access time the better, right? Also, regarding the H7 FMC read timing diagram below

I cannot find the corresponding FMC parameter to the "access time" mentioned in the SDRAM datasheet.

Any help? 

[SofLit]

Hello,

You can check this article "How to set up the FMC peripheral to interface with the SDRAM IS42S16800F-6BLI from ISSI" on how to configure SDRAM for STM32 based on a SDRAM datasheet: 

Hope it helps.

[regjoe]

Hello @SofLit ,

I knew about this document before but unfortunately it does not answer my question, I think.

I just want to understand why the more expensive 166MHz ISSI -6 has been chosen for the STMH7 evaluation boards although IMHO the 143/133MHz -7 does the job even better than the -6. 

When the H7 reads data, the SDRAM drives its outputs at rising clock after tAC, the µC reads at the next rising clock and data is hold by the SDRAM for tOH.

The H7 read needs a setup and hold time tSU and tH of 3 and 0ns.

The ISSI -7 has tAC of 5.4ns, the -6 at 6ns. So the -7 provides data earlier to the H7 rising clock than the -6. The hold time of -7 and -6 are for both 2.5ns.

Regarding the AM SDRAM, tAC is 5.4ns and tH is 2.7ns.

IMHO the ISSI -7 and AM -7 chips both provide a better timing characteristics and are usable for the H7.

Anybody already using the -7 chips from ISSI or AM? Do I miss something?

[Tesla DeLorean]

>>I cannot find the corresponding FMC parameter to the "access time" ..

Access time comes from the totality of *time* that the accumulation of *cycles* affords. You get to it via the assorted cycles in the various stages.

The logic is synchronous so the unit of time you can add/remove is a cycle.

SDRAM has a somewhat slow setup/prefetch time, where is pulls a relatively large *line* of data from the array, and then blast that out in a linear sequence.

At 5ns CAS3 is 15ns, whereas at 7ns CAS2 is 14ns, both >= 14ns, it's then a balancing exercise between setup and streaming data. The STM32/ARM don't have particularly deep caches/prefetch, so its hard to get maximum performance. The peripherals might have more awareness, say LTDC, so that the fetches/fifo are somewhat more optimal.

The STM32 pin aren't generally architected to go >100 MHz

What ST pays for SDRAM, and the partnerships they have, is more likely a driver as to what parts they use, vs your options. Similarly it's the reason they use half of a 32-bit wide device, because it's a higher volume, common foot-print, with potentially more secondary sources, or adds to volume of a common part.

[regjoe · Accepted solution]

I'm not sure if I fully understand your answer regarding tAC.

According to your definition, access time is the time span between the rising edge of the first CL and the first rising edge after the last CL cycle.

Regarding the reference manual, the FMC expects data to be valid somewhat earlier, minus the tSU time.

 For example, at 100MHz and CL=2 data must be valid at least 2x10ns - 3ns = 17ns.

Regarding the datasheet of the H753, the data must be available 3ns before the rising clock after the last CL.

This timing diagram implies that data must be available at least 7ns after the rising edge of the last CL, even if CL=1. This means to me that at 100 MHz even a single CL cycle would be sufficient to fulfil this requirement.

IMHO all of the named SDRAMs, no matter which speed option is used and how many CL cycles are inserted, can be used with H7 running FMC at 100 MHz?

EDIT1: 

Except for the AM -7 which requires a minimum clock cycle time of 20ns / 50 MHz at CL=1

EDIT2:

I got a response from ISSI. All of their SDRAMs -5, -6, -7 should work for the H7 at 100MHz and CAS=2 or 3.