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I have a custom board with an STM32G051. The STM32 is a SPI receive only device. PA1 is SCLK, PA2 is MOSI, PB0 is nSS (which is hardware controlled). The beginnings of the project where created with CubeMX so the clocks should all be set correctly...
i have written a driver code to run 4 wire resistive touch panel. I use only 1 adc and change its adc channel during runtime. Like i set X+ and Y+ as output high by default and X- and Y- set as low by default and set X- and y- pull down to make ADC r...
Post edited by ST moderator to be inline with the community rules for the code sharing. In next time please use </> button to paste your code and a linker script content. Please read this post: How to insert source code. I have a STM32L433RCT3 and I'...
Hello everyone,We are experiencing an issue with a product that integrates an STM32H562ZG microcontroller.Our development environment consists of IAR Embedded Workbench 9.70.1, with the project configured using CMake.Currently, we are observing unexp...
Hello! I need help. STM32L073RZT6 MCU.How can I write, for example, 2 times 8 Bytes into any second half-page of flash memory?Every first page is recorded successfully and read successfully. For example, I write 8 Bytes of data to the beginning of th...
Both in the manual and in CubeMX, it is shown that my microcontroller, has the ability to configure the FMC, for an asynchronous muxed PSRAM interface.However, in the manual I can only find the timing description for the asynchronous NOR Flash and fo...
Hi.I am trying to test out a fault handler for our STM32G (right now, the fault handler just tries to determine the location of the code that caused the fault).If I force a fault (divide by zero) in "normal" non-interrupt handler code, I can easily r...
I am experiencing an issue when trying to use STOP3 mode on an STM32U575VIT6Q device mounted on a custom PCB. In fact, the MCU never seems to actually enter STOP3, even though I explicitly call:HAL_SuspendTick(); HAL_PWREx_EnterSTOP3Mode(PWR_STOPENTR...
In the lower-end STM32L4, covered by RM0394, SRAM is partitioned into two parts, SRAM1 and SRAM2.SRAM2 (besides being "special" in that it has ECC and automatic erase facities), is mapped at both 0x1000'0000 and at the end of SRAM1 in the 0x200x'xxxx...
