Ask questions, find answers, and share insights on STM32 products and their technical features.
Hello all,We are testing LPUART wake-up from Stop 2 mode using the STM32CubeU0 LL example:STM32Cube_FW_U0_V1.2.0/Projects/NUCLEOU083RC/Examples_LL/LPUART/LPUART_WakeUpFromStop2_InitWe made a minimal modification to the example:Replaced LPUART1 with L...
For the microcontroller STM32H562IIT6, does it support code execution from External flash(Xip)? Also does it support Quadspi interfacing in given Octospi lines?
Is the flash dual-BANK feature of H563 enabled by default? How to switch banks
Hello,I was trying to implement extended calibration for ADC1 on my STM32U575 according to RM0456 Rev 5. I have a revision ID 0x3001 chip which should support extended calibration. The chip would hang very badly (can no longer connect with debug pr...
hiim trying to design ADC module with STM32L452.in datasheet table 77, t_s must be 0.03125us - 8.00625us when f_ADC is 80MHzbut in table 78 the range of sampling time is 32.25ns - 8006.75ns.isnt it must be 8006.25ns?
Can the STM32G031Y8Y6TR be subjected to ultrasonic cleaning after being mounted on the board? Are there any internal structures that do not allow ultrasonic cleaning?1. **Cleaning agents**: ST-240KKA or pure water2. **Temperature**: 55°C or below3.**...
Why is it that when I set the clock frequency of the STM32 to a high frequency (180 MHz), the code will crash, but when I set it to a low frequency (72 MHz), the code can run normally?
Hello everyone, I'm having some trouble implementing I3C communication and would like to ask for some help. I am using the NUCLEO-H503RB board as my main controller. For the target devices, I have the NUCLEO-IKS01A3 expansion board and the TSC1641 (C...
Hi all,In my project I use several IOs, I2C, SPI, UART, ADC, DAC and most of them work as expected.However, I have 2 inputs from push buttons (pushing the button would set them to 0 volt), set with pull-ups (not set as EXTI) that sometimes stop worki...
The VENC peripheral on the N6 boasts a hardware handshake path with the DCMIPP peripheral, potentially allowing full compression of each frame to occur with very little active RAM. From what I can find, the DCMIPP capture starts, then the VENC is tol...
