ADC on STM32L152rct6 to wake up from Sleep
What is the process to use the ADC on STM32L152rct6 to wake up the micro from Sleep?
STM32 MCUs Products
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Resolved! GPDMA Linked List in Secure code on STM32N6
Hi,The example for FSBL works as describedhttps://community.st.com/t5/stm32-mcus/how-to-configure-the-linked-list-mode-in-stm32cubemx/ta-p/693779But if the same approach is applied to Appli (Secure) code, the "User Setting Error" raised in DMA IRQ.I ...
STM32H7S: External Memory Loader / manager and Independant SDRAM
Hey everyone,I'm currently working with the STM32H7S78-DK.I'm trying to set up an external memory loader project, executing code from external memory with XIP, while also partitioning out the SDRAM in a few different addressable chunks in the memory ...
Resolved! STM32H757 Uses FMC SDRam Bank 1 and FMC SRam 1 at the same time.
Hi,while I'm configuring the FMC interface i come cross this memory map and i couldn't understand it. Does the FMC SDRAM Bank 1 have 4 possible regions? if yes, does SDRAM Bank 2 have the same option.what about the External Memory region, are those f...
Resolved! STM32N657xx Timer Clock(s)
I am confused about which clock(s) drive the timers. In the reference manual is says the APB clock drives the timers but there are 5 APB clocks. Also, in STM32CubeMX there is a "Timer Group Clocks". What clocks drive which timers or is the one dri...
Resolved! Failure on GO Command of STM32G070
I have questions on the System Memory Boot Mode of the STM32G070CB MCUSetup:Access the System Memory Bootloader Mode every power cycle. Hence, I updated the Option Bytes as below:The MCU contains the Application image only; it does not contain a cust...
EXTI Edge Detection Characteristic for STM32H7 - rise/fall time?
I am trying to detect both rising and falling edges on a GPIO input using EXTI.I am using a STM32H755 (144 pin) - SYSCLK is 400MHz, but I am using the CM4 core, so the CPU clock is 200MHz. APB Timer clock is also 200MHz.The signal I am monitoring is ...
How to unbrick STM32C0
How to unbrick a C0 if user firmware reprograms SWD pins as IO? Because by default BOOT0 pin is disabled so there's no way to enter the bootloader unless it's enabled in OPTIONS bytes. I've added a failsafe 2 second delay at bootup before running any...
The F429 uses both SDRAM and SRAM
Whether the two buses can be used at the same time？ Winbond's SDRAM is used to find a high probability of reading and writing errors in SDRAM data。 but there is no problem with using ISSI. If you don't read or write to the external SRAM, it's fine。
Resolved! PDM microphone and filter options
I have compared my platforms using PDM microphones related to PDM to PCM and filtering:Platform 1:STM32H747 (Portenta H7), with SW PDM2PCM filter (and optional to add post-processing)Platform 2:STM32U5A5 with ADF filter (in MCU) or external PCMD3180 ...
