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Hello, I am fighting about a week to enable USB-PD comms on my STM32G0B1 MCU and even chat GPT literally told me - he don't have a solution ( shock, a?) One last try before I quit, is to try 1.5.0 package version but I can see in cube MX only 1.6.0 ...
For H7, the kernel clock limit are given in Table 61 Kernel clock distribution overview as shown inhttps://community.st.com/t5/stm32cubemx-mcus/stm32h745-fdcan-clock-frequency/td-p/83540I do not find a similar table for U5 in the most recent datashee...
The STM32H753 Reference Manual (RM0433) covers the integrated flash memory inside the microcontroller. It does not say why type of flash is integrated though (NOR or NAND). Is it possible to share what type of flash it is?
In STM32G474 UART4 pin no PC11(Rx) is 5 Volt tolerant . If I pull up this pin to +5V with 4.7kOhms then it will affect life or operation of microcontroller? please Suggest.
Hello everyI want to increase STM32G473 FDCAN Tx buffer and Rx buffer size,In STM32G473 datasheet >> "A 3-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers. This message RAM is shar...
Bit-banding Alternatives for Modern ARM Cores Background Information: The bit-banding feature available in ARM Cortex-M cores (ARMv7-M architecture including Cortex-M3 and Cortex-M4) provides hardware-level mapping of individual bits within a 1 MB me...
Hi, Has anyone managed to Trigger Timer 2(Combined PWM Mode, One-Pulse) with Internal Trigger 3(ITR3). The TIM14 OC1 waveform is the trigger. When I run Timer 14 in output compare mode, with an active level on match between Couner and CCR1. I cannot...
I am able to do a line reset, enter into JTAG_SWD mode and read the SWD_ID. I want to know how to configure the core registers for SWD initialization process.
I can't decipher the silkscreen markings on this chip. Could you please help me confirm?This chip looks like it's from ST, but I didn't see the ST logo. I suspect it's an abbreviation for STM32G473ME, but I can't confirm it, and the chip's datasheet ...
I'm working with the STM32U5G9, trying to configure access to internal RAM blocks with TrustZone enabled. Part of this configuration uses the HAL_GTZC_MPCBB_ConfigMem() function from stm32u5xx_hal_gtzc.c from STM32CubeU5 v1.7.0.I see in that functio...
