Ask questions, find answers, and share insights on STM32 products and their technical features.
Hello, I found in the documentation search for STM32U5G9 that some interfaces available for high-speed communication, such as OctoSPI and HexaSPI, do not seem to support slave mode. The device we are making requires two STM32U5G9 chips, each connecte...
Hi!I’m currently building an application where I need to periodically wake up my NUCLEO-U575ZI-Q from Standby mode using RTC alarms. I’m aware of the Wake-Up Timers, but I’ve been specifically asked to use alarms. This will be integrated into a FreeR...
Hello, I am working with the STM32H747I microcontroller and using the SPI6 peripheral to interface with an external ADC (MCP3462RT). I have observed that when the system clock (SYSCLK) is set to 120 MHz, SPI6 communication works correctly and the ADC...
Hi, When I clear the EXTSEL bits in the ADC1 CFGR1 register, my resolution bits also get cleared ?. My ADC randomly changes resolution. Below is screenshots of the code. Why does this happen ?, I can disable the ADC to write the RES bits to what th...
Hello community,I am running in an issue with the VREFINT calibration value of the ADC.For calculation I use the __LL_ADC_CALC_VREFANALOG_VOLTAGE function from the stm32u0xx_ll_adc.h file and I'm getting wrong values.The Chip is powered with 3.3V and...
Hi,We've successfully implemented the use of external RAM connected via the OCTOSPI1 interface on the B-U585I-IOT02A board, using the example code provided in the CubeMX packages for read/write operations. Everything works as expected under normal co...
hi:I have two NUCLEO-H563ZI EVB boards and tried to implement I3C controller and target feature.When ENTDAA was issued, I obtained the target 48-bit provisioned ID "0x020813810100" from waveform, I saw the description from I3C register I3C_EPIDR ,i...
Hi, @FBL I am also using this board and STM32Cube_FW_U5_V1.8.0 to create a USBX stand-alone (without THREADX) MSC device,but struggling to get the board to enumerate with the PC.I'm not sure if it's a configuration issue or a code modification probl...
Hi all, i am going through deeper configuration of GPDMA on STM32U5 and there are some things i do not understand.S/DBL_1 in TR1 register is able to vrite destination/source burst length in range 0-63 but FIFO size is 8 bytes for channels 0-11 and 32...
Is there a way to set the FDCAN TX and RX FIFO sizes for STM32H7R7 in CubeIDE?I snooped around and found a list of macros that are responsible for determining the FDCAN RAM size in the stm32h7rsxx_hal_fdcan.c. Do I just modify these values to set the...
