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Hi Team,I have few questions regarding stm32h7 errata.Errata 2.2.21, Can silicon revision 'V' support a cpu frequency of 480 Mhz ? If yes, why is it showing 'P' for v revision. 2. Can I please ask if there is a fix in the HAL for the below given S...
I'm bringing up a design based off the STM32H573 and I believe I'm having a number of issues that are probably sharing a common thread with bad hardware. I don't usually screw those things up, but I guess I got unlucky this time.1) PC1 when configure...
HI USB-C Input (5–20 V PD) + USB-C Data (USB2.0 D+/D– to STM32H745) + charging phone at same time + Audio data transfer Problem: When I connect the USB-C input supply (PD 5–20 V), the phone only charges and the audio USB port does NOT appear.But when...
Hello everyone,This is my first post on the platform, so please bear with me.I would like to write raw data to an SD card very quickly.After quite a bit of research, I decided to use SDMMC with MDMA, and I want to write directly to the SD card blocks...
I'm trying to port a proprietary code that is designed for another STM32H753 plateform, to a STM32H753-EVAL board.My code remains stuck waiting for HSERDY bit.The setup I am doing looks identical to STM32CubeHW example but I guess I forgot something:...
I want to use N657B0 to drive VD55G0, and the camera side can already enter the Stream state. After I use the function HAL_DCMIPP_CSI_PIPE_Start, I track the variable csi_instance through single-step debugging and find that several bits in its SR1 re...
I have a STM32U595 and I use the RTC in binary mode.If an SSR underflow occurs during Vbat mode, will the SSRUF be set so after power recovery I can manage the interrupt ?
From my understanding all STM32N6 chips need a external flash chip and there's a static stage 0 boot loader. So if this is true is there any limitation's on the brands of flash or speed/address bit size limitations? With the previous stage 0 bootloa...
Hi Everyone,I am working on a project with TouchGFX. I'm working with STM32U5G9ZJT6 and I have an external RAM APS12808L-OBM-BA connected via HSPI (Fclk-hspi 100 MHz) in mapped mode. The project is working, but the image animation are not working wel...
In the RM0456 at 33.4.31 Oversampler it say:The division coefficient M consists of a right bit shift up to 10 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.But at 33.6.5 ADC configuration register 2 (ADC_CFGR2), it allow up ...
