Hi, @B.Montanari We are working with the STM32N6570-DK EVK and developing an application that includes both a Bootloader and an Application. The application requires a contiguous 4MB+ memory block configured as a Heap.We have followed your articles a...
Hi,I am trying to interface Stm32h745 controller with a 240x320 TFT LCD over FMC. Interesting thing is, when I manually control lcd control and data pins(Set them as GPIO_OUTPUT_PP), Lcd works, but when I switched to FMC it does not. Tried lots of ti...
Originally a comment on the How to redirect the printf function to a UART for debug messages Knowledge Base article.Moved to main forum for better visibility & discussion Hello @ST AME Support NF ,I have tried example code...\Repository\STM32Cube_FW_...
I want to connect my STM32H573I-DK to Azure IoT Hub via MQTT over websocket to avoid firewall complications.For that I am using STM32CubeExpansion_Cloud_AZURE_H5_V1.1.0 project (https://www.st.com/en/embedded-software/x-cube-azure-h5.html). I added N...
Hello everyone,I use the NUCLEO-H743ZI2 board in my project and previously, Before I've used the MBed OS - it works well on this board, just I need to maximize TCP transfer speed as well as QSPI. So I decided to try another RTOS. After reading forums...
Hello,I need to connect SD card to STM32H5 device. CubeMX does not support fatfs I was using in the past, but only ThreadX and FileX. We decided to use this as STM32H5 seems like a good choice for many future projects.So we connected the SD via SPI.M...
Hello,This is assuming STM32G0 with SPI configured as slave. I'm looking for a way to detect if a ongoing SPI transfer is happening. Not at the byte level but at the bit level.So I can detect if some incomplete byte is pending in the RX buffer (due t...
Hello ST Community, I am trying to set up SPI communication between two STM32 microcontrollers (two NUCLEO-F401RE boards); one as an SPI master and the other as an SPI slave. For now, I am only trying to transmit only one byte (0x61). For this I am u...
Hello,I was looking at the UsbX middleware source code and noticed that the memory pools are split in 2. a) non-cached memory poolb) cached memory poolThe STM implementation doesn't seem to use this code and just places everything into the non-cached...
How does the bootloader in the STM32C071 system memory generate its 12-character USB serial number string descriptor (e.g. "205537C24236")? I notice some similarities between this serial number and the 96-bit unique device ID at address 0x1FFF7550, ...
