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SRAM faut injection

stefanodimascio9
Associate II
Posted on December 11, 2015 at 11:31

Hello everybody,

I'm working on the SPC56EL70L5

From the reference manual, I know that:

“For platform RAM, the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections or double-bit non-correctable errors that are terminated with an error response.�?

So, I coded (I put the related assembly too):

SPP_MCM.ECR.R=0x33;  \\to activate reportings

0x00001D7E:   70 1F E7 F4  E_LIS     R0,0xFFF4

0x00001D82:   4B 37        SE_LI     R7,0x33

0x00001D84:   01 06        SE_MR     R6,R0

0x00001D86:   34 E6 00 43  E_STB     R7,0x43(R6)

SPP_MCM.EEGR.B.FR11BI=1;   \\ injection

0x00001D8A:   70 FF E7 F4  E_LIS     R7,0xFFF4

0x00001D8E:   50 07 00 48  E_LWZ     R0,0x48(R7)  

0x00001D92:   48 16        SE_LI     R6,0x1

0x00001D94:   74 C0 64 E6  E_RLWIMI  R0,R6,0xC,0x13,0x13

0x00001D98:   54 07 00 48  E_STW     R0,0x48(R7)

But, execution of instruction at 0x00001D8E causes hangs in

_unhandled_exception:0x000003A0:   78 00 00 00  E_B       _unhandled_exception (0x000003A0))

This is not the expected behavior, what is going wrong?

Thanks in advance for the help
2 REPLIES 2
Erwan YVIN
ST Employee
Posted on December 14, 2015 at 15:45

Hello Stefano ,

It is linked to the compiler optimization. to set a bitfield is not recommended in some compilers. I recommend to use the register directly :

// Force RAM One 1-bit Data Inversion
#define ECSM_EEGR_FR11BI_MASK 0x1000
 /* Force internal SRAM one 1-bit correctable data error */
 SPP_MCM.EEGR.R = (uint16_t)(ECSM_EEGR_FR11BI_MASK | 0); 

Best regards Erwan
stefanodimascio9
Associate II
Posted on December 16, 2015 at 12:40

Thank you, it worked.

Best Regards