temp1.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001f8 08020000 08020000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000020b0 080201f8 080201f8 000101f8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000010 080222a8 080222a8 000122a8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080222b8 080222b8 0002000c 2**0 CONTENTS 4 .ARM 00000008 080222b8 080222b8 000122b8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080222c0 080222c0 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080222c0 080222c0 000122c0 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080222c4 080222c4 000122c4 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 080222c8 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 2000000c 080222d4 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000002c 080222d4 0002002c 2**0 ALLOC 11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 0000784c 00000000 00000000 0002003a 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 00001471 00000000 00000000 00027886 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 000005d0 00000000 00000000 00028cf8 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000518 00000000 00000000 000292c8 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00026f44 00000000 00000000 000297e0 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 00006a1e 00000000 00000000 00050724 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 000f663e 00000000 00000000 00057142 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 0014d780 2**0 CONTENTS, READONLY 20 .debug_frame 00001530 00000000 00000000 0014d7fc 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080201f8 <__do_global_dtors_aux>: 80201f8: b510 push {r4, lr} 80201fa: 4c05 ldr r4, [pc, #20] ; (8020210 <__do_global_dtors_aux+0x18>) 80201fc: 7823 ldrb r3, [r4, #0] 80201fe: b933 cbnz r3, 802020e <__do_global_dtors_aux+0x16> 8020200: 4b04 ldr r3, [pc, #16] ; (8020214 <__do_global_dtors_aux+0x1c>) 8020202: b113 cbz r3, 802020a <__do_global_dtors_aux+0x12> 8020204: 4804 ldr r0, [pc, #16] ; (8020218 <__do_global_dtors_aux+0x20>) 8020206: f3af 8000 nop.w 802020a: 2301 movs r3, #1 802020c: 7023 strb r3, [r4, #0] 802020e: bd10 pop {r4, pc} 8020210: 2000000c .word 0x2000000c 8020214: 00000000 .word 0x00000000 8020218: 08022290 .word 0x08022290 0802021c : 802021c: b508 push {r3, lr} 802021e: 4b03 ldr r3, [pc, #12] ; (802022c ) 8020220: b11b cbz r3, 802022a 8020222: 4903 ldr r1, [pc, #12] ; (8020230 ) 8020224: 4803 ldr r0, [pc, #12] ; (8020234 ) 8020226: f3af 8000 nop.w 802022a: bd08 pop {r3, pc} 802022c: 00000000 .word 0x00000000 8020230: 20000010 .word 0x20000010 8020234: 08022290 .word 0x08022290 08020238 <__aeabi_uldivmod>: 8020238: b953 cbnz r3, 8020250 <__aeabi_uldivmod+0x18> 802023a: b94a cbnz r2, 8020250 <__aeabi_uldivmod+0x18> 802023c: 2900 cmp r1, #0 802023e: bf08 it eq 8020240: 2800 cmpeq r0, #0 8020242: bf1c itt ne 8020244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff 8020248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 802024c: f000 b972 b.w 8020534 <__aeabi_idiv0> 8020250: f1ad 0c08 sub.w ip, sp, #8 8020254: e96d ce04 strd ip, lr, [sp, #-16]! 8020258: f000 f806 bl 8020268 <__udivmoddi4> 802025c: f8dd e004 ldr.w lr, [sp, #4] 8020260: e9dd 2302 ldrd r2, r3, [sp, #8] 8020264: b004 add sp, #16 8020266: 4770 bx lr 08020268 <__udivmoddi4>: 8020268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 802026c: 9e08 ldr r6, [sp, #32] 802026e: 4604 mov r4, r0 8020270: 4688 mov r8, r1 8020272: 2b00 cmp r3, #0 8020274: d14b bne.n 802030e <__udivmoddi4+0xa6> 8020276: 428a cmp r2, r1 8020278: 4615 mov r5, r2 802027a: d967 bls.n 802034c <__udivmoddi4+0xe4> 802027c: fab2 f282 clz r2, r2 8020280: b14a cbz r2, 8020296 <__udivmoddi4+0x2e> 8020282: f1c2 0720 rsb r7, r2, #32 8020286: fa01 f302 lsl.w r3, r1, r2 802028a: fa20 f707 lsr.w r7, r0, r7 802028e: 4095 lsls r5, r2 8020290: ea47 0803 orr.w r8, r7, r3 8020294: 4094 lsls r4, r2 8020296: ea4f 4e15 mov.w lr, r5, lsr #16 802029a: 0c23 lsrs r3, r4, #16 802029c: fbb8 f7fe udiv r7, r8, lr 80202a0: fa1f fc85 uxth.w ip, r5 80202a4: fb0e 8817 mls r8, lr, r7, r8 80202a8: ea43 4308 orr.w r3, r3, r8, lsl #16 80202ac: fb07 f10c mul.w r1, r7, ip 80202b0: 4299 cmp r1, r3 80202b2: d909 bls.n 80202c8 <__udivmoddi4+0x60> 80202b4: 18eb adds r3, r5, r3 80202b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff 80202ba: f080 811b bcs.w 80204f4 <__udivmoddi4+0x28c> 80202be: 4299 cmp r1, r3 80202c0: f240 8118 bls.w 80204f4 <__udivmoddi4+0x28c> 80202c4: 3f02 subs r7, #2 80202c6: 442b add r3, r5 80202c8: 1a5b subs r3, r3, r1 80202ca: b2a4 uxth r4, r4 80202cc: fbb3 f0fe udiv r0, r3, lr 80202d0: fb0e 3310 mls r3, lr, r0, r3 80202d4: ea44 4403 orr.w r4, r4, r3, lsl #16 80202d8: fb00 fc0c mul.w ip, r0, ip 80202dc: 45a4 cmp ip, r4 80202de: d909 bls.n 80202f4 <__udivmoddi4+0x8c> 80202e0: 192c adds r4, r5, r4 80202e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 80202e6: f080 8107 bcs.w 80204f8 <__udivmoddi4+0x290> 80202ea: 45a4 cmp ip, r4 80202ec: f240 8104 bls.w 80204f8 <__udivmoddi4+0x290> 80202f0: 3802 subs r0, #2 80202f2: 442c add r4, r5 80202f4: ea40 4007 orr.w r0, r0, r7, lsl #16 80202f8: eba4 040c sub.w r4, r4, ip 80202fc: 2700 movs r7, #0 80202fe: b11e cbz r6, 8020308 <__udivmoddi4+0xa0> 8020300: 40d4 lsrs r4, r2 8020302: 2300 movs r3, #0 8020304: e9c6 4300 strd r4, r3, [r6] 8020308: 4639 mov r1, r7 802030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 802030e: 428b cmp r3, r1 8020310: d909 bls.n 8020326 <__udivmoddi4+0xbe> 8020312: 2e00 cmp r6, #0 8020314: f000 80eb beq.w 80204ee <__udivmoddi4+0x286> 8020318: 2700 movs r7, #0 802031a: e9c6 0100 strd r0, r1, [r6] 802031e: 4638 mov r0, r7 8020320: 4639 mov r1, r7 8020322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8020326: fab3 f783 clz r7, r3 802032a: 2f00 cmp r7, #0 802032c: d147 bne.n 80203be <__udivmoddi4+0x156> 802032e: 428b cmp r3, r1 8020330: d302 bcc.n 8020338 <__udivmoddi4+0xd0> 8020332: 4282 cmp r2, r0 8020334: f200 80fa bhi.w 802052c <__udivmoddi4+0x2c4> 8020338: 1a84 subs r4, r0, r2 802033a: eb61 0303 sbc.w r3, r1, r3 802033e: 2001 movs r0, #1 8020340: 4698 mov r8, r3 8020342: 2e00 cmp r6, #0 8020344: d0e0 beq.n 8020308 <__udivmoddi4+0xa0> 8020346: e9c6 4800 strd r4, r8, [r6] 802034a: e7dd b.n 8020308 <__udivmoddi4+0xa0> 802034c: b902 cbnz r2, 8020350 <__udivmoddi4+0xe8> 802034e: deff udf #255 ; 0xff 8020350: fab2 f282 clz r2, r2 8020354: 2a00 cmp r2, #0 8020356: f040 808f bne.w 8020478 <__udivmoddi4+0x210> 802035a: 1b49 subs r1, r1, r5 802035c: ea4f 4e15 mov.w lr, r5, lsr #16 8020360: fa1f f885 uxth.w r8, r5 8020364: 2701 movs r7, #1 8020366: fbb1 fcfe udiv ip, r1, lr 802036a: 0c23 lsrs r3, r4, #16 802036c: fb0e 111c mls r1, lr, ip, r1 8020370: ea43 4301 orr.w r3, r3, r1, lsl #16 8020374: fb08 f10c mul.w r1, r8, ip 8020378: 4299 cmp r1, r3 802037a: d907 bls.n 802038c <__udivmoddi4+0x124> 802037c: 18eb adds r3, r5, r3 802037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff 8020382: d202 bcs.n 802038a <__udivmoddi4+0x122> 8020384: 4299 cmp r1, r3 8020386: f200 80cd bhi.w 8020524 <__udivmoddi4+0x2bc> 802038a: 4684 mov ip, r0 802038c: 1a59 subs r1, r3, r1 802038e: b2a3 uxth r3, r4 8020390: fbb1 f0fe udiv r0, r1, lr 8020394: fb0e 1410 mls r4, lr, r0, r1 8020398: ea43 4404 orr.w r4, r3, r4, lsl #16 802039c: fb08 f800 mul.w r8, r8, r0 80203a0: 45a0 cmp r8, r4 80203a2: d907 bls.n 80203b4 <__udivmoddi4+0x14c> 80203a4: 192c adds r4, r5, r4 80203a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 80203aa: d202 bcs.n 80203b2 <__udivmoddi4+0x14a> 80203ac: 45a0 cmp r8, r4 80203ae: f200 80b6 bhi.w 802051e <__udivmoddi4+0x2b6> 80203b2: 4618 mov r0, r3 80203b4: eba4 0408 sub.w r4, r4, r8 80203b8: ea40 400c orr.w r0, r0, ip, lsl #16 80203bc: e79f b.n 80202fe <__udivmoddi4+0x96> 80203be: f1c7 0c20 rsb ip, r7, #32 80203c2: 40bb lsls r3, r7 80203c4: fa22 fe0c lsr.w lr, r2, ip 80203c8: ea4e 0e03 orr.w lr, lr, r3 80203cc: fa01 f407 lsl.w r4, r1, r7 80203d0: fa20 f50c lsr.w r5, r0, ip 80203d4: fa21 f30c lsr.w r3, r1, ip 80203d8: ea4f 481e mov.w r8, lr, lsr #16 80203dc: 4325 orrs r5, r4 80203de: fbb3 f9f8 udiv r9, r3, r8 80203e2: 0c2c lsrs r4, r5, #16 80203e4: fb08 3319 mls r3, r8, r9, r3 80203e8: fa1f fa8e uxth.w sl, lr 80203ec: ea44 4303 orr.w r3, r4, r3, lsl #16 80203f0: fb09 f40a mul.w r4, r9, sl 80203f4: 429c cmp r4, r3 80203f6: fa02 f207 lsl.w r2, r2, r7 80203fa: fa00 f107 lsl.w r1, r0, r7 80203fe: d90b bls.n 8020418 <__udivmoddi4+0x1b0> 8020400: eb1e 0303 adds.w r3, lr, r3 8020404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff 8020408: f080 8087 bcs.w 802051a <__udivmoddi4+0x2b2> 802040c: 429c cmp r4, r3 802040e: f240 8084 bls.w 802051a <__udivmoddi4+0x2b2> 8020412: f1a9 0902 sub.w r9, r9, #2 8020416: 4473 add r3, lr 8020418: 1b1b subs r3, r3, r4 802041a: b2ad uxth r5, r5 802041c: fbb3 f0f8 udiv r0, r3, r8 8020420: fb08 3310 mls r3, r8, r0, r3 8020424: ea45 4403 orr.w r4, r5, r3, lsl #16 8020428: fb00 fa0a mul.w sl, r0, sl 802042c: 45a2 cmp sl, r4 802042e: d908 bls.n 8020442 <__udivmoddi4+0x1da> 8020430: eb1e 0404 adds.w r4, lr, r4 8020434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 8020438: d26b bcs.n 8020512 <__udivmoddi4+0x2aa> 802043a: 45a2 cmp sl, r4 802043c: d969 bls.n 8020512 <__udivmoddi4+0x2aa> 802043e: 3802 subs r0, #2 8020440: 4474 add r4, lr 8020442: ea40 4009 orr.w r0, r0, r9, lsl #16 8020446: fba0 8902 umull r8, r9, r0, r2 802044a: eba4 040a sub.w r4, r4, sl 802044e: 454c cmp r4, r9 8020450: 46c2 mov sl, r8 8020452: 464b mov r3, r9 8020454: d354 bcc.n 8020500 <__udivmoddi4+0x298> 8020456: d051 beq.n 80204fc <__udivmoddi4+0x294> 8020458: 2e00 cmp r6, #0 802045a: d069 beq.n 8020530 <__udivmoddi4+0x2c8> 802045c: ebb1 050a subs.w r5, r1, sl 8020460: eb64 0403 sbc.w r4, r4, r3 8020464: fa04 fc0c lsl.w ip, r4, ip 8020468: 40fd lsrs r5, r7 802046a: 40fc lsrs r4, r7 802046c: ea4c 0505 orr.w r5, ip, r5 8020470: e9c6 5400 strd r5, r4, [r6] 8020474: 2700 movs r7, #0 8020476: e747 b.n 8020308 <__udivmoddi4+0xa0> 8020478: f1c2 0320 rsb r3, r2, #32 802047c: fa20 f703 lsr.w r7, r0, r3 8020480: 4095 lsls r5, r2 8020482: fa01 f002 lsl.w r0, r1, r2 8020486: fa21 f303 lsr.w r3, r1, r3 802048a: ea4f 4e15 mov.w lr, r5, lsr #16 802048e: 4338 orrs r0, r7 8020490: 0c01 lsrs r1, r0, #16 8020492: fbb3 f7fe udiv r7, r3, lr 8020496: fa1f f885 uxth.w r8, r5 802049a: fb0e 3317 mls r3, lr, r7, r3 802049e: ea41 4103 orr.w r1, r1, r3, lsl #16 80204a2: fb07 f308 mul.w r3, r7, r8 80204a6: 428b cmp r3, r1 80204a8: fa04 f402 lsl.w r4, r4, r2 80204ac: d907 bls.n 80204be <__udivmoddi4+0x256> 80204ae: 1869 adds r1, r5, r1 80204b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff 80204b4: d22f bcs.n 8020516 <__udivmoddi4+0x2ae> 80204b6: 428b cmp r3, r1 80204b8: d92d bls.n 8020516 <__udivmoddi4+0x2ae> 80204ba: 3f02 subs r7, #2 80204bc: 4429 add r1, r5 80204be: 1acb subs r3, r1, r3 80204c0: b281 uxth r1, r0 80204c2: fbb3 f0fe udiv r0, r3, lr 80204c6: fb0e 3310 mls r3, lr, r0, r3 80204ca: ea41 4103 orr.w r1, r1, r3, lsl #16 80204ce: fb00 f308 mul.w r3, r0, r8 80204d2: 428b cmp r3, r1 80204d4: d907 bls.n 80204e6 <__udivmoddi4+0x27e> 80204d6: 1869 adds r1, r5, r1 80204d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff 80204dc: d217 bcs.n 802050e <__udivmoddi4+0x2a6> 80204de: 428b cmp r3, r1 80204e0: d915 bls.n 802050e <__udivmoddi4+0x2a6> 80204e2: 3802 subs r0, #2 80204e4: 4429 add r1, r5 80204e6: 1ac9 subs r1, r1, r3 80204e8: ea40 4707 orr.w r7, r0, r7, lsl #16 80204ec: e73b b.n 8020366 <__udivmoddi4+0xfe> 80204ee: 4637 mov r7, r6 80204f0: 4630 mov r0, r6 80204f2: e709 b.n 8020308 <__udivmoddi4+0xa0> 80204f4: 4607 mov r7, r0 80204f6: e6e7 b.n 80202c8 <__udivmoddi4+0x60> 80204f8: 4618 mov r0, r3 80204fa: e6fb b.n 80202f4 <__udivmoddi4+0x8c> 80204fc: 4541 cmp r1, r8 80204fe: d2ab bcs.n 8020458 <__udivmoddi4+0x1f0> 8020500: ebb8 0a02 subs.w sl, r8, r2 8020504: eb69 020e sbc.w r2, r9, lr 8020508: 3801 subs r0, #1 802050a: 4613 mov r3, r2 802050c: e7a4 b.n 8020458 <__udivmoddi4+0x1f0> 802050e: 4660 mov r0, ip 8020510: e7e9 b.n 80204e6 <__udivmoddi4+0x27e> 8020512: 4618 mov r0, r3 8020514: e795 b.n 8020442 <__udivmoddi4+0x1da> 8020516: 4667 mov r7, ip 8020518: e7d1 b.n 80204be <__udivmoddi4+0x256> 802051a: 4681 mov r9, r0 802051c: e77c b.n 8020418 <__udivmoddi4+0x1b0> 802051e: 3802 subs r0, #2 8020520: 442c add r4, r5 8020522: e747 b.n 80203b4 <__udivmoddi4+0x14c> 8020524: f1ac 0c02 sub.w ip, ip, #2 8020528: 442b add r3, r5 802052a: e72f b.n 802038c <__udivmoddi4+0x124> 802052c: 4638 mov r0, r7 802052e: e708 b.n 8020342 <__udivmoddi4+0xda> 8020530: 4637 mov r7, r6 8020532: e6e9 b.n 8020308 <__udivmoddi4+0xa0> 08020534 <__aeabi_idiv0>: 8020534: 4770 bx lr 8020536: bf00 nop 08020538 : /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_INLINE void SCB_EnableICache (void) { 8020538: b480 push {r7} 802053a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 802053c: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8020540: f3bf 8f6f isb sy #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8020544: 4b0b ldr r3, [pc, #44] ; (8020574 ) 8020546: 2200 movs r2, #0 8020548: f8c3 2250 str.w r2, [r3, #592] ; 0x250 __ASM volatile ("dsb 0xF":::"memory"); 802054c: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8020550: f3bf 8f6f isb sy __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 8020554: 4b07 ldr r3, [pc, #28] ; (8020574 ) 8020556: 695b ldr r3, [r3, #20] 8020558: 4a06 ldr r2, [pc, #24] ; (8020574 ) 802055a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 802055e: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8020560: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8020564: f3bf 8f6f isb sy __DSB(); __ISB(); #endif } 8020568: bf00 nop 802056a: 46bd mov sp, r7 802056c: f85d 7b04 ldr.w r7, [sp], #4 8020570: 4770 bx lr 8020572: bf00 nop 8020574: e000ed00 .word 0xe000ed00 08020578 : /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_INLINE void SCB_EnableDCache (void) { 8020578: b480 push {r7} 802057a: b085 sub sp, #20 802057c: af00 add r7, sp, #0 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 802057e: 4b1d ldr r3, [pc, #116] ; (80205f4 ) 8020580: 2200 movs r2, #0 8020582: f8c3 2084 str.w r2, [r3, #132] ; 0x84 __ASM volatile ("dsb 0xF":::"memory"); 8020586: f3bf 8f4f dsb sy __DSB(); ccsidr = SCB->CCSIDR; 802058a: 4b1a ldr r3, [pc, #104] ; (80205f4 ) 802058c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8020590: 607b str r3, [r7, #4] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 8020592: 687b ldr r3, [r7, #4] 8020594: 0b5b lsrs r3, r3, #13 8020596: f3c3 030e ubfx r3, r3, #0, #15 802059a: 60fb str r3, [r7, #12] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 802059c: 687b ldr r3, [r7, #4] 802059e: 08db lsrs r3, r3, #3 80205a0: f3c3 0309 ubfx r3, r3, #0, #10 80205a4: 60bb str r3, [r7, #8] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80205a6: 68fb ldr r3, [r7, #12] 80205a8: 015a lsls r2, r3, #5 80205aa: f643 73e0 movw r3, #16352 ; 0x3fe0 80205ae: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 80205b0: 68ba ldr r2, [r7, #8] 80205b2: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80205b4: 490f ldr r1, [pc, #60] ; (80205f4 ) 80205b6: 4313 orrs r3, r2 80205b8: f8c1 3260 str.w r3, [r1, #608] ; 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 80205bc: 68bb ldr r3, [r7, #8] 80205be: 1e5a subs r2, r3, #1 80205c0: 60ba str r2, [r7, #8] 80205c2: 2b00 cmp r3, #0 80205c4: d1ef bne.n 80205a6 } while(sets-- != 0U); 80205c6: 68fb ldr r3, [r7, #12] 80205c8: 1e5a subs r2, r3, #1 80205ca: 60fa str r2, [r7, #12] 80205cc: 2b00 cmp r3, #0 80205ce: d1e5 bne.n 802059c 80205d0: f3bf 8f4f dsb sy __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 80205d4: 4b07 ldr r3, [pc, #28] ; (80205f4 ) 80205d6: 695b ldr r3, [r3, #20] 80205d8: 4a06 ldr r2, [pc, #24] ; (80205f4 ) 80205da: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80205de: 6153 str r3, [r2, #20] 80205e0: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 80205e4: f3bf 8f6f isb sy __DSB(); __ISB(); #endif } 80205e8: bf00 nop 80205ea: 3714 adds r7, #20 80205ec: 46bd mov sp, r7 80205ee: f85d 7b04 ldr.w r7, [sp], #4 80205f2: 4770 bx lr 80205f4: e000ed00 .word 0xe000ed00 080205f8
: /** * @brief The application entry point. * @retval int */ int main(void) { 80205f8: b580 push {r7, lr} 80205fa: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ // /* Configure the MPU attributes as Device memory for ETH DMA descriptors */ // MPU_Config(); /* Enable the CPU Cache */ CPU_CACHE_Enable(); 80205fc: f000 f940 bl 8020880 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8020600: f000 f9df bl 80209c2 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8020604: f000 f80e bl 8020624 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8020608: f000 f8a2 bl 8020750 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { /* USER CODE END WHILE */ HAL_GPIO_TogglePin(GPIOB, LD3_Pin); 802060c: f44f 4180 mov.w r1, #16384 ; 0x4000 8020610: 4803 ldr r0, [pc, #12] ; (8020620 ) 8020612: f000 fcfe bl 8021012 HAL_Delay(249); 8020616: 20f9 movs r0, #249 ; 0xf9 8020618: f000 fa30 bl 8020a7c HAL_GPIO_TogglePin(GPIOB, LD3_Pin); 802061c: e7f6 b.n 802060c 802061e: bf00 nop 8020620: 40020400 .word 0x40020400 08020624 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8020624: b580 push {r7, lr} 8020626: b0b8 sub sp, #224 ; 0xe0 8020628: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 802062a: f107 03ac add.w r3, r7, #172 ; 0xac 802062e: 2234 movs r2, #52 ; 0x34 8020630: 2100 movs r1, #0 8020632: 4618 mov r0, r3 8020634: f001 fe24 bl 8022280 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8020638: f107 0398 add.w r3, r7, #152 ; 0x98 802063c: 2200 movs r2, #0 802063e: 601a str r2, [r3, #0] 8020640: 605a str r2, [r3, #4] 8020642: 609a str r2, [r3, #8] 8020644: 60da str r2, [r3, #12] 8020646: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8020648: f107 0308 add.w r3, r7, #8 802064c: 2290 movs r2, #144 ; 0x90 802064e: 2100 movs r1, #0 8020650: 4618 mov r0, r3 8020652: f001 fe15 bl 8022280 /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); 8020656: f000 fcf7 bl 8021048 /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 802065a: 4b3a ldr r3, [pc, #232] ; (8020744 ) 802065c: 6c1b ldr r3, [r3, #64] ; 0x40 802065e: 4a39 ldr r2, [pc, #228] ; (8020744 ) 8020660: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8020664: 6413 str r3, [r2, #64] ; 0x40 8020666: 4b37 ldr r3, [pc, #220] ; (8020744 ) 8020668: 6c1b ldr r3, [r3, #64] ; 0x40 802066a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 802066e: 607b str r3, [r7, #4] 8020670: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8020672: 4b35 ldr r3, [pc, #212] ; (8020748 ) 8020674: 681b ldr r3, [r3, #0] 8020676: f423 4340 bic.w r3, r3, #49152 ; 0xc000 802067a: 4a33 ldr r2, [pc, #204] ; (8020748 ) 802067c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8020680: 6013 str r3, [r2, #0] 8020682: 4b31 ldr r3, [pc, #196] ; (8020748 ) 8020684: 681b ldr r3, [r3, #0] 8020686: f403 4340 and.w r3, r3, #49152 ; 0xc000 802068a: 603b str r3, [r7, #0] 802068c: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 802068e: 2301 movs r3, #1 8020690: f8c7 30ac str.w r3, [r7, #172] ; 0xac RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8020694: f44f 23a0 mov.w r3, #327680 ; 0x50000 8020698: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 802069c: 2302 movs r3, #2 802069e: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80206a2: f44f 0380 mov.w r3, #4194304 ; 0x400000 80206a6: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 RCC_OscInitStruct.PLL.PLLM = 4; 80206aa: 2304 movs r3, #4 80206ac: f8c7 30cc str.w r3, [r7, #204] ; 0xcc RCC_OscInitStruct.PLL.PLLN = 96; 80206b0: 2360 movs r3, #96 ; 0x60 80206b2: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80206b6: 2302 movs r3, #2 80206b8: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 RCC_OscInitStruct.PLL.PLLQ = 4; 80206bc: 2304 movs r3, #4 80206be: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80206c2: f107 03ac add.w r3, r7, #172 ; 0xac 80206c6: 4618 mov r0, r3 80206c8: f000 fd1e bl 8021108 80206cc: 4603 mov r3, r0 80206ce: 2b00 cmp r3, #0 80206d0: d001 beq.n 80206d6 { Error_Handler(); 80206d2: f000 f8dd bl 8020890 } /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) 80206d6: f000 fcc7 bl 8021068 80206da: 4603 mov r3, r0 80206dc: 2b00 cmp r3, #0 80206de: d001 beq.n 80206e4 { Error_Handler(); 80206e0: f000 f8d6 bl 8020890 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80206e4: 230f movs r3, #15 80206e6: f8c7 3098 str.w r3, [r7, #152] ; 0x98 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80206ea: 2302 movs r3, #2 80206ec: f8c7 309c str.w r3, [r7, #156] ; 0x9c RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80206f0: 2300 movs r3, #0 80206f2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80206f6: f44f 5380 mov.w r3, #4096 ; 0x1000 80206fa: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80206fe: 2300 movs r3, #0 8020700: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) 8020704: f107 0398 add.w r3, r7, #152 ; 0x98 8020708: 2103 movs r1, #3 802070a: 4618 mov r0, r3 802070c: f000 ffaa bl 8021664 8020710: 4603 mov r3, r0 8020712: 2b00 cmp r3, #0 8020714: d001 beq.n 802071a { Error_Handler(); 8020716: f000 f8bb bl 8020890 } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_CLK48; 802071a: 4b0c ldr r3, [pc, #48] ; (802074c ) 802071c: 60bb str r3, [r7, #8] PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; 802071e: 2300 movs r3, #0 8020720: 657b str r3, [r7, #84] ; 0x54 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; 8020722: 2300 movs r3, #0 8020724: f8c7 3084 str.w r3, [r7, #132] ; 0x84 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8020728: f107 0308 add.w r3, r7, #8 802072c: 4618 mov r0, r3 802072e: f001 f95d bl 80219ec 8020732: 4603 mov r3, r0 8020734: 2b00 cmp r3, #0 8020736: d001 beq.n 802073c { Error_Handler(); 8020738: f000 f8aa bl 8020890 } } 802073c: bf00 nop 802073e: 37e0 adds r7, #224 ; 0xe0 8020740: 46bd mov sp, r7 8020742: bd80 pop {r7, pc} 8020744: 40023800 .word 0x40023800 8020748: 40007000 .word 0x40007000 802074c: 00200100 .word 0x00200100 08020750 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8020750: b580 push {r7, lr} 8020752: b08c sub sp, #48 ; 0x30 8020754: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8020756: f107 031c add.w r3, r7, #28 802075a: 2200 movs r2, #0 802075c: 601a str r2, [r3, #0] 802075e: 605a str r2, [r3, #4] 8020760: 609a str r2, [r3, #8] 8020762: 60da str r2, [r3, #12] 8020764: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8020766: 4b41 ldr r3, [pc, #260] ; (802086c ) 8020768: 6b1b ldr r3, [r3, #48] ; 0x30 802076a: 4a40 ldr r2, [pc, #256] ; (802086c ) 802076c: f043 0304 orr.w r3, r3, #4 8020770: 6313 str r3, [r2, #48] ; 0x30 8020772: 4b3e ldr r3, [pc, #248] ; (802086c ) 8020774: 6b1b ldr r3, [r3, #48] ; 0x30 8020776: f003 0304 and.w r3, r3, #4 802077a: 61bb str r3, [r7, #24] 802077c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 802077e: 4b3b ldr r3, [pc, #236] ; (802086c ) 8020780: 6b1b ldr r3, [r3, #48] ; 0x30 8020782: 4a3a ldr r2, [pc, #232] ; (802086c ) 8020784: f043 0380 orr.w r3, r3, #128 ; 0x80 8020788: 6313 str r3, [r2, #48] ; 0x30 802078a: 4b38 ldr r3, [pc, #224] ; (802086c ) 802078c: 6b1b ldr r3, [r3, #48] ; 0x30 802078e: f003 0380 and.w r3, r3, #128 ; 0x80 8020792: 617b str r3, [r7, #20] 8020794: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8020796: 4b35 ldr r3, [pc, #212] ; (802086c ) 8020798: 6b1b ldr r3, [r3, #48] ; 0x30 802079a: 4a34 ldr r2, [pc, #208] ; (802086c ) 802079c: f043 0301 orr.w r3, r3, #1 80207a0: 6313 str r3, [r2, #48] ; 0x30 80207a2: 4b32 ldr r3, [pc, #200] ; (802086c ) 80207a4: 6b1b ldr r3, [r3, #48] ; 0x30 80207a6: f003 0301 and.w r3, r3, #1 80207aa: 613b str r3, [r7, #16] 80207ac: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80207ae: 4b2f ldr r3, [pc, #188] ; (802086c ) 80207b0: 6b1b ldr r3, [r3, #48] ; 0x30 80207b2: 4a2e ldr r2, [pc, #184] ; (802086c ) 80207b4: f043 0302 orr.w r3, r3, #2 80207b8: 6313 str r3, [r2, #48] ; 0x30 80207ba: 4b2c ldr r3, [pc, #176] ; (802086c ) 80207bc: 6b1b ldr r3, [r3, #48] ; 0x30 80207be: f003 0302 and.w r3, r3, #2 80207c2: 60fb str r3, [r7, #12] 80207c4: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 80207c6: 4b29 ldr r3, [pc, #164] ; (802086c ) 80207c8: 6b1b ldr r3, [r3, #48] ; 0x30 80207ca: 4a28 ldr r2, [pc, #160] ; (802086c ) 80207cc: f043 0308 orr.w r3, r3, #8 80207d0: 6313 str r3, [r2, #48] ; 0x30 80207d2: 4b26 ldr r3, [pc, #152] ; (802086c ) 80207d4: 6b1b ldr r3, [r3, #48] ; 0x30 80207d6: f003 0308 and.w r3, r3, #8 80207da: 60bb str r3, [r7, #8] 80207dc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 80207de: 4b23 ldr r3, [pc, #140] ; (802086c ) 80207e0: 6b1b ldr r3, [r3, #48] ; 0x30 80207e2: 4a22 ldr r2, [pc, #136] ; (802086c ) 80207e4: f043 0340 orr.w r3, r3, #64 ; 0x40 80207e8: 6313 str r3, [r2, #48] ; 0x30 80207ea: 4b20 ldr r3, [pc, #128] ; (802086c ) 80207ec: 6b1b ldr r3, [r3, #48] ; 0x30 80207ee: f003 0340 and.w r3, r3, #64 ; 0x40 80207f2: 607b str r3, [r7, #4] 80207f4: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET); 80207f6: 2200 movs r2, #0 80207f8: f244 0181 movw r1, #16513 ; 0x4081 80207fc: 481c ldr r0, [pc, #112] ; (8020870 ) 80207fe: f000 fbef bl 8020fe0 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET); 8020802: 2200 movs r2, #0 8020804: 2140 movs r1, #64 ; 0x40 8020806: 481b ldr r0, [pc, #108] ; (8020874 ) 8020808: f000 fbea bl 8020fe0 /*Configure GPIO pin : USER_Btn_Pin */ GPIO_InitStruct.Pin = USER_Btn_Pin; 802080c: f44f 5300 mov.w r3, #8192 ; 0x2000 8020810: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8020812: 4b19 ldr r3, [pc, #100] ; (8020878 ) 8020814: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8020816: 2300 movs r3, #0 8020818: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct); 802081a: f107 031c add.w r3, r7, #28 802081e: 4619 mov r1, r3 8020820: 4816 ldr r0, [pc, #88] ; (802087c ) 8020822: f000 fa33 bl 8020c8c /*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */ GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin; 8020826: f244 0381 movw r3, #16513 ; 0x4081 802082a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 802082c: 2301 movs r3, #1 802082e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8020830: 2300 movs r3, #0 8020832: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8020834: 2300 movs r3, #0 8020836: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8020838: f107 031c add.w r3, r7, #28 802083c: 4619 mov r1, r3 802083e: 480c ldr r0, [pc, #48] ; (8020870 ) 8020840: f000 fa24 bl 8020c8c HAL_GPIO_WritePin(GPIOB, LD1_Pin, GPIO_PIN_RESET); 8020844: 2200 movs r2, #0 8020846: 2101 movs r1, #1 8020848: 4809 ldr r0, [pc, #36] ; (8020870 ) 802084a: f000 fbc9 bl 8020fe0 HAL_GPIO_WritePin(GPIOB, LD2_Pin, GPIO_PIN_RESET); 802084e: 2200 movs r2, #0 8020850: 2180 movs r1, #128 ; 0x80 8020852: 4807 ldr r0, [pc, #28] ; (8020870 ) 8020854: f000 fbc4 bl 8020fe0 HAL_GPIO_WritePin(GPIOB, LD3_Pin, GPIO_PIN_RESET); 8020858: 2200 movs r2, #0 802085a: f44f 4180 mov.w r1, #16384 ; 0x4000 802085e: 4804 ldr r0, [pc, #16] ; (8020870 ) 8020860: f000 fbbe bl 8020fe0 // GPIO_InitStruct.Pin = USB_OverCurrent_Pin; // GPIO_InitStruct.Mode = GPIO_MODE_INPUT; // GPIO_InitStruct.Pull = GPIO_NOPULL; // HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct); } 8020864: bf00 nop 8020866: 3730 adds r7, #48 ; 0x30 8020868: 46bd mov sp, r7 802086a: bd80 pop {r7, pc} 802086c: 40023800 .word 0x40023800 8020870: 40020400 .word 0x40020400 8020874: 40021800 .word 0x40021800 8020878: 10110000 .word 0x10110000 802087c: 40020800 .word 0x40020800 08020880 : * @brief CPU L1-Cache enable. * @param None * @retval None */ static void CPU_CACHE_Enable(void) { 8020880: b580 push {r7, lr} 8020882: af00 add r7, sp, #0 /* Enable I-Cache */ SCB_EnableICache(); 8020884: f7ff fe58 bl 8020538 /* Enable D-Cache */ SCB_EnableDCache(); 8020888: f7ff fe76 bl 8020578 } 802088c: bf00 nop 802088e: bd80 pop {r7, pc} 08020890 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8020890: b480 push {r7} 8020892: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 8020894: bf00 nop 8020896: 46bd mov sp, r7 8020898: f85d 7b04 ldr.w r7, [sp], #4 802089c: 4770 bx lr ... 080208a0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80208a0: b480 push {r7} 80208a2: b083 sub sp, #12 80208a4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_PWR_CLK_ENABLE(); 80208a6: 4b0f ldr r3, [pc, #60] ; (80208e4 ) 80208a8: 6c1b ldr r3, [r3, #64] ; 0x40 80208aa: 4a0e ldr r2, [pc, #56] ; (80208e4 ) 80208ac: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80208b0: 6413 str r3, [r2, #64] ; 0x40 80208b2: 4b0c ldr r3, [pc, #48] ; (80208e4 ) 80208b4: 6c1b ldr r3, [r3, #64] ; 0x40 80208b6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80208ba: 607b str r3, [r7, #4] 80208bc: 687b ldr r3, [r7, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 80208be: 4b09 ldr r3, [pc, #36] ; (80208e4 ) 80208c0: 6c5b ldr r3, [r3, #68] ; 0x44 80208c2: 4a08 ldr r2, [pc, #32] ; (80208e4 ) 80208c4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80208c8: 6453 str r3, [r2, #68] ; 0x44 80208ca: 4b06 ldr r3, [pc, #24] ; (80208e4 ) 80208cc: 6c5b ldr r3, [r3, #68] ; 0x44 80208ce: f403 4380 and.w r3, r3, #16384 ; 0x4000 80208d2: 603b str r3, [r7, #0] 80208d4: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80208d6: bf00 nop 80208d8: 370c adds r7, #12 80208da: 46bd mov sp, r7 80208dc: f85d 7b04 ldr.w r7, [sp], #4 80208e0: 4770 bx lr 80208e2: bf00 nop 80208e4: 40023800 .word 0x40023800 080208e8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80208e8: b480 push {r7} 80208ea: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 80208ec: bf00 nop 80208ee: 46bd mov sp, r7 80208f0: f85d 7b04 ldr.w r7, [sp], #4 80208f4: 4770 bx lr 080208f6 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80208f6: b480 push {r7} 80208f8: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80208fa: e7fe b.n 80208fa 080208fc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80208fc: b480 push {r7} 80208fe: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8020900: e7fe b.n 8020900 08020902 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8020902: b480 push {r7} 8020904: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8020906: e7fe b.n 8020906 08020908 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8020908: b480 push {r7} 802090a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 802090c: e7fe b.n 802090c 0802090e : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 802090e: b480 push {r7} 8020910: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8020912: bf00 nop 8020914: 46bd mov sp, r7 8020916: f85d 7b04 ldr.w r7, [sp], #4 802091a: 4770 bx lr 0802091c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 802091c: b480 push {r7} 802091e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8020920: bf00 nop 8020922: 46bd mov sp, r7 8020924: f85d 7b04 ldr.w r7, [sp], #4 8020928: 4770 bx lr 0802092a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 802092a: b480 push {r7} 802092c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 802092e: bf00 nop 8020930: 46bd mov sp, r7 8020932: f85d 7b04 ldr.w r7, [sp], #4 8020936: 4770 bx lr 08020938 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8020938: b580 push {r7, lr} 802093a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 802093c: f000 f87e bl 8020a3c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8020940: bf00 nop 8020942: bd80 pop {r7, pc} 08020944 : * SystemFrequency variable. * @param None * @retval None */ void SystemInit(void) { 8020944: b480 push {r7} 8020946: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8020948: 4b07 ldr r3, [pc, #28] ; (8020968 ) 802094a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 802094e: 4a06 ldr r2, [pc, #24] ; (8020968 ) 8020950: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8020954: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 8020958: 4b03 ldr r3, [pc, #12] ; (8020968 ) 802095a: 4a04 ldr r2, [pc, #16] ; (802096c ) 802095c: 609a str r2, [r3, #8] #endif } 802095e: bf00 nop 8020960: 46bd mov sp, r7 8020962: f85d 7b04 ldr.w r7, [sp], #4 8020966: 4770 bx lr 8020968: e000ed00 .word 0xe000ed00 802096c: 08020000 .word 0x08020000 08020970 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8020970: f8df d034 ldr.w sp, [pc, #52] ; 80209a8 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8020974: 2100 movs r1, #0 b LoopCopyDataInit 8020976: e003 b.n 8020980 08020978 : CopyDataInit: ldr r3, =_sidata 8020978: 4b0c ldr r3, [pc, #48] ; (80209ac ) ldr r3, [r3, r1] 802097a: 585b ldr r3, [r3, r1] str r3, [r0, r1] 802097c: 5043 str r3, [r0, r1] adds r1, r1, #4 802097e: 3104 adds r1, #4 08020980 : LoopCopyDataInit: ldr r0, =_sdata 8020980: 480b ldr r0, [pc, #44] ; (80209b0 ) ldr r3, =_edata 8020982: 4b0c ldr r3, [pc, #48] ; (80209b4 ) adds r2, r0, r1 8020984: 1842 adds r2, r0, r1 cmp r2, r3 8020986: 429a cmp r2, r3 bcc CopyDataInit 8020988: d3f6 bcc.n 8020978 ldr r2, =_sbss 802098a: 4a0b ldr r2, [pc, #44] ; (80209b8 ) b LoopFillZerobss 802098c: e002 b.n 8020994 0802098e : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 802098e: 2300 movs r3, #0 str r3, [r2], #4 8020990: f842 3b04 str.w r3, [r2], #4 08020994 : LoopFillZerobss: ldr r3, = _ebss 8020994: 4b09 ldr r3, [pc, #36] ; (80209bc ) cmp r2, r3 8020996: 429a cmp r2, r3 bcc FillZerobss 8020998: d3f9 bcc.n 802098e /* Call the clock system initialization function.*/ bl SystemInit 802099a: f7ff ffd3 bl 8020944 /* Call static constructors */ bl __libc_init_array 802099e: f001 fc4b bl 8022238 <__libc_init_array> /* Call the application's entry point.*/ bl main 80209a2: f7ff fe29 bl 80205f8
bx lr 80209a6: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80209a8: 20080000 .word 0x20080000 ldr r3, =_sidata 80209ac: 080222c8 .word 0x080222c8 ldr r0, =_sdata 80209b0: 20000000 .word 0x20000000 ldr r3, =_edata 80209b4: 2000000c .word 0x2000000c ldr r2, =_sbss 80209b8: 2000000c .word 0x2000000c ldr r3, = _ebss 80209bc: 2000002c .word 0x2000002c 080209c0 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80209c0: e7fe b.n 80209c0 080209c2 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80209c2: b580 push {r7, lr} 80209c4: af00 add r7, sp, #0 #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80209c6: 2003 movs r0, #3 80209c8: f000 f92c bl 8020c24 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80209cc: 2000 movs r0, #0 80209ce: f000 f805 bl 80209dc /* Init the low level hardware */ HAL_MspInit(); 80209d2: f7ff ff65 bl 80208a0 /* Return function status */ return HAL_OK; 80209d6: 2300 movs r3, #0 } 80209d8: 4618 mov r0, r3 80209da: bd80 pop {r7, pc} 080209dc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80209dc: b580 push {r7, lr} 80209de: b082 sub sp, #8 80209e0: af00 add r7, sp, #0 80209e2: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80209e4: 4b12 ldr r3, [pc, #72] ; (8020a30 ) 80209e6: 681a ldr r2, [r3, #0] 80209e8: 4b12 ldr r3, [pc, #72] ; (8020a34 ) 80209ea: 781b ldrb r3, [r3, #0] 80209ec: 4619 mov r1, r3 80209ee: f44f 737a mov.w r3, #1000 ; 0x3e8 80209f2: fbb3 f3f1 udiv r3, r3, r1 80209f6: fbb2 f3f3 udiv r3, r2, r3 80209fa: 4618 mov r0, r3 80209fc: f000 f939 bl 8020c72 8020a00: 4603 mov r3, r0 8020a02: 2b00 cmp r3, #0 8020a04: d001 beq.n 8020a0a { return HAL_ERROR; 8020a06: 2301 movs r3, #1 8020a08: e00e b.n 8020a28 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8020a0a: 687b ldr r3, [r7, #4] 8020a0c: 2b0f cmp r3, #15 8020a0e: d80a bhi.n 8020a26 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8020a10: 2200 movs r2, #0 8020a12: 6879 ldr r1, [r7, #4] 8020a14: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8020a18: f000 f90f bl 8020c3a uwTickPrio = TickPriority; 8020a1c: 4a06 ldr r2, [pc, #24] ; (8020a38 ) 8020a1e: 687b ldr r3, [r7, #4] 8020a20: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8020a22: 2300 movs r3, #0 8020a24: e000 b.n 8020a28 return HAL_ERROR; 8020a26: 2301 movs r3, #1 } 8020a28: 4618 mov r0, r3 8020a2a: 3708 adds r7, #8 8020a2c: 46bd mov sp, r7 8020a2e: bd80 pop {r7, pc} 8020a30: 20000000 .word 0x20000000 8020a34: 20000008 .word 0x20000008 8020a38: 20000004 .word 0x20000004 08020a3c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8020a3c: b480 push {r7} 8020a3e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8020a40: 4b06 ldr r3, [pc, #24] ; (8020a5c ) 8020a42: 781b ldrb r3, [r3, #0] 8020a44: 461a mov r2, r3 8020a46: 4b06 ldr r3, [pc, #24] ; (8020a60 ) 8020a48: 681b ldr r3, [r3, #0] 8020a4a: 4413 add r3, r2 8020a4c: 4a04 ldr r2, [pc, #16] ; (8020a60 ) 8020a4e: 6013 str r3, [r2, #0] } 8020a50: bf00 nop 8020a52: 46bd mov sp, r7 8020a54: f85d 7b04 ldr.w r7, [sp], #4 8020a58: 4770 bx lr 8020a5a: bf00 nop 8020a5c: 20000008 .word 0x20000008 8020a60: 20000028 .word 0x20000028 08020a64 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8020a64: b480 push {r7} 8020a66: af00 add r7, sp, #0 return uwTick; 8020a68: 4b03 ldr r3, [pc, #12] ; (8020a78 ) 8020a6a: 681b ldr r3, [r3, #0] } 8020a6c: 4618 mov r0, r3 8020a6e: 46bd mov sp, r7 8020a70: f85d 7b04 ldr.w r7, [sp], #4 8020a74: 4770 bx lr 8020a76: bf00 nop 8020a78: 20000028 .word 0x20000028 08020a7c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8020a7c: b580 push {r7, lr} 8020a7e: b084 sub sp, #16 8020a80: af00 add r7, sp, #0 8020a82: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8020a84: f7ff ffee bl 8020a64 8020a88: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8020a8a: 687b ldr r3, [r7, #4] 8020a8c: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8020a8e: 68fb ldr r3, [r7, #12] 8020a90: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8020a94: d005 beq.n 8020aa2 { wait += (uint32_t)(uwTickFreq); 8020a96: 4b09 ldr r3, [pc, #36] ; (8020abc ) 8020a98: 781b ldrb r3, [r3, #0] 8020a9a: 461a mov r2, r3 8020a9c: 68fb ldr r3, [r7, #12] 8020a9e: 4413 add r3, r2 8020aa0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8020aa2: bf00 nop 8020aa4: f7ff ffde bl 8020a64 8020aa8: 4602 mov r2, r0 8020aaa: 68bb ldr r3, [r7, #8] 8020aac: 1ad3 subs r3, r2, r3 8020aae: 68fa ldr r2, [r7, #12] 8020ab0: 429a cmp r2, r3 8020ab2: d8f7 bhi.n 8020aa4 { } } 8020ab4: bf00 nop 8020ab6: 3710 adds r7, #16 8020ab8: 46bd mov sp, r7 8020aba: bd80 pop {r7, pc} 8020abc: 20000008 .word 0x20000008 08020ac0 <__NVIC_SetPriorityGrouping>: { 8020ac0: b480 push {r7} 8020ac2: b085 sub sp, #20 8020ac4: af00 add r7, sp, #0 8020ac6: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8020ac8: 687b ldr r3, [r7, #4] 8020aca: f003 0307 and.w r3, r3, #7 8020ace: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8020ad0: 4b0b ldr r3, [pc, #44] ; (8020b00 <__NVIC_SetPriorityGrouping+0x40>) 8020ad2: 68db ldr r3, [r3, #12] 8020ad4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8020ad6: 68ba ldr r2, [r7, #8] 8020ad8: f64f 03ff movw r3, #63743 ; 0xf8ff 8020adc: 4013 ands r3, r2 8020ade: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8020ae0: 68fb ldr r3, [r7, #12] 8020ae2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8020ae4: 68bb ldr r3, [r7, #8] 8020ae6: 431a orrs r2, r3 reg_value = (reg_value | 8020ae8: 4b06 ldr r3, [pc, #24] ; (8020b04 <__NVIC_SetPriorityGrouping+0x44>) 8020aea: 4313 orrs r3, r2 8020aec: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8020aee: 4a04 ldr r2, [pc, #16] ; (8020b00 <__NVIC_SetPriorityGrouping+0x40>) 8020af0: 68bb ldr r3, [r7, #8] 8020af2: 60d3 str r3, [r2, #12] } 8020af4: bf00 nop 8020af6: 3714 adds r7, #20 8020af8: 46bd mov sp, r7 8020afa: f85d 7b04 ldr.w r7, [sp], #4 8020afe: 4770 bx lr 8020b00: e000ed00 .word 0xe000ed00 8020b04: 05fa0000 .word 0x05fa0000 08020b08 <__NVIC_GetPriorityGrouping>: { 8020b08: b480 push {r7} 8020b0a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8020b0c: 4b04 ldr r3, [pc, #16] ; (8020b20 <__NVIC_GetPriorityGrouping+0x18>) 8020b0e: 68db ldr r3, [r3, #12] 8020b10: 0a1b lsrs r3, r3, #8 8020b12: f003 0307 and.w r3, r3, #7 } 8020b16: 4618 mov r0, r3 8020b18: 46bd mov sp, r7 8020b1a: f85d 7b04 ldr.w r7, [sp], #4 8020b1e: 4770 bx lr 8020b20: e000ed00 .word 0xe000ed00 08020b24 <__NVIC_SetPriority>: { 8020b24: b480 push {r7} 8020b26: b083 sub sp, #12 8020b28: af00 add r7, sp, #0 8020b2a: 4603 mov r3, r0 8020b2c: 6039 str r1, [r7, #0] 8020b2e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8020b30: f997 3007 ldrsb.w r3, [r7, #7] 8020b34: 2b00 cmp r3, #0 8020b36: db0a blt.n 8020b4e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8020b38: 683b ldr r3, [r7, #0] 8020b3a: b2da uxtb r2, r3 8020b3c: 490c ldr r1, [pc, #48] ; (8020b70 <__NVIC_SetPriority+0x4c>) 8020b3e: f997 3007 ldrsb.w r3, [r7, #7] 8020b42: 0112 lsls r2, r2, #4 8020b44: b2d2 uxtb r2, r2 8020b46: 440b add r3, r1 8020b48: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 8020b4c: e00a b.n 8020b64 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8020b4e: 683b ldr r3, [r7, #0] 8020b50: b2da uxtb r2, r3 8020b52: 4908 ldr r1, [pc, #32] ; (8020b74 <__NVIC_SetPriority+0x50>) 8020b54: 79fb ldrb r3, [r7, #7] 8020b56: f003 030f and.w r3, r3, #15 8020b5a: 3b04 subs r3, #4 8020b5c: 0112 lsls r2, r2, #4 8020b5e: b2d2 uxtb r2, r2 8020b60: 440b add r3, r1 8020b62: 761a strb r2, [r3, #24] } 8020b64: bf00 nop 8020b66: 370c adds r7, #12 8020b68: 46bd mov sp, r7 8020b6a: f85d 7b04 ldr.w r7, [sp], #4 8020b6e: 4770 bx lr 8020b70: e000e100 .word 0xe000e100 8020b74: e000ed00 .word 0xe000ed00 08020b78 : { 8020b78: b480 push {r7} 8020b7a: b089 sub sp, #36 ; 0x24 8020b7c: af00 add r7, sp, #0 8020b7e: 60f8 str r0, [r7, #12] 8020b80: 60b9 str r1, [r7, #8] 8020b82: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8020b84: 68fb ldr r3, [r7, #12] 8020b86: f003 0307 and.w r3, r3, #7 8020b8a: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8020b8c: 69fb ldr r3, [r7, #28] 8020b8e: f1c3 0307 rsb r3, r3, #7 8020b92: 2b04 cmp r3, #4 8020b94: bf28 it cs 8020b96: 2304 movcs r3, #4 8020b98: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8020b9a: 69fb ldr r3, [r7, #28] 8020b9c: 3304 adds r3, #4 8020b9e: 2b06 cmp r3, #6 8020ba0: d902 bls.n 8020ba8 8020ba2: 69fb ldr r3, [r7, #28] 8020ba4: 3b03 subs r3, #3 8020ba6: e000 b.n 8020baa 8020ba8: 2300 movs r3, #0 8020baa: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8020bac: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8020bb0: 69bb ldr r3, [r7, #24] 8020bb2: fa02 f303 lsl.w r3, r2, r3 8020bb6: 43da mvns r2, r3 8020bb8: 68bb ldr r3, [r7, #8] 8020bba: 401a ands r2, r3 8020bbc: 697b ldr r3, [r7, #20] 8020bbe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8020bc0: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8020bc4: 697b ldr r3, [r7, #20] 8020bc6: fa01 f303 lsl.w r3, r1, r3 8020bca: 43d9 mvns r1, r3 8020bcc: 687b ldr r3, [r7, #4] 8020bce: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8020bd0: 4313 orrs r3, r2 } 8020bd2: 4618 mov r0, r3 8020bd4: 3724 adds r7, #36 ; 0x24 8020bd6: 46bd mov sp, r7 8020bd8: f85d 7b04 ldr.w r7, [sp], #4 8020bdc: 4770 bx lr ... 08020be0 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8020be0: b580 push {r7, lr} 8020be2: b082 sub sp, #8 8020be4: af00 add r7, sp, #0 8020be6: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8020be8: 687b ldr r3, [r7, #4] 8020bea: 3b01 subs r3, #1 8020bec: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8020bf0: d301 bcc.n 8020bf6 { return (1UL); /* Reload value impossible */ 8020bf2: 2301 movs r3, #1 8020bf4: e00f b.n 8020c16 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8020bf6: 4a0a ldr r2, [pc, #40] ; (8020c20 ) 8020bf8: 687b ldr r3, [r7, #4] 8020bfa: 3b01 subs r3, #1 8020bfc: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8020bfe: 210f movs r1, #15 8020c00: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8020c04: f7ff ff8e bl 8020b24 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8020c08: 4b05 ldr r3, [pc, #20] ; (8020c20 ) 8020c0a: 2200 movs r2, #0 8020c0c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8020c0e: 4b04 ldr r3, [pc, #16] ; (8020c20 ) 8020c10: 2207 movs r2, #7 8020c12: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8020c14: 2300 movs r3, #0 } 8020c16: 4618 mov r0, r3 8020c18: 3708 adds r7, #8 8020c1a: 46bd mov sp, r7 8020c1c: bd80 pop {r7, pc} 8020c1e: bf00 nop 8020c20: e000e010 .word 0xe000e010 08020c24 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8020c24: b580 push {r7, lr} 8020c26: b082 sub sp, #8 8020c28: af00 add r7, sp, #0 8020c2a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8020c2c: 6878 ldr r0, [r7, #4] 8020c2e: f7ff ff47 bl 8020ac0 <__NVIC_SetPriorityGrouping> } 8020c32: bf00 nop 8020c34: 3708 adds r7, #8 8020c36: 46bd mov sp, r7 8020c38: bd80 pop {r7, pc} 08020c3a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8020c3a: b580 push {r7, lr} 8020c3c: b086 sub sp, #24 8020c3e: af00 add r7, sp, #0 8020c40: 4603 mov r3, r0 8020c42: 60b9 str r1, [r7, #8] 8020c44: 607a str r2, [r7, #4] 8020c46: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; 8020c48: 2300 movs r3, #0 8020c4a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8020c4c: f7ff ff5c bl 8020b08 <__NVIC_GetPriorityGrouping> 8020c50: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8020c52: 687a ldr r2, [r7, #4] 8020c54: 68b9 ldr r1, [r7, #8] 8020c56: 6978 ldr r0, [r7, #20] 8020c58: f7ff ff8e bl 8020b78 8020c5c: 4602 mov r2, r0 8020c5e: f997 300f ldrsb.w r3, [r7, #15] 8020c62: 4611 mov r1, r2 8020c64: 4618 mov r0, r3 8020c66: f7ff ff5d bl 8020b24 <__NVIC_SetPriority> } 8020c6a: bf00 nop 8020c6c: 3718 adds r7, #24 8020c6e: 46bd mov sp, r7 8020c70: bd80 pop {r7, pc} 08020c72 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8020c72: b580 push {r7, lr} 8020c74: b082 sub sp, #8 8020c76: af00 add r7, sp, #0 8020c78: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8020c7a: 6878 ldr r0, [r7, #4] 8020c7c: f7ff ffb0 bl 8020be0 8020c80: 4603 mov r3, r0 } 8020c82: 4618 mov r0, r3 8020c84: 3708 adds r7, #8 8020c86: 46bd mov sp, r7 8020c88: bd80 pop {r7, pc} ... 08020c8c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8020c8c: b480 push {r7} 8020c8e: b089 sub sp, #36 ; 0x24 8020c90: af00 add r7, sp, #0 8020c92: 6078 str r0, [r7, #4] 8020c94: 6039 str r1, [r7, #0] uint32_t position = 0x00; 8020c96: 2300 movs r3, #0 8020c98: 61fb str r3, [r7, #28] uint32_t ioposition = 0x00; 8020c9a: 2300 movs r3, #0 8020c9c: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; 8020c9e: 2300 movs r3, #0 8020ca0: 613b str r3, [r7, #16] uint32_t temp = 0x00; 8020ca2: 2300 movs r3, #0 8020ca4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0; position < GPIO_NUMBER; position++) 8020ca6: 2300 movs r3, #0 8020ca8: 61fb str r3, [r7, #28] 8020caa: e175 b.n 8020f98 { /* Get the IO position */ ioposition = ((uint32_t)0x01) << position; 8020cac: 2201 movs r2, #1 8020cae: 69fb ldr r3, [r7, #28] 8020cb0: fa02 f303 lsl.w r3, r2, r3 8020cb4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8020cb6: 683b ldr r3, [r7, #0] 8020cb8: 681b ldr r3, [r3, #0] 8020cba: 697a ldr r2, [r7, #20] 8020cbc: 4013 ands r3, r2 8020cbe: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8020cc0: 693a ldr r2, [r7, #16] 8020cc2: 697b ldr r3, [r7, #20] 8020cc4: 429a cmp r2, r3 8020cc6: f040 8164 bne.w 8020f92 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 8020cca: 683b ldr r3, [r7, #0] 8020ccc: 685b ldr r3, [r3, #4] 8020cce: 2b01 cmp r3, #1 8020cd0: d00b beq.n 8020cea 8020cd2: 683b ldr r3, [r7, #0] 8020cd4: 685b ldr r3, [r3, #4] 8020cd6: 2b02 cmp r3, #2 8020cd8: d007 beq.n 8020cea (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8020cda: 683b ldr r3, [r7, #0] 8020cdc: 685b ldr r3, [r3, #4] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 8020cde: 2b11 cmp r3, #17 8020ce0: d003 beq.n 8020cea (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8020ce2: 683b ldr r3, [r7, #0] 8020ce4: 685b ldr r3, [r3, #4] 8020ce6: 2b12 cmp r3, #18 8020ce8: d130 bne.n 8020d4c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8020cea: 687b ldr r3, [r7, #4] 8020cec: 689b ldr r3, [r3, #8] 8020cee: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); 8020cf0: 69fb ldr r3, [r7, #28] 8020cf2: 005b lsls r3, r3, #1 8020cf4: 2203 movs r2, #3 8020cf6: fa02 f303 lsl.w r3, r2, r3 8020cfa: 43db mvns r3, r3 8020cfc: 69ba ldr r2, [r7, #24] 8020cfe: 4013 ands r3, r2 8020d00: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2)); 8020d02: 683b ldr r3, [r7, #0] 8020d04: 68da ldr r2, [r3, #12] 8020d06: 69fb ldr r3, [r7, #28] 8020d08: 005b lsls r3, r3, #1 8020d0a: fa02 f303 lsl.w r3, r2, r3 8020d0e: 69ba ldr r2, [r7, #24] 8020d10: 4313 orrs r3, r2 8020d12: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8020d14: 687b ldr r3, [r7, #4] 8020d16: 69ba ldr r2, [r7, #24] 8020d18: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8020d1a: 687b ldr r3, [r7, #4] 8020d1c: 685b ldr r3, [r3, #4] 8020d1e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8020d20: 2201 movs r2, #1 8020d22: 69fb ldr r3, [r7, #28] 8020d24: fa02 f303 lsl.w r3, r2, r3 8020d28: 43db mvns r3, r3 8020d2a: 69ba ldr r2, [r7, #24] 8020d2c: 4013 ands r3, r2 8020d2e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); 8020d30: 683b ldr r3, [r7, #0] 8020d32: 685b ldr r3, [r3, #4] 8020d34: 091b lsrs r3, r3, #4 8020d36: f003 0201 and.w r2, r3, #1 8020d3a: 69fb ldr r3, [r7, #28] 8020d3c: fa02 f303 lsl.w r3, r2, r3 8020d40: 69ba ldr r2, [r7, #24] 8020d42: 4313 orrs r3, r2 8020d44: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8020d46: 687b ldr r3, [r7, #4] 8020d48: 69ba ldr r2, [r7, #24] 8020d4a: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8020d4c: 687b ldr r3, [r7, #4] 8020d4e: 68db ldr r3, [r3, #12] 8020d50: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); 8020d52: 69fb ldr r3, [r7, #28] 8020d54: 005b lsls r3, r3, #1 8020d56: 2203 movs r2, #3 8020d58: fa02 f303 lsl.w r3, r2, r3 8020d5c: 43db mvns r3, r3 8020d5e: 69ba ldr r2, [r7, #24] 8020d60: 4013 ands r3, r2 8020d62: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2)); 8020d64: 683b ldr r3, [r7, #0] 8020d66: 689a ldr r2, [r3, #8] 8020d68: 69fb ldr r3, [r7, #28] 8020d6a: 005b lsls r3, r3, #1 8020d6c: fa02 f303 lsl.w r3, r2, r3 8020d70: 69ba ldr r2, [r7, #24] 8020d72: 4313 orrs r3, r2 8020d74: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8020d76: 687b ldr r3, [r7, #4] 8020d78: 69ba ldr r2, [r7, #24] 8020d7a: 60da str r2, [r3, #12] /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8020d7c: 683b ldr r3, [r7, #0] 8020d7e: 685b ldr r3, [r3, #4] 8020d80: 2b02 cmp r3, #2 8020d82: d003 beq.n 8020d8c 8020d84: 683b ldr r3, [r7, #0] 8020d86: 685b ldr r3, [r3, #4] 8020d88: 2b12 cmp r3, #18 8020d8a: d123 bne.n 8020dd4 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; 8020d8c: 69fb ldr r3, [r7, #28] 8020d8e: 08da lsrs r2, r3, #3 8020d90: 687b ldr r3, [r7, #4] 8020d92: 3208 adds r2, #8 8020d94: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8020d98: 61bb str r3, [r7, #24] temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; 8020d9a: 69fb ldr r3, [r7, #28] 8020d9c: f003 0307 and.w r3, r3, #7 8020da0: 009b lsls r3, r3, #2 8020da2: 220f movs r2, #15 8020da4: fa02 f303 lsl.w r3, r2, r3 8020da8: 43db mvns r3, r3 8020daa: 69ba ldr r2, [r7, #24] 8020dac: 4013 ands r3, r2 8020dae: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); 8020db0: 683b ldr r3, [r7, #0] 8020db2: 691a ldr r2, [r3, #16] 8020db4: 69fb ldr r3, [r7, #28] 8020db6: f003 0307 and.w r3, r3, #7 8020dba: 009b lsls r3, r3, #2 8020dbc: fa02 f303 lsl.w r3, r2, r3 8020dc0: 69ba ldr r2, [r7, #24] 8020dc2: 4313 orrs r3, r2 8020dc4: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3] = temp; 8020dc6: 69fb ldr r3, [r7, #28] 8020dc8: 08da lsrs r2, r3, #3 8020dca: 687b ldr r3, [r7, #4] 8020dcc: 3208 adds r2, #8 8020dce: 69b9 ldr r1, [r7, #24] 8020dd0: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8020dd4: 687b ldr r3, [r7, #4] 8020dd6: 681b ldr r3, [r3, #0] 8020dd8: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2)); 8020dda: 69fb ldr r3, [r7, #28] 8020ddc: 005b lsls r3, r3, #1 8020dde: 2203 movs r2, #3 8020de0: fa02 f303 lsl.w r3, r2, r3 8020de4: 43db mvns r3, r3 8020de6: 69ba ldr r2, [r7, #24] 8020de8: 4013 ands r3, r2 8020dea: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); 8020dec: 683b ldr r3, [r7, #0] 8020dee: 685b ldr r3, [r3, #4] 8020df0: f003 0203 and.w r2, r3, #3 8020df4: 69fb ldr r3, [r7, #28] 8020df6: 005b lsls r3, r3, #1 8020df8: fa02 f303 lsl.w r3, r2, r3 8020dfc: 69ba ldr r2, [r7, #24] 8020dfe: 4313 orrs r3, r2 8020e00: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8020e02: 687b ldr r3, [r7, #4] 8020e04: 69ba ldr r2, [r7, #24] 8020e06: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8020e08: 683b ldr r3, [r7, #0] 8020e0a: 685b ldr r3, [r3, #4] 8020e0c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8020e10: 2b00 cmp r3, #0 8020e12: f000 80be beq.w 8020f92 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8020e16: 4b65 ldr r3, [pc, #404] ; (8020fac ) 8020e18: 6c5b ldr r3, [r3, #68] ; 0x44 8020e1a: 4a64 ldr r2, [pc, #400] ; (8020fac ) 8020e1c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8020e20: 6453 str r3, [r2, #68] ; 0x44 8020e22: 4b62 ldr r3, [pc, #392] ; (8020fac ) 8020e24: 6c5b ldr r3, [r3, #68] ; 0x44 8020e26: f403 4380 and.w r3, r3, #16384 ; 0x4000 8020e2a: 60fb str r3, [r7, #12] 8020e2c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2]; 8020e2e: 4a60 ldr r2, [pc, #384] ; (8020fb0 ) 8020e30: 69fb ldr r3, [r7, #28] 8020e32: 089b lsrs r3, r3, #2 8020e34: 3302 adds r3, #2 8020e36: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8020e3a: 61bb str r3, [r7, #24] temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); 8020e3c: 69fb ldr r3, [r7, #28] 8020e3e: f003 0303 and.w r3, r3, #3 8020e42: 009b lsls r3, r3, #2 8020e44: 220f movs r2, #15 8020e46: fa02 f303 lsl.w r3, r2, r3 8020e4a: 43db mvns r3, r3 8020e4c: 69ba ldr r2, [r7, #24] 8020e4e: 4013 ands r3, r2 8020e50: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); 8020e52: 687b ldr r3, [r7, #4] 8020e54: 4a57 ldr r2, [pc, #348] ; (8020fb4 ) 8020e56: 4293 cmp r3, r2 8020e58: d037 beq.n 8020eca 8020e5a: 687b ldr r3, [r7, #4] 8020e5c: 4a56 ldr r2, [pc, #344] ; (8020fb8 ) 8020e5e: 4293 cmp r3, r2 8020e60: d031 beq.n 8020ec6 8020e62: 687b ldr r3, [r7, #4] 8020e64: 4a55 ldr r2, [pc, #340] ; (8020fbc ) 8020e66: 4293 cmp r3, r2 8020e68: d02b beq.n 8020ec2 8020e6a: 687b ldr r3, [r7, #4] 8020e6c: 4a54 ldr r2, [pc, #336] ; (8020fc0 ) 8020e6e: 4293 cmp r3, r2 8020e70: d025 beq.n 8020ebe 8020e72: 687b ldr r3, [r7, #4] 8020e74: 4a53 ldr r2, [pc, #332] ; (8020fc4 ) 8020e76: 4293 cmp r3, r2 8020e78: d01f beq.n 8020eba 8020e7a: 687b ldr r3, [r7, #4] 8020e7c: 4a52 ldr r2, [pc, #328] ; (8020fc8 ) 8020e7e: 4293 cmp r3, r2 8020e80: d019 beq.n 8020eb6 8020e82: 687b ldr r3, [r7, #4] 8020e84: 4a51 ldr r2, [pc, #324] ; (8020fcc ) 8020e86: 4293 cmp r3, r2 8020e88: d013 beq.n 8020eb2 8020e8a: 687b ldr r3, [r7, #4] 8020e8c: 4a50 ldr r2, [pc, #320] ; (8020fd0 ) 8020e8e: 4293 cmp r3, r2 8020e90: d00d beq.n 8020eae 8020e92: 687b ldr r3, [r7, #4] 8020e94: 4a4f ldr r2, [pc, #316] ; (8020fd4 ) 8020e96: 4293 cmp r3, r2 8020e98: d007 beq.n 8020eaa 8020e9a: 687b ldr r3, [r7, #4] 8020e9c: 4a4e ldr r2, [pc, #312] ; (8020fd8 ) 8020e9e: 4293 cmp r3, r2 8020ea0: d101 bne.n 8020ea6 8020ea2: 2309 movs r3, #9 8020ea4: e012 b.n 8020ecc 8020ea6: 230a movs r3, #10 8020ea8: e010 b.n 8020ecc 8020eaa: 2308 movs r3, #8 8020eac: e00e b.n 8020ecc 8020eae: 2307 movs r3, #7 8020eb0: e00c b.n 8020ecc 8020eb2: 2306 movs r3, #6 8020eb4: e00a b.n 8020ecc 8020eb6: 2305 movs r3, #5 8020eb8: e008 b.n 8020ecc 8020eba: 2304 movs r3, #4 8020ebc: e006 b.n 8020ecc 8020ebe: 2303 movs r3, #3 8020ec0: e004 b.n 8020ecc 8020ec2: 2302 movs r3, #2 8020ec4: e002 b.n 8020ecc 8020ec6: 2301 movs r3, #1 8020ec8: e000 b.n 8020ecc 8020eca: 2300 movs r3, #0 8020ecc: 69fa ldr r2, [r7, #28] 8020ece: f002 0203 and.w r2, r2, #3 8020ed2: 0092 lsls r2, r2, #2 8020ed4: 4093 lsls r3, r2 8020ed6: 69ba ldr r2, [r7, #24] 8020ed8: 4313 orrs r3, r2 8020eda: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2] = temp; 8020edc: 4934 ldr r1, [pc, #208] ; (8020fb0 ) 8020ede: 69fb ldr r3, [r7, #28] 8020ee0: 089b lsrs r3, r3, #2 8020ee2: 3302 adds r3, #2 8020ee4: 69ba ldr r2, [r7, #24] 8020ee6: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8020eea: 4b3c ldr r3, [pc, #240] ; (8020fdc ) 8020eec: 681b ldr r3, [r3, #0] 8020eee: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8020ef0: 693b ldr r3, [r7, #16] 8020ef2: 43db mvns r3, r3 8020ef4: 69ba ldr r2, [r7, #24] 8020ef6: 4013 ands r3, r2 8020ef8: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8020efa: 683b ldr r3, [r7, #0] 8020efc: 685b ldr r3, [r3, #4] 8020efe: f403 3380 and.w r3, r3, #65536 ; 0x10000 8020f02: 2b00 cmp r3, #0 8020f04: d003 beq.n 8020f0e { temp |= iocurrent; 8020f06: 69ba ldr r2, [r7, #24] 8020f08: 693b ldr r3, [r7, #16] 8020f0a: 4313 orrs r3, r2 8020f0c: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8020f0e: 4a33 ldr r2, [pc, #204] ; (8020fdc ) 8020f10: 69bb ldr r3, [r7, #24] 8020f12: 6013 str r3, [r2, #0] temp = EXTI->EMR; 8020f14: 4b31 ldr r3, [pc, #196] ; (8020fdc ) 8020f16: 685b ldr r3, [r3, #4] 8020f18: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8020f1a: 693b ldr r3, [r7, #16] 8020f1c: 43db mvns r3, r3 8020f1e: 69ba ldr r2, [r7, #24] 8020f20: 4013 ands r3, r2 8020f22: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8020f24: 683b ldr r3, [r7, #0] 8020f26: 685b ldr r3, [r3, #4] 8020f28: f403 3300 and.w r3, r3, #131072 ; 0x20000 8020f2c: 2b00 cmp r3, #0 8020f2e: d003 beq.n 8020f38 { temp |= iocurrent; 8020f30: 69ba ldr r2, [r7, #24] 8020f32: 693b ldr r3, [r7, #16] 8020f34: 4313 orrs r3, r2 8020f36: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8020f38: 4a28 ldr r2, [pc, #160] ; (8020fdc ) 8020f3a: 69bb ldr r3, [r7, #24] 8020f3c: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8020f3e: 4b27 ldr r3, [pc, #156] ; (8020fdc ) 8020f40: 689b ldr r3, [r3, #8] 8020f42: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8020f44: 693b ldr r3, [r7, #16] 8020f46: 43db mvns r3, r3 8020f48: 69ba ldr r2, [r7, #24] 8020f4a: 4013 ands r3, r2 8020f4c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8020f4e: 683b ldr r3, [r7, #0] 8020f50: 685b ldr r3, [r3, #4] 8020f52: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8020f56: 2b00 cmp r3, #0 8020f58: d003 beq.n 8020f62 { temp |= iocurrent; 8020f5a: 69ba ldr r2, [r7, #24] 8020f5c: 693b ldr r3, [r7, #16] 8020f5e: 4313 orrs r3, r2 8020f60: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8020f62: 4a1e ldr r2, [pc, #120] ; (8020fdc ) 8020f64: 69bb ldr r3, [r7, #24] 8020f66: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8020f68: 4b1c ldr r3, [pc, #112] ; (8020fdc ) 8020f6a: 68db ldr r3, [r3, #12] 8020f6c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8020f6e: 693b ldr r3, [r7, #16] 8020f70: 43db mvns r3, r3 8020f72: 69ba ldr r2, [r7, #24] 8020f74: 4013 ands r3, r2 8020f76: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8020f78: 683b ldr r3, [r7, #0] 8020f7a: 685b ldr r3, [r3, #4] 8020f7c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8020f80: 2b00 cmp r3, #0 8020f82: d003 beq.n 8020f8c { temp |= iocurrent; 8020f84: 69ba ldr r2, [r7, #24] 8020f86: 693b ldr r3, [r7, #16] 8020f88: 4313 orrs r3, r2 8020f8a: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8020f8c: 4a13 ldr r2, [pc, #76] ; (8020fdc ) 8020f8e: 69bb ldr r3, [r7, #24] 8020f90: 60d3 str r3, [r2, #12] for(position = 0; position < GPIO_NUMBER; position++) 8020f92: 69fb ldr r3, [r7, #28] 8020f94: 3301 adds r3, #1 8020f96: 61fb str r3, [r7, #28] 8020f98: 69fb ldr r3, [r7, #28] 8020f9a: 2b0f cmp r3, #15 8020f9c: f67f ae86 bls.w 8020cac } } } } 8020fa0: bf00 nop 8020fa2: 3724 adds r7, #36 ; 0x24 8020fa4: 46bd mov sp, r7 8020fa6: f85d 7b04 ldr.w r7, [sp], #4 8020faa: 4770 bx lr 8020fac: 40023800 .word 0x40023800 8020fb0: 40013800 .word 0x40013800 8020fb4: 40020000 .word 0x40020000 8020fb8: 40020400 .word 0x40020400 8020fbc: 40020800 .word 0x40020800 8020fc0: 40020c00 .word 0x40020c00 8020fc4: 40021000 .word 0x40021000 8020fc8: 40021400 .word 0x40021400 8020fcc: 40021800 .word 0x40021800 8020fd0: 40021c00 .word 0x40021c00 8020fd4: 40022000 .word 0x40022000 8020fd8: 40022400 .word 0x40022400 8020fdc: 40013c00 .word 0x40013c00 08020fe0 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8020fe0: b480 push {r7} 8020fe2: b083 sub sp, #12 8020fe4: af00 add r7, sp, #0 8020fe6: 6078 str r0, [r7, #4] 8020fe8: 460b mov r3, r1 8020fea: 807b strh r3, [r7, #2] 8020fec: 4613 mov r3, r2 8020fee: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8020ff0: 787b ldrb r3, [r7, #1] 8020ff2: 2b00 cmp r3, #0 8020ff4: d003 beq.n 8020ffe { GPIOx->BSRR = GPIO_Pin; 8020ff6: 887a ldrh r2, [r7, #2] 8020ff8: 687b ldr r3, [r7, #4] 8020ffa: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; } } 8020ffc: e003 b.n 8021006 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; 8020ffe: 887b ldrh r3, [r7, #2] 8021000: 041a lsls r2, r3, #16 8021002: 687b ldr r3, [r7, #4] 8021004: 619a str r2, [r3, #24] } 8021006: bf00 nop 8021008: 370c adds r7, #12 802100a: 46bd mov sp, r7 802100c: f85d 7b04 ldr.w r7, [sp], #4 8021010: 4770 bx lr 08021012 : * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8021012: b480 push {r7} 8021014: b083 sub sp, #12 8021016: af00 add r7, sp, #0 8021018: 6078 str r0, [r7, #4] 802101a: 460b mov r3, r1 802101c: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != 0X00u) 802101e: 687b ldr r3, [r7, #4] 8021020: 695a ldr r2, [r3, #20] 8021022: 887b ldrh r3, [r7, #2] 8021024: 4013 ands r3, r2 8021026: 2b00 cmp r3, #0 8021028: d004 beq.n 8021034 { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 802102a: 887b ldrh r3, [r7, #2] 802102c: 041a lsls r2, r3, #16 802102e: 687b ldr r3, [r7, #4] 8021030: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin; } } 8021032: e002 b.n 802103a GPIOx->BSRR = (uint32_t)GPIO_Pin; 8021034: 887a ldrh r2, [r7, #2] 8021036: 687b ldr r3, [r7, #4] 8021038: 619a str r2, [r3, #24] } 802103a: bf00 nop 802103c: 370c adds r7, #12 802103e: 46bd mov sp, r7 8021040: f85d 7b04 ldr.w r7, [sp], #4 8021044: 4770 bx lr ... 08021048 : * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8021048: b480 push {r7} 802104a: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 802104c: 4b05 ldr r3, [pc, #20] ; (8021064 ) 802104e: 681b ldr r3, [r3, #0] 8021050: 4a04 ldr r2, [pc, #16] ; (8021064 ) 8021052: f443 7380 orr.w r3, r3, #256 ; 0x100 8021056: 6013 str r3, [r2, #0] } 8021058: bf00 nop 802105a: 46bd mov sp, r7 802105c: f85d 7b04 ldr.w r7, [sp], #4 8021060: 4770 bx lr 8021062: bf00 nop 8021064: 40007000 .word 0x40007000 08021068 : * During the Over-drive switch activation, no peripheral clocks should be enabled. * The peripheral clocks must be enabled once the Over-drive mode is activated. * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) { 8021068: b580 push {r7, lr} 802106a: b082 sub sp, #8 802106c: af00 add r7, sp, #0 uint32_t tickstart = 0; 802106e: 2300 movs r3, #0 8021070: 607b str r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8021072: 4b23 ldr r3, [pc, #140] ; (8021100 ) 8021074: 6c1b ldr r3, [r3, #64] ; 0x40 8021076: 4a22 ldr r2, [pc, #136] ; (8021100 ) 8021078: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 802107c: 6413 str r3, [r2, #64] ; 0x40 802107e: 4b20 ldr r3, [pc, #128] ; (8021100 ) 8021080: 6c1b ldr r3, [r3, #64] ; 0x40 8021082: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8021086: 603b str r3, [r7, #0] 8021088: 683b ldr r3, [r7, #0] /* Enable the Over-drive to extend the clock frequency to 216 MHz */ __HAL_PWR_OVERDRIVE_ENABLE(); 802108a: 4b1e ldr r3, [pc, #120] ; (8021104 ) 802108c: 681b ldr r3, [r3, #0] 802108e: 4a1d ldr r2, [pc, #116] ; (8021104 ) 8021090: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8021094: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 8021096: f7ff fce5 bl 8020a64 802109a: 6078 str r0, [r7, #4] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) 802109c: e009 b.n 80210b2 { if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) 802109e: f7ff fce1 bl 8020a64 80210a2: 4602 mov r2, r0 80210a4: 687b ldr r3, [r7, #4] 80210a6: 1ad3 subs r3, r2, r3 80210a8: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80210ac: d901 bls.n 80210b2 { return HAL_TIMEOUT; 80210ae: 2303 movs r3, #3 80210b0: e022 b.n 80210f8 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) 80210b2: 4b14 ldr r3, [pc, #80] ; (8021104 ) 80210b4: 685b ldr r3, [r3, #4] 80210b6: f403 3380 and.w r3, r3, #65536 ; 0x10000 80210ba: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80210be: d1ee bne.n 802109e } } /* Enable the Over-drive switch */ __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); 80210c0: 4b10 ldr r3, [pc, #64] ; (8021104 ) 80210c2: 681b ldr r3, [r3, #0] 80210c4: 4a0f ldr r2, [pc, #60] ; (8021104 ) 80210c6: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80210ca: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 80210cc: f7ff fcca bl 8020a64 80210d0: 6078 str r0, [r7, #4] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) 80210d2: e009 b.n 80210e8 { if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) 80210d4: f7ff fcc6 bl 8020a64 80210d8: 4602 mov r2, r0 80210da: 687b ldr r3, [r7, #4] 80210dc: 1ad3 subs r3, r2, r3 80210de: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80210e2: d901 bls.n 80210e8 { return HAL_TIMEOUT; 80210e4: 2303 movs r3, #3 80210e6: e007 b.n 80210f8 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) 80210e8: 4b06 ldr r3, [pc, #24] ; (8021104 ) 80210ea: 685b ldr r3, [r3, #4] 80210ec: f403 3300 and.w r3, r3, #131072 ; 0x20000 80210f0: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80210f4: d1ee bne.n 80210d4 } } return HAL_OK; 80210f6: 2300 movs r3, #0 } 80210f8: 4618 mov r0, r3 80210fa: 3708 adds r7, #8 80210fc: 46bd mov sp, r7 80210fe: bd80 pop {r7, pc} 8021100: 40023800 .word 0x40023800 8021104: 40007000 .word 0x40007000 08021108 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8021108: b580 push {r7, lr} 802110a: b086 sub sp, #24 802110c: af00 add r7, sp, #0 802110e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; FlagStatus pwrclkchanged = RESET; 8021110: 2300 movs r3, #0 8021112: 75fb strb r3, [r7, #23] /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8021114: 687b ldr r3, [r7, #4] 8021116: 2b00 cmp r3, #0 8021118: d101 bne.n 802111e { return HAL_ERROR; 802111a: 2301 movs r3, #1 802111c: e29b b.n 8021656 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 802111e: 687b ldr r3, [r7, #4] 8021120: 681b ldr r3, [r3, #0] 8021122: f003 0301 and.w r3, r3, #1 8021126: 2b00 cmp r3, #0 8021128: f000 8087 beq.w 802123a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 802112c: 4b96 ldr r3, [pc, #600] ; (8021388 ) 802112e: 689b ldr r3, [r3, #8] 8021130: f003 030c and.w r3, r3, #12 8021134: 2b04 cmp r3, #4 8021136: d00c beq.n 8021152 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8021138: 4b93 ldr r3, [pc, #588] ; (8021388 ) 802113a: 689b ldr r3, [r3, #8] 802113c: f003 030c and.w r3, r3, #12 8021140: 2b08 cmp r3, #8 8021142: d112 bne.n 802116a 8021144: 4b90 ldr r3, [pc, #576] ; (8021388 ) 8021146: 685b ldr r3, [r3, #4] 8021148: f403 0380 and.w r3, r3, #4194304 ; 0x400000 802114c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8021150: d10b bne.n 802116a { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8021152: 4b8d ldr r3, [pc, #564] ; (8021388 ) 8021154: 681b ldr r3, [r3, #0] 8021156: f403 3300 and.w r3, r3, #131072 ; 0x20000 802115a: 2b00 cmp r3, #0 802115c: d06c beq.n 8021238 802115e: 687b ldr r3, [r7, #4] 8021160: 685b ldr r3, [r3, #4] 8021162: 2b00 cmp r3, #0 8021164: d168 bne.n 8021238 { return HAL_ERROR; 8021166: 2301 movs r3, #1 8021168: e275 b.n 8021656 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 802116a: 687b ldr r3, [r7, #4] 802116c: 685b ldr r3, [r3, #4] 802116e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8021172: d106 bne.n 8021182 8021174: 4b84 ldr r3, [pc, #528] ; (8021388 ) 8021176: 681b ldr r3, [r3, #0] 8021178: 4a83 ldr r2, [pc, #524] ; (8021388 ) 802117a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 802117e: 6013 str r3, [r2, #0] 8021180: e02e b.n 80211e0 8021182: 687b ldr r3, [r7, #4] 8021184: 685b ldr r3, [r3, #4] 8021186: 2b00 cmp r3, #0 8021188: d10c bne.n 80211a4 802118a: 4b7f ldr r3, [pc, #508] ; (8021388 ) 802118c: 681b ldr r3, [r3, #0] 802118e: 4a7e ldr r2, [pc, #504] ; (8021388 ) 8021190: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8021194: 6013 str r3, [r2, #0] 8021196: 4b7c ldr r3, [pc, #496] ; (8021388 ) 8021198: 681b ldr r3, [r3, #0] 802119a: 4a7b ldr r2, [pc, #492] ; (8021388 ) 802119c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80211a0: 6013 str r3, [r2, #0] 80211a2: e01d b.n 80211e0 80211a4: 687b ldr r3, [r7, #4] 80211a6: 685b ldr r3, [r3, #4] 80211a8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80211ac: d10c bne.n 80211c8 80211ae: 4b76 ldr r3, [pc, #472] ; (8021388 ) 80211b0: 681b ldr r3, [r3, #0] 80211b2: 4a75 ldr r2, [pc, #468] ; (8021388 ) 80211b4: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80211b8: 6013 str r3, [r2, #0] 80211ba: 4b73 ldr r3, [pc, #460] ; (8021388 ) 80211bc: 681b ldr r3, [r3, #0] 80211be: 4a72 ldr r2, [pc, #456] ; (8021388 ) 80211c0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80211c4: 6013 str r3, [r2, #0] 80211c6: e00b b.n 80211e0 80211c8: 4b6f ldr r3, [pc, #444] ; (8021388 ) 80211ca: 681b ldr r3, [r3, #0] 80211cc: 4a6e ldr r2, [pc, #440] ; (8021388 ) 80211ce: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80211d2: 6013 str r3, [r2, #0] 80211d4: 4b6c ldr r3, [pc, #432] ; (8021388 ) 80211d6: 681b ldr r3, [r3, #0] 80211d8: 4a6b ldr r2, [pc, #428] ; (8021388 ) 80211da: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80211de: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80211e0: 687b ldr r3, [r7, #4] 80211e2: 685b ldr r3, [r3, #4] 80211e4: 2b00 cmp r3, #0 80211e6: d013 beq.n 8021210 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80211e8: f7ff fc3c bl 8020a64 80211ec: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80211ee: e008 b.n 8021202 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80211f0: f7ff fc38 bl 8020a64 80211f4: 4602 mov r2, r0 80211f6: 693b ldr r3, [r7, #16] 80211f8: 1ad3 subs r3, r2, r3 80211fa: 2b64 cmp r3, #100 ; 0x64 80211fc: d901 bls.n 8021202 { return HAL_TIMEOUT; 80211fe: 2303 movs r3, #3 8021200: e229 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8021202: 4b61 ldr r3, [pc, #388] ; (8021388 ) 8021204: 681b ldr r3, [r3, #0] 8021206: f403 3300 and.w r3, r3, #131072 ; 0x20000 802120a: 2b00 cmp r3, #0 802120c: d0f0 beq.n 80211f0 802120e: e014 b.n 802123a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021210: f7ff fc28 bl 8020a64 8021214: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8021216: e008 b.n 802122a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8021218: f7ff fc24 bl 8020a64 802121c: 4602 mov r2, r0 802121e: 693b ldr r3, [r7, #16] 8021220: 1ad3 subs r3, r2, r3 8021222: 2b64 cmp r3, #100 ; 0x64 8021224: d901 bls.n 802122a { return HAL_TIMEOUT; 8021226: 2303 movs r3, #3 8021228: e215 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 802122a: 4b57 ldr r3, [pc, #348] ; (8021388 ) 802122c: 681b ldr r3, [r3, #0] 802122e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8021232: 2b00 cmp r3, #0 8021234: d1f0 bne.n 8021218 8021236: e000 b.n 802123a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8021238: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 802123a: 687b ldr r3, [r7, #4] 802123c: 681b ldr r3, [r3, #0] 802123e: f003 0302 and.w r3, r3, #2 8021242: 2b00 cmp r3, #0 8021244: d069 beq.n 802131a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8021246: 4b50 ldr r3, [pc, #320] ; (8021388 ) 8021248: 689b ldr r3, [r3, #8] 802124a: f003 030c and.w r3, r3, #12 802124e: 2b00 cmp r3, #0 8021250: d00b beq.n 802126a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8021252: 4b4d ldr r3, [pc, #308] ; (8021388 ) 8021254: 689b ldr r3, [r3, #8] 8021256: f003 030c and.w r3, r3, #12 802125a: 2b08 cmp r3, #8 802125c: d11c bne.n 8021298 802125e: 4b4a ldr r3, [pc, #296] ; (8021388 ) 8021260: 685b ldr r3, [r3, #4] 8021262: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8021266: 2b00 cmp r3, #0 8021268: d116 bne.n 8021298 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 802126a: 4b47 ldr r3, [pc, #284] ; (8021388 ) 802126c: 681b ldr r3, [r3, #0] 802126e: f003 0302 and.w r3, r3, #2 8021272: 2b00 cmp r3, #0 8021274: d005 beq.n 8021282 8021276: 687b ldr r3, [r7, #4] 8021278: 68db ldr r3, [r3, #12] 802127a: 2b01 cmp r3, #1 802127c: d001 beq.n 8021282 { return HAL_ERROR; 802127e: 2301 movs r3, #1 8021280: e1e9 b.n 8021656 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8021282: 4b41 ldr r3, [pc, #260] ; (8021388 ) 8021284: 681b ldr r3, [r3, #0] 8021286: f023 02f8 bic.w r2, r3, #248 ; 0xf8 802128a: 687b ldr r3, [r7, #4] 802128c: 691b ldr r3, [r3, #16] 802128e: 00db lsls r3, r3, #3 8021290: 493d ldr r1, [pc, #244] ; (8021388 ) 8021292: 4313 orrs r3, r2 8021294: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8021296: e040 b.n 802131a } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8021298: 687b ldr r3, [r7, #4] 802129a: 68db ldr r3, [r3, #12] 802129c: 2b00 cmp r3, #0 802129e: d023 beq.n 80212e8 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80212a0: 4b39 ldr r3, [pc, #228] ; (8021388 ) 80212a2: 681b ldr r3, [r3, #0] 80212a4: 4a38 ldr r2, [pc, #224] ; (8021388 ) 80212a6: f043 0301 orr.w r3, r3, #1 80212aa: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80212ac: f7ff fbda bl 8020a64 80212b0: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80212b2: e008 b.n 80212c6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80212b4: f7ff fbd6 bl 8020a64 80212b8: 4602 mov r2, r0 80212ba: 693b ldr r3, [r7, #16] 80212bc: 1ad3 subs r3, r2, r3 80212be: 2b02 cmp r3, #2 80212c0: d901 bls.n 80212c6 { return HAL_TIMEOUT; 80212c2: 2303 movs r3, #3 80212c4: e1c7 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80212c6: 4b30 ldr r3, [pc, #192] ; (8021388 ) 80212c8: 681b ldr r3, [r3, #0] 80212ca: f003 0302 and.w r3, r3, #2 80212ce: 2b00 cmp r3, #0 80212d0: d0f0 beq.n 80212b4 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80212d2: 4b2d ldr r3, [pc, #180] ; (8021388 ) 80212d4: 681b ldr r3, [r3, #0] 80212d6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80212da: 687b ldr r3, [r7, #4] 80212dc: 691b ldr r3, [r3, #16] 80212de: 00db lsls r3, r3, #3 80212e0: 4929 ldr r1, [pc, #164] ; (8021388 ) 80212e2: 4313 orrs r3, r2 80212e4: 600b str r3, [r1, #0] 80212e6: e018 b.n 802131a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80212e8: 4b27 ldr r3, [pc, #156] ; (8021388 ) 80212ea: 681b ldr r3, [r3, #0] 80212ec: 4a26 ldr r2, [pc, #152] ; (8021388 ) 80212ee: f023 0301 bic.w r3, r3, #1 80212f2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80212f4: f7ff fbb6 bl 8020a64 80212f8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80212fa: e008 b.n 802130e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80212fc: f7ff fbb2 bl 8020a64 8021300: 4602 mov r2, r0 8021302: 693b ldr r3, [r7, #16] 8021304: 1ad3 subs r3, r2, r3 8021306: 2b02 cmp r3, #2 8021308: d901 bls.n 802130e { return HAL_TIMEOUT; 802130a: 2303 movs r3, #3 802130c: e1a3 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 802130e: 4b1e ldr r3, [pc, #120] ; (8021388 ) 8021310: 681b ldr r3, [r3, #0] 8021312: f003 0302 and.w r3, r3, #2 8021316: 2b00 cmp r3, #0 8021318: d1f0 bne.n 80212fc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 802131a: 687b ldr r3, [r7, #4] 802131c: 681b ldr r3, [r3, #0] 802131e: f003 0308 and.w r3, r3, #8 8021322: 2b00 cmp r3, #0 8021324: d038 beq.n 8021398 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8021326: 687b ldr r3, [r7, #4] 8021328: 695b ldr r3, [r3, #20] 802132a: 2b00 cmp r3, #0 802132c: d019 beq.n 8021362 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 802132e: 4b16 ldr r3, [pc, #88] ; (8021388 ) 8021330: 6f5b ldr r3, [r3, #116] ; 0x74 8021332: 4a15 ldr r2, [pc, #84] ; (8021388 ) 8021334: f043 0301 orr.w r3, r3, #1 8021338: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 802133a: f7ff fb93 bl 8020a64 802133e: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8021340: e008 b.n 8021354 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8021342: f7ff fb8f bl 8020a64 8021346: 4602 mov r2, r0 8021348: 693b ldr r3, [r7, #16] 802134a: 1ad3 subs r3, r2, r3 802134c: 2b02 cmp r3, #2 802134e: d901 bls.n 8021354 { return HAL_TIMEOUT; 8021350: 2303 movs r3, #3 8021352: e180 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8021354: 4b0c ldr r3, [pc, #48] ; (8021388 ) 8021356: 6f5b ldr r3, [r3, #116] ; 0x74 8021358: f003 0302 and.w r3, r3, #2 802135c: 2b00 cmp r3, #0 802135e: d0f0 beq.n 8021342 8021360: e01a b.n 8021398 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8021362: 4b09 ldr r3, [pc, #36] ; (8021388 ) 8021364: 6f5b ldr r3, [r3, #116] ; 0x74 8021366: 4a08 ldr r2, [pc, #32] ; (8021388 ) 8021368: f023 0301 bic.w r3, r3, #1 802136c: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 802136e: f7ff fb79 bl 8020a64 8021372: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8021374: e00a b.n 802138c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8021376: f7ff fb75 bl 8020a64 802137a: 4602 mov r2, r0 802137c: 693b ldr r3, [r7, #16] 802137e: 1ad3 subs r3, r2, r3 8021380: 2b02 cmp r3, #2 8021382: d903 bls.n 802138c { return HAL_TIMEOUT; 8021384: 2303 movs r3, #3 8021386: e166 b.n 8021656 8021388: 40023800 .word 0x40023800 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 802138c: 4b92 ldr r3, [pc, #584] ; (80215d8 ) 802138e: 6f5b ldr r3, [r3, #116] ; 0x74 8021390: f003 0302 and.w r3, r3, #2 8021394: 2b00 cmp r3, #0 8021396: d1ee bne.n 8021376 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8021398: 687b ldr r3, [r7, #4] 802139a: 681b ldr r3, [r3, #0] 802139c: f003 0304 and.w r3, r3, #4 80213a0: 2b00 cmp r3, #0 80213a2: f000 80a4 beq.w 80214ee /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80213a6: 4b8c ldr r3, [pc, #560] ; (80215d8 ) 80213a8: 6c1b ldr r3, [r3, #64] ; 0x40 80213aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80213ae: 2b00 cmp r3, #0 80213b0: d10d bne.n 80213ce { /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 80213b2: 4b89 ldr r3, [pc, #548] ; (80215d8 ) 80213b4: 6c1b ldr r3, [r3, #64] ; 0x40 80213b6: 4a88 ldr r2, [pc, #544] ; (80215d8 ) 80213b8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80213bc: 6413 str r3, [r2, #64] ; 0x40 80213be: 4b86 ldr r3, [pc, #536] ; (80215d8 ) 80213c0: 6c1b ldr r3, [r3, #64] ; 0x40 80213c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80213c6: 60bb str r3, [r7, #8] 80213c8: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80213ca: 2301 movs r3, #1 80213cc: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80213ce: 4b83 ldr r3, [pc, #524] ; (80215dc ) 80213d0: 681b ldr r3, [r3, #0] 80213d2: f403 7380 and.w r3, r3, #256 ; 0x100 80213d6: 2b00 cmp r3, #0 80213d8: d118 bne.n 802140c { /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 80213da: 4b80 ldr r3, [pc, #512] ; (80215dc ) 80213dc: 681b ldr r3, [r3, #0] 80213de: 4a7f ldr r2, [pc, #508] ; (80215dc ) 80213e0: f443 7380 orr.w r3, r3, #256 ; 0x100 80213e4: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80213e6: f7ff fb3d bl 8020a64 80213ea: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80213ec: e008 b.n 8021400 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80213ee: f7ff fb39 bl 8020a64 80213f2: 4602 mov r2, r0 80213f4: 693b ldr r3, [r7, #16] 80213f6: 1ad3 subs r3, r2, r3 80213f8: 2b64 cmp r3, #100 ; 0x64 80213fa: d901 bls.n 8021400 { return HAL_TIMEOUT; 80213fc: 2303 movs r3, #3 80213fe: e12a b.n 8021656 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8021400: 4b76 ldr r3, [pc, #472] ; (80215dc ) 8021402: 681b ldr r3, [r3, #0] 8021404: f403 7380 and.w r3, r3, #256 ; 0x100 8021408: 2b00 cmp r3, #0 802140a: d0f0 beq.n 80213ee } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 802140c: 687b ldr r3, [r7, #4] 802140e: 689b ldr r3, [r3, #8] 8021410: 2b01 cmp r3, #1 8021412: d106 bne.n 8021422 8021414: 4b70 ldr r3, [pc, #448] ; (80215d8 ) 8021416: 6f1b ldr r3, [r3, #112] ; 0x70 8021418: 4a6f ldr r2, [pc, #444] ; (80215d8 ) 802141a: f043 0301 orr.w r3, r3, #1 802141e: 6713 str r3, [r2, #112] ; 0x70 8021420: e02d b.n 802147e 8021422: 687b ldr r3, [r7, #4] 8021424: 689b ldr r3, [r3, #8] 8021426: 2b00 cmp r3, #0 8021428: d10c bne.n 8021444 802142a: 4b6b ldr r3, [pc, #428] ; (80215d8 ) 802142c: 6f1b ldr r3, [r3, #112] ; 0x70 802142e: 4a6a ldr r2, [pc, #424] ; (80215d8 ) 8021430: f023 0301 bic.w r3, r3, #1 8021434: 6713 str r3, [r2, #112] ; 0x70 8021436: 4b68 ldr r3, [pc, #416] ; (80215d8 ) 8021438: 6f1b ldr r3, [r3, #112] ; 0x70 802143a: 4a67 ldr r2, [pc, #412] ; (80215d8 ) 802143c: f023 0304 bic.w r3, r3, #4 8021440: 6713 str r3, [r2, #112] ; 0x70 8021442: e01c b.n 802147e 8021444: 687b ldr r3, [r7, #4] 8021446: 689b ldr r3, [r3, #8] 8021448: 2b05 cmp r3, #5 802144a: d10c bne.n 8021466 802144c: 4b62 ldr r3, [pc, #392] ; (80215d8 ) 802144e: 6f1b ldr r3, [r3, #112] ; 0x70 8021450: 4a61 ldr r2, [pc, #388] ; (80215d8 ) 8021452: f043 0304 orr.w r3, r3, #4 8021456: 6713 str r3, [r2, #112] ; 0x70 8021458: 4b5f ldr r3, [pc, #380] ; (80215d8 ) 802145a: 6f1b ldr r3, [r3, #112] ; 0x70 802145c: 4a5e ldr r2, [pc, #376] ; (80215d8 ) 802145e: f043 0301 orr.w r3, r3, #1 8021462: 6713 str r3, [r2, #112] ; 0x70 8021464: e00b b.n 802147e 8021466: 4b5c ldr r3, [pc, #368] ; (80215d8 ) 8021468: 6f1b ldr r3, [r3, #112] ; 0x70 802146a: 4a5b ldr r2, [pc, #364] ; (80215d8 ) 802146c: f023 0301 bic.w r3, r3, #1 8021470: 6713 str r3, [r2, #112] ; 0x70 8021472: 4b59 ldr r3, [pc, #356] ; (80215d8 ) 8021474: 6f1b ldr r3, [r3, #112] ; 0x70 8021476: 4a58 ldr r2, [pc, #352] ; (80215d8 ) 8021478: f023 0304 bic.w r3, r3, #4 802147c: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 802147e: 687b ldr r3, [r7, #4] 8021480: 689b ldr r3, [r3, #8] 8021482: 2b00 cmp r3, #0 8021484: d015 beq.n 80214b2 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021486: f7ff faed bl 8020a64 802148a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 802148c: e00a b.n 80214a4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 802148e: f7ff fae9 bl 8020a64 8021492: 4602 mov r2, r0 8021494: 693b ldr r3, [r7, #16] 8021496: 1ad3 subs r3, r2, r3 8021498: f241 3288 movw r2, #5000 ; 0x1388 802149c: 4293 cmp r3, r2 802149e: d901 bls.n 80214a4 { return HAL_TIMEOUT; 80214a0: 2303 movs r3, #3 80214a2: e0d8 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80214a4: 4b4c ldr r3, [pc, #304] ; (80215d8 ) 80214a6: 6f1b ldr r3, [r3, #112] ; 0x70 80214a8: f003 0302 and.w r3, r3, #2 80214ac: 2b00 cmp r3, #0 80214ae: d0ee beq.n 802148e 80214b0: e014 b.n 80214dc } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80214b2: f7ff fad7 bl 8020a64 80214b6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80214b8: e00a b.n 80214d0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80214ba: f7ff fad3 bl 8020a64 80214be: 4602 mov r2, r0 80214c0: 693b ldr r3, [r7, #16] 80214c2: 1ad3 subs r3, r2, r3 80214c4: f241 3288 movw r2, #5000 ; 0x1388 80214c8: 4293 cmp r3, r2 80214ca: d901 bls.n 80214d0 { return HAL_TIMEOUT; 80214cc: 2303 movs r3, #3 80214ce: e0c2 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80214d0: 4b41 ldr r3, [pc, #260] ; (80215d8 ) 80214d2: 6f1b ldr r3, [r3, #112] ; 0x70 80214d4: f003 0302 and.w r3, r3, #2 80214d8: 2b00 cmp r3, #0 80214da: d1ee bne.n 80214ba } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80214dc: 7dfb ldrb r3, [r7, #23] 80214de: 2b01 cmp r3, #1 80214e0: d105 bne.n 80214ee { __HAL_RCC_PWR_CLK_DISABLE(); 80214e2: 4b3d ldr r3, [pc, #244] ; (80215d8 ) 80214e4: 6c1b ldr r3, [r3, #64] ; 0x40 80214e6: 4a3c ldr r2, [pc, #240] ; (80215d8 ) 80214e8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 80214ec: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80214ee: 687b ldr r3, [r7, #4] 80214f0: 699b ldr r3, [r3, #24] 80214f2: 2b00 cmp r3, #0 80214f4: f000 80ae beq.w 8021654 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80214f8: 4b37 ldr r3, [pc, #220] ; (80215d8 ) 80214fa: 689b ldr r3, [r3, #8] 80214fc: f003 030c and.w r3, r3, #12 8021500: 2b08 cmp r3, #8 8021502: d06d beq.n 80215e0 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8021504: 687b ldr r3, [r7, #4] 8021506: 699b ldr r3, [r3, #24] 8021508: 2b02 cmp r3, #2 802150a: d14b bne.n 80215a4 #if defined (RCC_PLLCFGR_PLLR) assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 802150c: 4b32 ldr r3, [pc, #200] ; (80215d8 ) 802150e: 681b ldr r3, [r3, #0] 8021510: 4a31 ldr r2, [pc, #196] ; (80215d8 ) 8021512: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8021516: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021518: f7ff faa4 bl 8020a64 802151c: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 802151e: e008 b.n 8021532 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8021520: f7ff faa0 bl 8020a64 8021524: 4602 mov r2, r0 8021526: 693b ldr r3, [r7, #16] 8021528: 1ad3 subs r3, r2, r3 802152a: 2b02 cmp r3, #2 802152c: d901 bls.n 8021532 { return HAL_TIMEOUT; 802152e: 2303 movs r3, #3 8021530: e091 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8021532: 4b29 ldr r3, [pc, #164] ; (80215d8 ) 8021534: 681b ldr r3, [r3, #0] 8021536: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 802153a: 2b00 cmp r3, #0 802153c: d1f0 bne.n 8021520 } } /* Configure the main PLL clock source, multiplication and division factors. */ #if defined (RCC_PLLCFGR_PLLR) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 802153e: 687b ldr r3, [r7, #4] 8021540: 69da ldr r2, [r3, #28] 8021542: 687b ldr r3, [r7, #4] 8021544: 6a1b ldr r3, [r3, #32] 8021546: 431a orrs r2, r3 8021548: 687b ldr r3, [r7, #4] 802154a: 6a5b ldr r3, [r3, #36] ; 0x24 802154c: 019b lsls r3, r3, #6 802154e: 431a orrs r2, r3 8021550: 687b ldr r3, [r7, #4] 8021552: 6a9b ldr r3, [r3, #40] ; 0x28 8021554: 085b lsrs r3, r3, #1 8021556: 3b01 subs r3, #1 8021558: 041b lsls r3, r3, #16 802155a: 431a orrs r2, r3 802155c: 687b ldr r3, [r7, #4] 802155e: 6adb ldr r3, [r3, #44] ; 0x2c 8021560: 061b lsls r3, r3, #24 8021562: 431a orrs r2, r3 8021564: 687b ldr r3, [r7, #4] 8021566: 6b1b ldr r3, [r3, #48] ; 0x30 8021568: 071b lsls r3, r3, #28 802156a: 491b ldr r1, [pc, #108] ; (80215d8 ) 802156c: 4313 orrs r3, r2 802156e: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ); #endif /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8021570: 4b19 ldr r3, [pc, #100] ; (80215d8 ) 8021572: 681b ldr r3, [r3, #0] 8021574: 4a18 ldr r2, [pc, #96] ; (80215d8 ) 8021576: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 802157a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 802157c: f7ff fa72 bl 8020a64 8021580: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8021582: e008 b.n 8021596 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8021584: f7ff fa6e bl 8020a64 8021588: 4602 mov r2, r0 802158a: 693b ldr r3, [r7, #16] 802158c: 1ad3 subs r3, r2, r3 802158e: 2b02 cmp r3, #2 8021590: d901 bls.n 8021596 { return HAL_TIMEOUT; 8021592: 2303 movs r3, #3 8021594: e05f b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8021596: 4b10 ldr r3, [pc, #64] ; (80215d8 ) 8021598: 681b ldr r3, [r3, #0] 802159a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 802159e: 2b00 cmp r3, #0 80215a0: d0f0 beq.n 8021584 80215a2: e057 b.n 8021654 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80215a4: 4b0c ldr r3, [pc, #48] ; (80215d8 ) 80215a6: 681b ldr r3, [r3, #0] 80215a8: 4a0b ldr r2, [pc, #44] ; (80215d8 ) 80215aa: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 80215ae: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80215b0: f7ff fa58 bl 8020a64 80215b4: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80215b6: e008 b.n 80215ca { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80215b8: f7ff fa54 bl 8020a64 80215bc: 4602 mov r2, r0 80215be: 693b ldr r3, [r7, #16] 80215c0: 1ad3 subs r3, r2, r3 80215c2: 2b02 cmp r3, #2 80215c4: d901 bls.n 80215ca { return HAL_TIMEOUT; 80215c6: 2303 movs r3, #3 80215c8: e045 b.n 8021656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80215ca: 4b03 ldr r3, [pc, #12] ; (80215d8 ) 80215cc: 681b ldr r3, [r3, #0] 80215ce: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80215d2: 2b00 cmp r3, #0 80215d4: d1f0 bne.n 80215b8 80215d6: e03d b.n 8021654 80215d8: 40023800 .word 0x40023800 80215dc: 40007000 .word 0x40007000 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80215e0: 4b1f ldr r3, [pc, #124] ; (8021660 ) 80215e2: 685b ldr r3, [r3, #4] 80215e4: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80215e6: 687b ldr r3, [r7, #4] 80215e8: 699b ldr r3, [r3, #24] 80215ea: 2b01 cmp r3, #1 80215ec: d030 beq.n 8021650 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80215ee: 68fb ldr r3, [r7, #12] 80215f0: f403 0280 and.w r2, r3, #4194304 ; 0x400000 80215f4: 687b ldr r3, [r7, #4] 80215f6: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80215f8: 429a cmp r2, r3 80215fa: d129 bne.n 8021650 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 80215fc: 68fb ldr r3, [r7, #12] 80215fe: f003 023f and.w r2, r3, #63 ; 0x3f 8021602: 687b ldr r3, [r7, #4] 8021604: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8021606: 429a cmp r2, r3 8021608: d122 bne.n 8021650 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 802160a: 68fa ldr r2, [r7, #12] 802160c: f647 73c0 movw r3, #32704 ; 0x7fc0 8021610: 4013 ands r3, r2 8021612: 687a ldr r2, [r7, #4] 8021614: 6a52 ldr r2, [r2, #36] ; 0x24 8021616: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8021618: 4293 cmp r3, r2 802161a: d119 bne.n 8021650 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || 802161c: 68fb ldr r3, [r7, #12] 802161e: f403 3240 and.w r2, r3, #196608 ; 0x30000 8021622: 687b ldr r3, [r7, #4] 8021624: 6a9b ldr r3, [r3, #40] ; 0x28 8021626: 085b lsrs r3, r3, #1 8021628: 3b01 subs r3, #1 802162a: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 802162c: 429a cmp r2, r3 802162e: d10f bne.n 8021650 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8021630: 68fb ldr r3, [r7, #12] 8021632: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 8021636: 687b ldr r3, [r7, #4] 8021638: 6adb ldr r3, [r3, #44] ; 0x2c 802163a: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || 802163c: 429a cmp r2, r3 802163e: d107 bne.n 8021650 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 8021640: 68fb ldr r3, [r7, #12] 8021642: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 8021646: 687b ldr r3, [r7, #4] 8021648: 6b1b ldr r3, [r3, #48] ; 0x30 802164a: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 802164c: 429a cmp r2, r3 802164e: d001 beq.n 8021654 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif { return HAL_ERROR; 8021650: 2301 movs r3, #1 8021652: e000 b.n 8021656 } } } return HAL_OK; 8021654: 2300 movs r3, #0 } 8021656: 4618 mov r0, r3 8021658: 3718 adds r7, #24 802165a: 46bd mov sp, r7 802165c: bd80 pop {r7, pc} 802165e: bf00 nop 8021660: 40023800 .word 0x40023800 08021664 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8021664: b580 push {r7, lr} 8021666: b084 sub sp, #16 8021668: af00 add r7, sp, #0 802166a: 6078 str r0, [r7, #4] 802166c: 6039 str r1, [r7, #0] uint32_t tickstart = 0; 802166e: 2300 movs r3, #0 8021670: 60fb str r3, [r7, #12] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8021672: 687b ldr r3, [r7, #4] 8021674: 2b00 cmp r3, #0 8021676: d101 bne.n 802167c { return HAL_ERROR; 8021678: 2301 movs r3, #1 802167a: e0d0 b.n 802181e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 802167c: 4b6a ldr r3, [pc, #424] ; (8021828 ) 802167e: 681b ldr r3, [r3, #0] 8021680: f003 030f and.w r3, r3, #15 8021684: 683a ldr r2, [r7, #0] 8021686: 429a cmp r2, r3 8021688: d910 bls.n 80216ac { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 802168a: 4b67 ldr r3, [pc, #412] ; (8021828 ) 802168c: 681b ldr r3, [r3, #0] 802168e: f023 020f bic.w r2, r3, #15 8021692: 4965 ldr r1, [pc, #404] ; (8021828 ) 8021694: 683b ldr r3, [r7, #0] 8021696: 4313 orrs r3, r2 8021698: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 802169a: 4b63 ldr r3, [pc, #396] ; (8021828 ) 802169c: 681b ldr r3, [r3, #0] 802169e: f003 030f and.w r3, r3, #15 80216a2: 683a ldr r2, [r7, #0] 80216a4: 429a cmp r2, r3 80216a6: d001 beq.n 80216ac { return HAL_ERROR; 80216a8: 2301 movs r3, #1 80216aa: e0b8 b.n 802181e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80216ac: 687b ldr r3, [r7, #4] 80216ae: 681b ldr r3, [r3, #0] 80216b0: f003 0302 and.w r3, r3, #2 80216b4: 2b00 cmp r3, #0 80216b6: d020 beq.n 80216fa { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80216b8: 687b ldr r3, [r7, #4] 80216ba: 681b ldr r3, [r3, #0] 80216bc: f003 0304 and.w r3, r3, #4 80216c0: 2b00 cmp r3, #0 80216c2: d005 beq.n 80216d0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80216c4: 4b59 ldr r3, [pc, #356] ; (802182c ) 80216c6: 689b ldr r3, [r3, #8] 80216c8: 4a58 ldr r2, [pc, #352] ; (802182c ) 80216ca: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 80216ce: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80216d0: 687b ldr r3, [r7, #4] 80216d2: 681b ldr r3, [r3, #0] 80216d4: f003 0308 and.w r3, r3, #8 80216d8: 2b00 cmp r3, #0 80216da: d005 beq.n 80216e8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80216dc: 4b53 ldr r3, [pc, #332] ; (802182c ) 80216de: 689b ldr r3, [r3, #8] 80216e0: 4a52 ldr r2, [pc, #328] ; (802182c ) 80216e2: f443 4360 orr.w r3, r3, #57344 ; 0xe000 80216e6: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80216e8: 4b50 ldr r3, [pc, #320] ; (802182c ) 80216ea: 689b ldr r3, [r3, #8] 80216ec: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80216f0: 687b ldr r3, [r7, #4] 80216f2: 689b ldr r3, [r3, #8] 80216f4: 494d ldr r1, [pc, #308] ; (802182c ) 80216f6: 4313 orrs r3, r2 80216f8: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80216fa: 687b ldr r3, [r7, #4] 80216fc: 681b ldr r3, [r3, #0] 80216fe: f003 0301 and.w r3, r3, #1 8021702: 2b00 cmp r3, #0 8021704: d040 beq.n 8021788 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8021706: 687b ldr r3, [r7, #4] 8021708: 685b ldr r3, [r3, #4] 802170a: 2b01 cmp r3, #1 802170c: d107 bne.n 802171e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 802170e: 4b47 ldr r3, [pc, #284] ; (802182c ) 8021710: 681b ldr r3, [r3, #0] 8021712: f403 3300 and.w r3, r3, #131072 ; 0x20000 8021716: 2b00 cmp r3, #0 8021718: d115 bne.n 8021746 { return HAL_ERROR; 802171a: 2301 movs r3, #1 802171c: e07f b.n 802181e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 802171e: 687b ldr r3, [r7, #4] 8021720: 685b ldr r3, [r3, #4] 8021722: 2b02 cmp r3, #2 8021724: d107 bne.n 8021736 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8021726: 4b41 ldr r3, [pc, #260] ; (802182c ) 8021728: 681b ldr r3, [r3, #0] 802172a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 802172e: 2b00 cmp r3, #0 8021730: d109 bne.n 8021746 { return HAL_ERROR; 8021732: 2301 movs r3, #1 8021734: e073 b.n 802181e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8021736: 4b3d ldr r3, [pc, #244] ; (802182c ) 8021738: 681b ldr r3, [r3, #0] 802173a: f003 0302 and.w r3, r3, #2 802173e: 2b00 cmp r3, #0 8021740: d101 bne.n 8021746 { return HAL_ERROR; 8021742: 2301 movs r3, #1 8021744: e06b b.n 802181e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8021746: 4b39 ldr r3, [pc, #228] ; (802182c ) 8021748: 689b ldr r3, [r3, #8] 802174a: f023 0203 bic.w r2, r3, #3 802174e: 687b ldr r3, [r7, #4] 8021750: 685b ldr r3, [r3, #4] 8021752: 4936 ldr r1, [pc, #216] ; (802182c ) 8021754: 4313 orrs r3, r2 8021756: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021758: f7ff f984 bl 8020a64 802175c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 802175e: e00a b.n 8021776 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8021760: f7ff f980 bl 8020a64 8021764: 4602 mov r2, r0 8021766: 68fb ldr r3, [r7, #12] 8021768: 1ad3 subs r3, r2, r3 802176a: f241 3288 movw r2, #5000 ; 0x1388 802176e: 4293 cmp r3, r2 8021770: d901 bls.n 8021776 { return HAL_TIMEOUT; 8021772: 2303 movs r3, #3 8021774: e053 b.n 802181e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8021776: 4b2d ldr r3, [pc, #180] ; (802182c ) 8021778: 689b ldr r3, [r3, #8] 802177a: f003 020c and.w r2, r3, #12 802177e: 687b ldr r3, [r7, #4] 8021780: 685b ldr r3, [r3, #4] 8021782: 009b lsls r3, r3, #2 8021784: 429a cmp r2, r3 8021786: d1eb bne.n 8021760 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8021788: 4b27 ldr r3, [pc, #156] ; (8021828 ) 802178a: 681b ldr r3, [r3, #0] 802178c: f003 030f and.w r3, r3, #15 8021790: 683a ldr r2, [r7, #0] 8021792: 429a cmp r2, r3 8021794: d210 bcs.n 80217b8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8021796: 4b24 ldr r3, [pc, #144] ; (8021828 ) 8021798: 681b ldr r3, [r3, #0] 802179a: f023 020f bic.w r2, r3, #15 802179e: 4922 ldr r1, [pc, #136] ; (8021828 ) 80217a0: 683b ldr r3, [r7, #0] 80217a2: 4313 orrs r3, r2 80217a4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80217a6: 4b20 ldr r3, [pc, #128] ; (8021828 ) 80217a8: 681b ldr r3, [r3, #0] 80217aa: f003 030f and.w r3, r3, #15 80217ae: 683a ldr r2, [r7, #0] 80217b0: 429a cmp r2, r3 80217b2: d001 beq.n 80217b8 { return HAL_ERROR; 80217b4: 2301 movs r3, #1 80217b6: e032 b.n 802181e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80217b8: 687b ldr r3, [r7, #4] 80217ba: 681b ldr r3, [r3, #0] 80217bc: f003 0304 and.w r3, r3, #4 80217c0: 2b00 cmp r3, #0 80217c2: d008 beq.n 80217d6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80217c4: 4b19 ldr r3, [pc, #100] ; (802182c ) 80217c6: 689b ldr r3, [r3, #8] 80217c8: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 80217cc: 687b ldr r3, [r7, #4] 80217ce: 68db ldr r3, [r3, #12] 80217d0: 4916 ldr r1, [pc, #88] ; (802182c ) 80217d2: 4313 orrs r3, r2 80217d4: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80217d6: 687b ldr r3, [r7, #4] 80217d8: 681b ldr r3, [r3, #0] 80217da: f003 0308 and.w r3, r3, #8 80217de: 2b00 cmp r3, #0 80217e0: d009 beq.n 80217f6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80217e2: 4b12 ldr r3, [pc, #72] ; (802182c ) 80217e4: 689b ldr r3, [r3, #8] 80217e6: f423 4260 bic.w r2, r3, #57344 ; 0xe000 80217ea: 687b ldr r3, [r7, #4] 80217ec: 691b ldr r3, [r3, #16] 80217ee: 00db lsls r3, r3, #3 80217f0: 490e ldr r1, [pc, #56] ; (802182c ) 80217f2: 4313 orrs r3, r2 80217f4: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80217f6: f000 f821 bl 802183c 80217fa: 4601 mov r1, r0 80217fc: 4b0b ldr r3, [pc, #44] ; (802182c ) 80217fe: 689b ldr r3, [r3, #8] 8021800: 091b lsrs r3, r3, #4 8021802: f003 030f and.w r3, r3, #15 8021806: 4a0a ldr r2, [pc, #40] ; (8021830 ) 8021808: 5cd3 ldrb r3, [r2, r3] 802180a: fa21 f303 lsr.w r3, r1, r3 802180e: 4a09 ldr r2, [pc, #36] ; (8021834 ) 8021810: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8021812: 4b09 ldr r3, [pc, #36] ; (8021838 ) 8021814: 681b ldr r3, [r3, #0] 8021816: 4618 mov r0, r3 8021818: f7ff f8e0 bl 80209dc return HAL_OK; 802181c: 2300 movs r3, #0 } 802181e: 4618 mov r0, r3 8021820: 3710 adds r7, #16 8021822: 46bd mov sp, r7 8021824: bd80 pop {r7, pc} 8021826: bf00 nop 8021828: 40023c00 .word 0x40023c00 802182c: 40023800 .word 0x40023800 8021830: 080222a8 .word 0x080222a8 8021834: 20000000 .word 0x20000000 8021838: 20000004 .word 0x20000004 0802183c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 802183c: b5f0 push {r4, r5, r6, r7, lr} 802183e: b085 sub sp, #20 8021840: af00 add r7, sp, #0 uint32_t pllm = 0, pllvco = 0, pllp = 0; 8021842: 2300 movs r3, #0 8021844: 607b str r3, [r7, #4] 8021846: 2300 movs r3, #0 8021848: 60fb str r3, [r7, #12] 802184a: 2300 movs r3, #0 802184c: 603b str r3, [r7, #0] uint32_t sysclockfreq = 0; 802184e: 2300 movs r3, #0 8021850: 60bb str r3, [r7, #8] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8021852: 4b63 ldr r3, [pc, #396] ; (80219e0 ) 8021854: 689b ldr r3, [r3, #8] 8021856: f003 030c and.w r3, r3, #12 802185a: 2b04 cmp r3, #4 802185c: d007 beq.n 802186e 802185e: 2b08 cmp r3, #8 8021860: d008 beq.n 8021874 8021862: 2b00 cmp r3, #0 8021864: f040 80b4 bne.w 80219d0 { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8021868: 4b5e ldr r3, [pc, #376] ; (80219e4 ) 802186a: 60bb str r3, [r7, #8] break; 802186c: e0b3 b.n 80219d6 } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 802186e: 4b5e ldr r3, [pc, #376] ; (80219e8 ) 8021870: 60bb str r3, [r7, #8] break; 8021872: e0b0 b.n 80219d6 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8021874: 4b5a ldr r3, [pc, #360] ; (80219e0 ) 8021876: 685b ldr r3, [r3, #4] 8021878: f003 033f and.w r3, r3, #63 ; 0x3f 802187c: 607b str r3, [r7, #4] if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) 802187e: 4b58 ldr r3, [pc, #352] ; (80219e0 ) 8021880: 685b ldr r3, [r3, #4] 8021882: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8021886: 2b00 cmp r3, #0 8021888: d04a beq.n 8021920 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 802188a: 4b55 ldr r3, [pc, #340] ; (80219e0 ) 802188c: 685b ldr r3, [r3, #4] 802188e: 099b lsrs r3, r3, #6 8021890: f04f 0400 mov.w r4, #0 8021894: f240 11ff movw r1, #511 ; 0x1ff 8021898: f04f 0200 mov.w r2, #0 802189c: ea03 0501 and.w r5, r3, r1 80218a0: ea04 0602 and.w r6, r4, r2 80218a4: 4629 mov r1, r5 80218a6: 4632 mov r2, r6 80218a8: f04f 0300 mov.w r3, #0 80218ac: f04f 0400 mov.w r4, #0 80218b0: 0154 lsls r4, r2, #5 80218b2: ea44 64d1 orr.w r4, r4, r1, lsr #27 80218b6: 014b lsls r3, r1, #5 80218b8: 4619 mov r1, r3 80218ba: 4622 mov r2, r4 80218bc: 1b49 subs r1, r1, r5 80218be: eb62 0206 sbc.w r2, r2, r6 80218c2: f04f 0300 mov.w r3, #0 80218c6: f04f 0400 mov.w r4, #0 80218ca: 0194 lsls r4, r2, #6 80218cc: ea44 6491 orr.w r4, r4, r1, lsr #26 80218d0: 018b lsls r3, r1, #6 80218d2: 1a5b subs r3, r3, r1 80218d4: eb64 0402 sbc.w r4, r4, r2 80218d8: f04f 0100 mov.w r1, #0 80218dc: f04f 0200 mov.w r2, #0 80218e0: 00e2 lsls r2, r4, #3 80218e2: ea42 7253 orr.w r2, r2, r3, lsr #29 80218e6: 00d9 lsls r1, r3, #3 80218e8: 460b mov r3, r1 80218ea: 4614 mov r4, r2 80218ec: 195b adds r3, r3, r5 80218ee: eb44 0406 adc.w r4, r4, r6 80218f2: f04f 0100 mov.w r1, #0 80218f6: f04f 0200 mov.w r2, #0 80218fa: 0262 lsls r2, r4, #9 80218fc: ea42 52d3 orr.w r2, r2, r3, lsr #23 8021900: 0259 lsls r1, r3, #9 8021902: 460b mov r3, r1 8021904: 4614 mov r4, r2 8021906: 4618 mov r0, r3 8021908: 4621 mov r1, r4 802190a: 687b ldr r3, [r7, #4] 802190c: f04f 0400 mov.w r4, #0 8021910: 461a mov r2, r3 8021912: 4623 mov r3, r4 8021914: f7fe fc90 bl 8020238 <__aeabi_uldivmod> 8021918: 4603 mov r3, r0 802191a: 460c mov r4, r1 802191c: 60fb str r3, [r7, #12] 802191e: e049 b.n 80219b4 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8021920: 4b2f ldr r3, [pc, #188] ; (80219e0 ) 8021922: 685b ldr r3, [r3, #4] 8021924: 099b lsrs r3, r3, #6 8021926: f04f 0400 mov.w r4, #0 802192a: f240 11ff movw r1, #511 ; 0x1ff 802192e: f04f 0200 mov.w r2, #0 8021932: ea03 0501 and.w r5, r3, r1 8021936: ea04 0602 and.w r6, r4, r2 802193a: 4629 mov r1, r5 802193c: 4632 mov r2, r6 802193e: f04f 0300 mov.w r3, #0 8021942: f04f 0400 mov.w r4, #0 8021946: 0154 lsls r4, r2, #5 8021948: ea44 64d1 orr.w r4, r4, r1, lsr #27 802194c: 014b lsls r3, r1, #5 802194e: 4619 mov r1, r3 8021950: 4622 mov r2, r4 8021952: 1b49 subs r1, r1, r5 8021954: eb62 0206 sbc.w r2, r2, r6 8021958: f04f 0300 mov.w r3, #0 802195c: f04f 0400 mov.w r4, #0 8021960: 0194 lsls r4, r2, #6 8021962: ea44 6491 orr.w r4, r4, r1, lsr #26 8021966: 018b lsls r3, r1, #6 8021968: 1a5b subs r3, r3, r1 802196a: eb64 0402 sbc.w r4, r4, r2 802196e: f04f 0100 mov.w r1, #0 8021972: f04f 0200 mov.w r2, #0 8021976: 00e2 lsls r2, r4, #3 8021978: ea42 7253 orr.w r2, r2, r3, lsr #29 802197c: 00d9 lsls r1, r3, #3 802197e: 460b mov r3, r1 8021980: 4614 mov r4, r2 8021982: 195b adds r3, r3, r5 8021984: eb44 0406 adc.w r4, r4, r6 8021988: f04f 0100 mov.w r1, #0 802198c: f04f 0200 mov.w r2, #0 8021990: 02a2 lsls r2, r4, #10 8021992: ea42 5293 orr.w r2, r2, r3, lsr #22 8021996: 0299 lsls r1, r3, #10 8021998: 460b mov r3, r1 802199a: 4614 mov r4, r2 802199c: 4618 mov r0, r3 802199e: 4621 mov r1, r4 80219a0: 687b ldr r3, [r7, #4] 80219a2: f04f 0400 mov.w r4, #0 80219a6: 461a mov r2, r3 80219a8: 4623 mov r3, r4 80219aa: f7fe fc45 bl 8020238 <__aeabi_uldivmod> 80219ae: 4603 mov r3, r0 80219b0: 460c mov r4, r1 80219b2: 60fb str r3, [r7, #12] } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); 80219b4: 4b0a ldr r3, [pc, #40] ; (80219e0 ) 80219b6: 685b ldr r3, [r3, #4] 80219b8: 0c1b lsrs r3, r3, #16 80219ba: f003 0303 and.w r3, r3, #3 80219be: 3301 adds r3, #1 80219c0: 005b lsls r3, r3, #1 80219c2: 603b str r3, [r7, #0] sysclockfreq = pllvco / pllp; 80219c4: 68fa ldr r2, [r7, #12] 80219c6: 683b ldr r3, [r7, #0] 80219c8: fbb2 f3f3 udiv r3, r2, r3 80219cc: 60bb str r3, [r7, #8] break; 80219ce: e002 b.n 80219d6 } default: { sysclockfreq = HSI_VALUE; 80219d0: 4b04 ldr r3, [pc, #16] ; (80219e4 ) 80219d2: 60bb str r3, [r7, #8] break; 80219d4: bf00 nop } } return sysclockfreq; 80219d6: 68bb ldr r3, [r7, #8] } 80219d8: 4618 mov r0, r3 80219da: 3714 adds r7, #20 80219dc: 46bd mov sp, r7 80219de: bdf0 pop {r4, r5, r6, r7, pc} 80219e0: 40023800 .word 0x40023800 80219e4: 00f42400 .word 0x00f42400 80219e8: 007a1200 .word 0x007a1200 080219ec : * the backup registers) are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80219ec: b580 push {r7, lr} 80219ee: b088 sub sp, #32 80219f0: af00 add r7, sp, #0 80219f2: 6078 str r0, [r7, #4] uint32_t tickstart = 0; 80219f4: 2300 movs r3, #0 80219f6: 617b str r3, [r7, #20] uint32_t tmpreg0 = 0; 80219f8: 2300 movs r3, #0 80219fa: 613b str r3, [r7, #16] uint32_t tmpreg1 = 0; 80219fc: 2300 movs r3, #0 80219fe: 60fb str r3, [r7, #12] uint32_t plli2sused = 0; 8021a00: 2300 movs r3, #0 8021a02: 61fb str r3, [r7, #28] uint32_t pllsaiused = 0; 8021a04: 2300 movs r3, #0 8021a06: 61bb str r3, [r7, #24] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) 8021a08: 687b ldr r3, [r7, #4] 8021a0a: 681b ldr r3, [r3, #0] 8021a0c: f003 0301 and.w r3, r3, #1 8021a10: 2b00 cmp r3, #0 8021a12: d012 beq.n 8021a3a { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 8021a14: 4b69 ldr r3, [pc, #420] ; (8021bbc ) 8021a16: 689b ldr r3, [r3, #8] 8021a18: 4a68 ldr r2, [pc, #416] ; (8021bbc ) 8021a1a: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 8021a1e: 6093 str r3, [r2, #8] 8021a20: 4b66 ldr r3, [pc, #408] ; (8021bbc ) 8021a22: 689a ldr r2, [r3, #8] 8021a24: 687b ldr r3, [r7, #4] 8021a26: 6b5b ldr r3, [r3, #52] ; 0x34 8021a28: 4964 ldr r1, [pc, #400] ; (8021bbc ) 8021a2a: 4313 orrs r3, r2 8021a2c: 608b str r3, [r1, #8] /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) 8021a2e: 687b ldr r3, [r7, #4] 8021a30: 6b5b ldr r3, [r3, #52] ; 0x34 8021a32: 2b00 cmp r3, #0 8021a34: d101 bne.n 8021a3a { plli2sused = 1; 8021a36: 2301 movs r3, #1 8021a38: 61fb str r3, [r7, #28] } } /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 8021a3a: 687b ldr r3, [r7, #4] 8021a3c: 681b ldr r3, [r3, #0] 8021a3e: f403 2300 and.w r3, r3, #524288 ; 0x80000 8021a42: 2b00 cmp r3, #0 8021a44: d017 beq.n 8021a76 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8021a46: 4b5d ldr r3, [pc, #372] ; (8021bbc ) 8021a48: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021a4c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8021a50: 687b ldr r3, [r7, #4] 8021a52: 6bdb ldr r3, [r3, #60] ; 0x3c 8021a54: 4959 ldr r1, [pc, #356] ; (8021bbc ) 8021a56: 4313 orrs r3, r2 8021a58: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 8021a5c: 687b ldr r3, [r7, #4] 8021a5e: 6bdb ldr r3, [r3, #60] ; 0x3c 8021a60: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8021a64: d101 bne.n 8021a6a { plli2sused = 1; 8021a66: 2301 movs r3, #1 8021a68: 61fb str r3, [r7, #28] } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 8021a6a: 687b ldr r3, [r7, #4] 8021a6c: 6bdb ldr r3, [r3, #60] ; 0x3c 8021a6e: 2b00 cmp r3, #0 8021a70: d101 bne.n 8021a76 { pllsaiused = 1; 8021a72: 2301 movs r3, #1 8021a74: 61bb str r3, [r7, #24] } } /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 8021a76: 687b ldr r3, [r7, #4] 8021a78: 681b ldr r3, [r3, #0] 8021a7a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8021a7e: 2b00 cmp r3, #0 8021a80: d017 beq.n 8021ab2 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8021a82: 4b4e ldr r3, [pc, #312] ; (8021bbc ) 8021a84: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021a88: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8021a8c: 687b ldr r3, [r7, #4] 8021a8e: 6c1b ldr r3, [r3, #64] ; 0x40 8021a90: 494a ldr r1, [pc, #296] ; (8021bbc ) 8021a92: 4313 orrs r3, r2 8021a94: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 8021a98: 687b ldr r3, [r7, #4] 8021a9a: 6c1b ldr r3, [r3, #64] ; 0x40 8021a9c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8021aa0: d101 bne.n 8021aa6 { plli2sused = 1; 8021aa2: 2301 movs r3, #1 8021aa4: 61fb str r3, [r7, #28] } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8021aa6: 687b ldr r3, [r7, #4] 8021aa8: 6c1b ldr r3, [r3, #64] ; 0x40 8021aaa: 2b00 cmp r3, #0 8021aac: d101 bne.n 8021ab2 { pllsaiused = 1; 8021aae: 2301 movs r3, #1 8021ab0: 61bb str r3, [r7, #24] } } /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8021ab2: 687b ldr r3, [r7, #4] 8021ab4: 681b ldr r3, [r3, #0] 8021ab6: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8021aba: 2b00 cmp r3, #0 8021abc: d001 beq.n 8021ac2 { plli2sused = 1; 8021abe: 2301 movs r3, #1 8021ac0: 61fb str r3, [r7, #28] } /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8021ac2: 687b ldr r3, [r7, #4] 8021ac4: 681b ldr r3, [r3, #0] 8021ac6: f003 0320 and.w r3, r3, #32 8021aca: 2b00 cmp r3, #0 8021acc: f000 808b beq.w 8021be6 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8021ad0: 4b3a ldr r3, [pc, #232] ; (8021bbc ) 8021ad2: 6c1b ldr r3, [r3, #64] ; 0x40 8021ad4: 4a39 ldr r2, [pc, #228] ; (8021bbc ) 8021ad6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8021ada: 6413 str r3, [r2, #64] ; 0x40 8021adc: 4b37 ldr r3, [pc, #220] ; (8021bbc ) 8021ade: 6c1b ldr r3, [r3, #64] ; 0x40 8021ae0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8021ae4: 60bb str r3, [r7, #8] 8021ae6: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8021ae8: 4b35 ldr r3, [pc, #212] ; (8021bc0 ) 8021aea: 681b ldr r3, [r3, #0] 8021aec: 4a34 ldr r2, [pc, #208] ; (8021bc0 ) 8021aee: f443 7380 orr.w r3, r3, #256 ; 0x100 8021af2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021af4: f7fe ffb6 bl 8020a64 8021af8: 6178 str r0, [r7, #20] /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) 8021afa: e008 b.n 8021b0e { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8021afc: f7fe ffb2 bl 8020a64 8021b00: 4602 mov r2, r0 8021b02: 697b ldr r3, [r7, #20] 8021b04: 1ad3 subs r3, r2, r3 8021b06: 2b64 cmp r3, #100 ; 0x64 8021b08: d901 bls.n 8021b0e { return HAL_TIMEOUT; 8021b0a: 2303 movs r3, #3 8021b0c: e38d b.n 802222a while((PWR->CR1 & PWR_CR1_DBP) == RESET) 8021b0e: 4b2c ldr r3, [pc, #176] ; (8021bc0 ) 8021b10: 681b ldr r3, [r3, #0] 8021b12: f403 7380 and.w r3, r3, #256 ; 0x100 8021b16: 2b00 cmp r3, #0 8021b18: d0f0 beq.n 8021afc } } /* Reset the Backup domain only if the RTC Clock source selection is modified */ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); 8021b1a: 4b28 ldr r3, [pc, #160] ; (8021bbc ) 8021b1c: 6f1b ldr r3, [r3, #112] ; 0x70 8021b1e: f403 7340 and.w r3, r3, #768 ; 0x300 8021b22: 613b str r3, [r7, #16] if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8021b24: 693b ldr r3, [r7, #16] 8021b26: 2b00 cmp r3, #0 8021b28: d035 beq.n 8021b96 8021b2a: 687b ldr r3, [r7, #4] 8021b2c: 6b1b ldr r3, [r3, #48] ; 0x30 8021b2e: f403 7340 and.w r3, r3, #768 ; 0x300 8021b32: 693a ldr r2, [r7, #16] 8021b34: 429a cmp r2, r3 8021b36: d02e beq.n 8021b96 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8021b38: 4b20 ldr r3, [pc, #128] ; (8021bbc ) 8021b3a: 6f1b ldr r3, [r3, #112] ; 0x70 8021b3c: f423 7340 bic.w r3, r3, #768 ; 0x300 8021b40: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8021b42: 4b1e ldr r3, [pc, #120] ; (8021bbc ) 8021b44: 6f1b ldr r3, [r3, #112] ; 0x70 8021b46: 4a1d ldr r2, [pc, #116] ; (8021bbc ) 8021b48: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8021b4c: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 8021b4e: 4b1b ldr r3, [pc, #108] ; (8021bbc ) 8021b50: 6f1b ldr r3, [r3, #112] ; 0x70 8021b52: 4a1a ldr r2, [pc, #104] ; (8021bbc ) 8021b54: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8021b58: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg0; 8021b5a: 4a18 ldr r2, [pc, #96] ; (8021bbc ) 8021b5c: 693b ldr r3, [r7, #16] 8021b5e: 6713 str r3, [r2, #112] ; 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 8021b60: 4b16 ldr r3, [pc, #88] ; (8021bbc ) 8021b62: 6f1b ldr r3, [r3, #112] ; 0x70 8021b64: f003 0301 and.w r3, r3, #1 8021b68: 2b01 cmp r3, #1 8021b6a: d114 bne.n 8021b96 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021b6c: f7fe ff7a bl 8020a64 8021b70: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8021b72: e00a b.n 8021b8a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8021b74: f7fe ff76 bl 8020a64 8021b78: 4602 mov r2, r0 8021b7a: 697b ldr r3, [r7, #20] 8021b7c: 1ad3 subs r3, r2, r3 8021b7e: f241 3288 movw r2, #5000 ; 0x1388 8021b82: 4293 cmp r3, r2 8021b84: d901 bls.n 8021b8a { return HAL_TIMEOUT; 8021b86: 2303 movs r3, #3 8021b88: e34f b.n 802222a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8021b8a: 4b0c ldr r3, [pc, #48] ; (8021bbc ) 8021b8c: 6f1b ldr r3, [r3, #112] ; 0x70 8021b8e: f003 0302 and.w r3, r3, #2 8021b92: 2b00 cmp r3, #0 8021b94: d0ee beq.n 8021b74 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8021b96: 687b ldr r3, [r7, #4] 8021b98: 6b1b ldr r3, [r3, #48] ; 0x30 8021b9a: f403 7340 and.w r3, r3, #768 ; 0x300 8021b9e: f5b3 7f40 cmp.w r3, #768 ; 0x300 8021ba2: d111 bne.n 8021bc8 8021ba4: 4b05 ldr r3, [pc, #20] ; (8021bbc ) 8021ba6: 689b ldr r3, [r3, #8] 8021ba8: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 8021bac: 687b ldr r3, [r7, #4] 8021bae: 6b19 ldr r1, [r3, #48] ; 0x30 8021bb0: 4b04 ldr r3, [pc, #16] ; (8021bc4 ) 8021bb2: 400b ands r3, r1 8021bb4: 4901 ldr r1, [pc, #4] ; (8021bbc ) 8021bb6: 4313 orrs r3, r2 8021bb8: 608b str r3, [r1, #8] 8021bba: e00b b.n 8021bd4 8021bbc: 40023800 .word 0x40023800 8021bc0: 40007000 .word 0x40007000 8021bc4: 0ffffcff .word 0x0ffffcff 8021bc8: 4bb3 ldr r3, [pc, #716] ; (8021e98 ) 8021bca: 689b ldr r3, [r3, #8] 8021bcc: 4ab2 ldr r2, [pc, #712] ; (8021e98 ) 8021bce: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 8021bd2: 6093 str r3, [r2, #8] 8021bd4: 4bb0 ldr r3, [pc, #704] ; (8021e98 ) 8021bd6: 6f1a ldr r2, [r3, #112] ; 0x70 8021bd8: 687b ldr r3, [r7, #4] 8021bda: 6b1b ldr r3, [r3, #48] ; 0x30 8021bdc: f3c3 030b ubfx r3, r3, #0, #12 8021be0: 49ad ldr r1, [pc, #692] ; (8021e98 ) 8021be2: 4313 orrs r3, r2 8021be4: 670b str r3, [r1, #112] ; 0x70 } /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8021be6: 687b ldr r3, [r7, #4] 8021be8: 681b ldr r3, [r3, #0] 8021bea: f003 0310 and.w r3, r3, #16 8021bee: 2b00 cmp r3, #0 8021bf0: d010 beq.n 8021c14 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8021bf2: 4ba9 ldr r3, [pc, #676] ; (8021e98 ) 8021bf4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021bf8: 4aa7 ldr r2, [pc, #668] ; (8021e98 ) 8021bfa: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8021bfe: f8c2 308c str.w r3, [r2, #140] ; 0x8c 8021c02: 4ba5 ldr r3, [pc, #660] ; (8021e98 ) 8021c04: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c 8021c08: 687b ldr r3, [r7, #4] 8021c0a: 6b9b ldr r3, [r3, #56] ; 0x38 8021c0c: 49a2 ldr r1, [pc, #648] ; (8021e98 ) 8021c0e: 4313 orrs r3, r2 8021c10: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8021c14: 687b ldr r3, [r7, #4] 8021c16: 681b ldr r3, [r3, #0] 8021c18: f403 4380 and.w r3, r3, #16384 ; 0x4000 8021c1c: 2b00 cmp r3, #0 8021c1e: d00a beq.n 8021c36 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8021c20: 4b9d ldr r3, [pc, #628] ; (8021e98 ) 8021c22: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021c26: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8021c2a: 687b ldr r3, [r7, #4] 8021c2c: 6e5b ldr r3, [r3, #100] ; 0x64 8021c2e: 499a ldr r1, [pc, #616] ; (8021e98 ) 8021c30: 4313 orrs r3, r2 8021c32: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 8021c36: 687b ldr r3, [r7, #4] 8021c38: 681b ldr r3, [r3, #0] 8021c3a: f403 4300 and.w r3, r3, #32768 ; 0x8000 8021c3e: 2b00 cmp r3, #0 8021c40: d00a beq.n 8021c58 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 8021c42: 4b95 ldr r3, [pc, #596] ; (8021e98 ) 8021c44: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021c48: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 8021c4c: 687b ldr r3, [r7, #4] 8021c4e: 6e9b ldr r3, [r3, #104] ; 0x68 8021c50: 4991 ldr r1, [pc, #580] ; (8021e98 ) 8021c52: 4313 orrs r3, r2 8021c54: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 8021c58: 687b ldr r3, [r7, #4] 8021c5a: 681b ldr r3, [r3, #0] 8021c5c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8021c60: 2b00 cmp r3, #0 8021c62: d00a beq.n 8021c7a { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 8021c64: 4b8c ldr r3, [pc, #560] ; (8021e98 ) 8021c66: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021c6a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8021c6e: 687b ldr r3, [r7, #4] 8021c70: 6edb ldr r3, [r3, #108] ; 0x6c 8021c72: 4989 ldr r1, [pc, #548] ; (8021e98 ) 8021c74: 4313 orrs r3, r2 8021c76: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8021c7a: 687b ldr r3, [r7, #4] 8021c7c: 681b ldr r3, [r3, #0] 8021c7e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8021c82: 2b00 cmp r3, #0 8021c84: d00a beq.n 8021c9c { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8021c86: 4b84 ldr r3, [pc, #528] ; (8021e98 ) 8021c88: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021c8c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8021c90: 687b ldr r3, [r7, #4] 8021c92: 6f1b ldr r3, [r3, #112] ; 0x70 8021c94: 4980 ldr r1, [pc, #512] ; (8021e98 ) 8021c96: 4313 orrs r3, r2 8021c98: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8021c9c: 687b ldr r3, [r7, #4] 8021c9e: 681b ldr r3, [r3, #0] 8021ca0: f003 0340 and.w r3, r3, #64 ; 0x40 8021ca4: 2b00 cmp r3, #0 8021ca6: d00a beq.n 8021cbe { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8021ca8: 4b7b ldr r3, [pc, #492] ; (8021e98 ) 8021caa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021cae: f023 0203 bic.w r2, r3, #3 8021cb2: 687b ldr r3, [r7, #4] 8021cb4: 6c5b ldr r3, [r3, #68] ; 0x44 8021cb6: 4978 ldr r1, [pc, #480] ; (8021e98 ) 8021cb8: 4313 orrs r3, r2 8021cba: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8021cbe: 687b ldr r3, [r7, #4] 8021cc0: 681b ldr r3, [r3, #0] 8021cc2: f003 0380 and.w r3, r3, #128 ; 0x80 8021cc6: 2b00 cmp r3, #0 8021cc8: d00a beq.n 8021ce0 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8021cca: 4b73 ldr r3, [pc, #460] ; (8021e98 ) 8021ccc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021cd0: f023 020c bic.w r2, r3, #12 8021cd4: 687b ldr r3, [r7, #4] 8021cd6: 6c9b ldr r3, [r3, #72] ; 0x48 8021cd8: 496f ldr r1, [pc, #444] ; (8021e98 ) 8021cda: 4313 orrs r3, r2 8021cdc: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 8021ce0: 687b ldr r3, [r7, #4] 8021ce2: 681b ldr r3, [r3, #0] 8021ce4: f403 7380 and.w r3, r3, #256 ; 0x100 8021ce8: 2b00 cmp r3, #0 8021cea: d00a beq.n 8021d02 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 8021cec: 4b6a ldr r3, [pc, #424] ; (8021e98 ) 8021cee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021cf2: f023 0230 bic.w r2, r3, #48 ; 0x30 8021cf6: 687b ldr r3, [r7, #4] 8021cf8: 6cdb ldr r3, [r3, #76] ; 0x4c 8021cfa: 4967 ldr r1, [pc, #412] ; (8021e98 ) 8021cfc: 4313 orrs r3, r2 8021cfe: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8021d02: 687b ldr r3, [r7, #4] 8021d04: 681b ldr r3, [r3, #0] 8021d06: f403 7300 and.w r3, r3, #512 ; 0x200 8021d0a: 2b00 cmp r3, #0 8021d0c: d00a beq.n 8021d24 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 8021d0e: 4b62 ldr r3, [pc, #392] ; (8021e98 ) 8021d10: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021d14: f023 02c0 bic.w r2, r3, #192 ; 0xc0 8021d18: 687b ldr r3, [r7, #4] 8021d1a: 6d1b ldr r3, [r3, #80] ; 0x50 8021d1c: 495e ldr r1, [pc, #376] ; (8021e98 ) 8021d1e: 4313 orrs r3, r2 8021d20: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART5 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 8021d24: 687b ldr r3, [r7, #4] 8021d26: 681b ldr r3, [r3, #0] 8021d28: f403 6380 and.w r3, r3, #1024 ; 0x400 8021d2c: 2b00 cmp r3, #0 8021d2e: d00a beq.n 8021d46 { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 8021d30: 4b59 ldr r3, [pc, #356] ; (8021e98 ) 8021d32: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021d36: f423 7240 bic.w r2, r3, #768 ; 0x300 8021d3a: 687b ldr r3, [r7, #4] 8021d3c: 6d5b ldr r3, [r3, #84] ; 0x54 8021d3e: 4956 ldr r1, [pc, #344] ; (8021e98 ) 8021d40: 4313 orrs r3, r2 8021d42: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART6 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) 8021d46: 687b ldr r3, [r7, #4] 8021d48: 681b ldr r3, [r3, #0] 8021d4a: f403 6300 and.w r3, r3, #2048 ; 0x800 8021d4e: 2b00 cmp r3, #0 8021d50: d00a beq.n 8021d68 { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); 8021d52: 4b51 ldr r3, [pc, #324] ; (8021e98 ) 8021d54: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021d58: f423 6240 bic.w r2, r3, #3072 ; 0xc00 8021d5c: 687b ldr r3, [r7, #4] 8021d5e: 6d9b ldr r3, [r3, #88] ; 0x58 8021d60: 494d ldr r1, [pc, #308] ; (8021e98 ) 8021d62: 4313 orrs r3, r2 8021d64: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART7 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) 8021d68: 687b ldr r3, [r7, #4] 8021d6a: 681b ldr r3, [r3, #0] 8021d6c: f403 5380 and.w r3, r3, #4096 ; 0x1000 8021d70: 2b00 cmp r3, #0 8021d72: d00a beq.n 8021d8a { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); 8021d74: 4b48 ldr r3, [pc, #288] ; (8021e98 ) 8021d76: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021d7a: f423 5240 bic.w r2, r3, #12288 ; 0x3000 8021d7e: 687b ldr r3, [r7, #4] 8021d80: 6ddb ldr r3, [r3, #92] ; 0x5c 8021d82: 4945 ldr r1, [pc, #276] ; (8021e98 ) 8021d84: 4313 orrs r3, r2 8021d86: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART8 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) 8021d8a: 687b ldr r3, [r7, #4] 8021d8c: 681b ldr r3, [r3, #0] 8021d8e: f403 5300 and.w r3, r3, #8192 ; 0x2000 8021d92: 2b00 cmp r3, #0 8021d94: d00a beq.n 8021dac { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); 8021d96: 4b40 ldr r3, [pc, #256] ; (8021e98 ) 8021d98: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021d9c: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8021da0: 687b ldr r3, [r7, #4] 8021da2: 6e1b ldr r3, [r3, #96] ; 0x60 8021da4: 493c ldr r1, [pc, #240] ; (8021e98 ) 8021da6: 4313 orrs r3, r2 8021da8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*--------------------------------------- CEC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 8021dac: 687b ldr r3, [r7, #4] 8021dae: 681b ldr r3, [r3, #0] 8021db0: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8021db4: 2b00 cmp r3, #0 8021db6: d00a beq.n 8021dce { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8021db8: 4b37 ldr r3, [pc, #220] ; (8021e98 ) 8021dba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021dbe: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 8021dc2: 687b ldr r3, [r7, #4] 8021dc4: 6f9b ldr r3, [r3, #120] ; 0x78 8021dc6: 4934 ldr r1, [pc, #208] ; (8021e98 ) 8021dc8: 4313 orrs r3, r2 8021dca: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8021dce: 687b ldr r3, [r7, #4] 8021dd0: 681b ldr r3, [r3, #0] 8021dd2: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8021dd6: 2b00 cmp r3, #0 8021dd8: d011 beq.n 8021dfe { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 8021dda: 4b2f ldr r3, [pc, #188] ; (8021e98 ) 8021ddc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021de0: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 8021de4: 687b ldr r3, [r7, #4] 8021de6: 6fdb ldr r3, [r3, #124] ; 0x7c 8021de8: 492b ldr r1, [pc, #172] ; (8021e98 ) 8021dea: 4313 orrs r3, r2 8021dec: f8c1 3090 str.w r3, [r1, #144] ; 0x90 /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) 8021df0: 687b ldr r3, [r7, #4] 8021df2: 6fdb ldr r3, [r3, #124] ; 0x7c 8021df4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8021df8: d101 bne.n 8021dfe { pllsaiused = 1; 8021dfa: 2301 movs r3, #1 8021dfc: 61bb str r3, [r7, #24] } } /*-------------------------------------- LTDC Configuration -----------------------------------*/ #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8021dfe: 687b ldr r3, [r7, #4] 8021e00: 681b ldr r3, [r3, #0] 8021e02: f003 0308 and.w r3, r3, #8 8021e06: 2b00 cmp r3, #0 8021e08: d001 beq.n 8021e0e { pllsaiused = 1; 8021e0a: 2301 movs r3, #1 8021e0c: 61bb str r3, [r7, #24] } #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8021e0e: 687b ldr r3, [r7, #4] 8021e10: 681b ldr r3, [r3, #0] 8021e12: f403 2380 and.w r3, r3, #262144 ; 0x40000 8021e16: 2b00 cmp r3, #0 8021e18: d00a beq.n 8021e30 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8021e1a: 4b1f ldr r3, [pc, #124] ; (8021e98 ) 8021e1c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021e20: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 8021e24: 687b ldr r3, [r7, #4] 8021e26: 6f5b ldr r3, [r3, #116] ; 0x74 8021e28: 491b ldr r1, [pc, #108] ; (8021e98 ) 8021e2a: 4313 orrs r3, r2 8021e2c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) 8021e30: 687b ldr r3, [r7, #4] 8021e32: 681b ldr r3, [r3, #0] 8021e34: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8021e38: 2b00 cmp r3, #0 8021e3a: d00b beq.n 8021e54 { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); 8021e3c: 4b16 ldr r3, [pc, #88] ; (8021e98 ) 8021e3e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021e42: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 8021e46: 687b ldr r3, [r7, #4] 8021e48: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8021e4c: 4912 ldr r1, [pc, #72] ; (8021e98 ) 8021e4e: 4313 orrs r3, r2 8021e50: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) 8021e54: 687b ldr r3, [r7, #4] 8021e56: 681b ldr r3, [r3, #0] 8021e58: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8021e5c: 2b00 cmp r3, #0 8021e5e: d00b beq.n 8021e78 { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); 8021e60: 4b0d ldr r3, [pc, #52] ; (8021e98 ) 8021e62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8021e66: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 8021e6a: 687b ldr r3, [r7, #4] 8021e6c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021e70: 4909 ldr r1, [pc, #36] ; (8021e98 ) 8021e72: 4313 orrs r3, r2 8021e74: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8021e78: 687b ldr r3, [r7, #4] 8021e7a: 681b ldr r3, [r3, #0] 8021e7c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8021e80: 2b00 cmp r3, #0 8021e82: d00f beq.n 8021ea4 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8021e84: 4b04 ldr r3, [pc, #16] ; (8021e98 ) 8021e86: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021e8a: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 8021e8e: 687b ldr r3, [r7, #4] 8021e90: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8021e94: e002 b.n 8021e9c 8021e96: bf00 nop 8021e98: 40023800 .word 0x40023800 8021e9c: 4985 ldr r1, [pc, #532] ; (80220b4 ) 8021e9e: 4313 orrs r3, r2 8021ea0: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) 8021ea4: 687b ldr r3, [r7, #4] 8021ea6: 681b ldr r3, [r3, #0] 8021ea8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8021eac: 2b00 cmp r3, #0 8021eae: d00b beq.n 8021ec8 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); /* Configure the DFSDM interface clock source */ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); 8021eb0: 4b80 ldr r3, [pc, #512] ; (80220b4 ) 8021eb2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021eb6: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 8021eba: 687b ldr r3, [r7, #4] 8021ebc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021ec0: 497c ldr r1, [pc, #496] ; (80220b4 ) 8021ec2: 4313 orrs r3, r2 8021ec4: f8c1 308c str.w r3, [r1, #140] ; 0x8c } #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8021ec8: 69fb ldr r3, [r7, #28] 8021eca: 2b01 cmp r3, #1 8021ecc: d005 beq.n 8021eda 8021ece: 687b ldr r3, [r7, #4] 8021ed0: 681b ldr r3, [r3, #0] 8021ed2: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8021ed6: f040 80d6 bne.w 8022086 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8021eda: 4b76 ldr r3, [pc, #472] ; (80220b4 ) 8021edc: 681b ldr r3, [r3, #0] 8021ede: 4a75 ldr r2, [pc, #468] ; (80220b4 ) 8021ee0: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8021ee4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8021ee6: f7fe fdbd bl 8020a64 8021eea: 6178 str r0, [r7, #20] /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8021eec: e008 b.n 8021f00 { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8021eee: f7fe fdb9 bl 8020a64 8021ef2: 4602 mov r2, r0 8021ef4: 697b ldr r3, [r7, #20] 8021ef6: 1ad3 subs r3, r2, r3 8021ef8: 2b64 cmp r3, #100 ; 0x64 8021efa: d901 bls.n 8021f00 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8021efc: 2303 movs r3, #3 8021efe: e194 b.n 802222a while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8021f00: 4b6c ldr r3, [pc, #432] ; (80220b4 ) 8021f02: 681b ldr r3, [r3, #0] 8021f04: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8021f08: 2b00 cmp r3, #0 8021f0a: d1f0 bne.n 8021eee /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) 8021f0c: 687b ldr r3, [r7, #4] 8021f0e: 681b ldr r3, [r3, #0] 8021f10: f003 0301 and.w r3, r3, #1 8021f14: 2b00 cmp r3, #0 8021f16: d021 beq.n 8021f5c 8021f18: 687b ldr r3, [r7, #4] 8021f1a: 6b5b ldr r3, [r3, #52] ; 0x34 8021f1c: 2b00 cmp r3, #0 8021f1e: d11d bne.n 8021f5c { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); 8021f20: 4b64 ldr r3, [pc, #400] ; (80220b4 ) 8021f22: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021f26: 0c1b lsrs r3, r3, #16 8021f28: f003 0303 and.w r3, r3, #3 8021f2c: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8021f2e: 4b61 ldr r3, [pc, #388] ; (80220b4 ) 8021f30: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021f34: 0e1b lsrs r3, r3, #24 8021f36: f003 030f and.w r3, r3, #15 8021f3a: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); 8021f3c: 687b ldr r3, [r7, #4] 8021f3e: 685b ldr r3, [r3, #4] 8021f40: 019a lsls r2, r3, #6 8021f42: 693b ldr r3, [r7, #16] 8021f44: 041b lsls r3, r3, #16 8021f46: 431a orrs r2, r3 8021f48: 68fb ldr r3, [r7, #12] 8021f4a: 061b lsls r3, r3, #24 8021f4c: 431a orrs r2, r3 8021f4e: 687b ldr r3, [r7, #4] 8021f50: 689b ldr r3, [r3, #8] 8021f52: 071b lsls r3, r3, #28 8021f54: 4957 ldr r1, [pc, #348] ; (80220b4 ) 8021f56: 4313 orrs r3, r2 8021f58: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8021f5c: 687b ldr r3, [r7, #4] 8021f5e: 681b ldr r3, [r3, #0] 8021f60: f403 2300 and.w r3, r3, #524288 ; 0x80000 8021f64: 2b00 cmp r3, #0 8021f66: d004 beq.n 8021f72 8021f68: 687b ldr r3, [r7, #4] 8021f6a: 6bdb ldr r3, [r3, #60] ; 0x3c 8021f6c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8021f70: d00a beq.n 8021f88 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8021f72: 687b ldr r3, [r7, #4] 8021f74: 681b ldr r3, [r3, #0] 8021f76: f403 1380 and.w r3, r3, #1048576 ; 0x100000 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8021f7a: 2b00 cmp r3, #0 8021f7c: d02e beq.n 8021fdc ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8021f7e: 687b ldr r3, [r7, #4] 8021f80: 6c1b ldr r3, [r3, #64] ; 0x40 8021f82: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8021f86: d129 bne.n 8021fdc assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); 8021f88: 4b4a ldr r3, [pc, #296] ; (80220b4 ) 8021f8a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021f8e: 0c1b lsrs r3, r3, #16 8021f90: f003 0303 and.w r3, r3, #3 8021f94: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8021f96: 4b47 ldr r3, [pc, #284] ; (80220b4 ) 8021f98: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021f9c: 0f1b lsrs r3, r3, #28 8021f9e: f003 0307 and.w r3, r3, #7 8021fa2: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); 8021fa4: 687b ldr r3, [r7, #4] 8021fa6: 685b ldr r3, [r3, #4] 8021fa8: 019a lsls r2, r3, #6 8021faa: 693b ldr r3, [r7, #16] 8021fac: 041b lsls r3, r3, #16 8021fae: 431a orrs r2, r3 8021fb0: 687b ldr r3, [r7, #4] 8021fb2: 68db ldr r3, [r3, #12] 8021fb4: 061b lsls r3, r3, #24 8021fb6: 431a orrs r2, r3 8021fb8: 68fb ldr r3, [r7, #12] 8021fba: 071b lsls r3, r3, #28 8021fbc: 493d ldr r1, [pc, #244] ; (80220b4 ) 8021fbe: 4313 orrs r3, r2 8021fc0: f8c1 3084 str.w r3, [r1, #132] ; 0x84 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8021fc4: 4b3b ldr r3, [pc, #236] ; (80220b4 ) 8021fc6: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8021fca: f023 021f bic.w r2, r3, #31 8021fce: 687b ldr r3, [r7, #4] 8021fd0: 6a5b ldr r3, [r3, #36] ; 0x24 8021fd2: 3b01 subs r3, #1 8021fd4: 4937 ldr r1, [pc, #220] ; (80220b4 ) 8021fd6: 4313 orrs r3, r2 8021fd8: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8021fdc: 687b ldr r3, [r7, #4] 8021fde: 681b ldr r3, [r3, #0] 8021fe0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8021fe4: 2b00 cmp r3, #0 8021fe6: d01d beq.n 8022024 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8021fe8: 4b32 ldr r3, [pc, #200] ; (80220b4 ) 8021fea: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021fee: 0e1b lsrs r3, r3, #24 8021ff0: f003 030f and.w r3, r3, #15 8021ff4: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8021ff6: 4b2f ldr r3, [pc, #188] ; (80220b4 ) 8021ff8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8021ffc: 0f1b lsrs r3, r3, #28 8021ffe: f003 0307 and.w r3, r3, #7 8022002: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); 8022004: 687b ldr r3, [r7, #4] 8022006: 685b ldr r3, [r3, #4] 8022008: 019a lsls r2, r3, #6 802200a: 687b ldr r3, [r7, #4] 802200c: 691b ldr r3, [r3, #16] 802200e: 041b lsls r3, r3, #16 8022010: 431a orrs r2, r3 8022012: 693b ldr r3, [r7, #16] 8022014: 061b lsls r3, r3, #24 8022016: 431a orrs r2, r3 8022018: 68fb ldr r3, [r7, #12] 802201a: 071b lsls r3, r3, #28 802201c: 4925 ldr r1, [pc, #148] ; (80220b4 ) 802201e: 4313 orrs r3, r2 8022020: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8022024: 687b ldr r3, [r7, #4] 8022026: 681b ldr r3, [r3, #0] 8022028: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 802202c: 2b00 cmp r3, #0 802202e: d011 beq.n 8022054 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); 8022030: 687b ldr r3, [r7, #4] 8022032: 685b ldr r3, [r3, #4] 8022034: 019a lsls r2, r3, #6 8022036: 687b ldr r3, [r7, #4] 8022038: 691b ldr r3, [r3, #16] 802203a: 041b lsls r3, r3, #16 802203c: 431a orrs r2, r3 802203e: 687b ldr r3, [r7, #4] 8022040: 68db ldr r3, [r3, #12] 8022042: 061b lsls r3, r3, #24 8022044: 431a orrs r2, r3 8022046: 687b ldr r3, [r7, #4] 8022048: 689b ldr r3, [r3, #8] 802204a: 071b lsls r3, r3, #28 802204c: 4919 ldr r1, [pc, #100] ; (80220b4 ) 802204e: 4313 orrs r3, r2 8022050: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8022054: 4b17 ldr r3, [pc, #92] ; (80220b4 ) 8022056: 681b ldr r3, [r3, #0] 8022058: 4a16 ldr r2, [pc, #88] ; (80220b4 ) 802205a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 802205e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8022060: f7fe fd00 bl 8020a64 8022064: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8022066: e008 b.n 802207a { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8022068: f7fe fcfc bl 8020a64 802206c: 4602 mov r2, r0 802206e: 697b ldr r3, [r7, #20] 8022070: 1ad3 subs r3, r2, r3 8022072: 2b64 cmp r3, #100 ; 0x64 8022074: d901 bls.n 802207a { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8022076: 2303 movs r3, #3 8022078: e0d7 b.n 802222a while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 802207a: 4b0e ldr r3, [pc, #56] ; (80220b4 ) 802207c: 681b ldr r3, [r3, #0] 802207e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8022082: 2b00 cmp r3, #0 8022084: d0f0 beq.n 8022068 } } /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) 8022086: 69bb ldr r3, [r7, #24] 8022088: 2b01 cmp r3, #1 802208a: f040 80cd bne.w 8022228 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 802208e: 4b09 ldr r3, [pc, #36] ; (80220b4 ) 8022090: 681b ldr r3, [r3, #0] 8022092: 4a08 ldr r2, [pc, #32] ; (80220b4 ) 8022094: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8022098: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 802209a: f7fe fce3 bl 8020a64 802209e: 6178 str r0, [r7, #20] /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 80220a0: e00a b.n 80220b8 { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 80220a2: f7fe fcdf bl 8020a64 80220a6: 4602 mov r2, r0 80220a8: 697b ldr r3, [r7, #20] 80220aa: 1ad3 subs r3, r2, r3 80220ac: 2b64 cmp r3, #100 ; 0x64 80220ae: d903 bls.n 80220b8 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80220b0: 2303 movs r3, #3 80220b2: e0ba b.n 802222a 80220b4: 40023800 .word 0x40023800 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 80220b8: 4b5e ldr r3, [pc, #376] ; (8022234 ) 80220ba: 681b ldr r3, [r3, #0] 80220bc: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 80220c0: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80220c4: d0ed beq.n 80220a2 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ 80220c6: 687b ldr r3, [r7, #4] 80220c8: 681b ldr r3, [r3, #0] 80220ca: f403 2300 and.w r3, r3, #524288 ; 0x80000 80220ce: 2b00 cmp r3, #0 80220d0: d003 beq.n 80220da 80220d2: 687b ldr r3, [r7, #4] 80220d4: 6bdb ldr r3, [r3, #60] ; 0x3c 80220d6: 2b00 cmp r3, #0 80220d8: d009 beq.n 80220ee ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 80220da: 687b ldr r3, [r7, #4] 80220dc: 681b ldr r3, [r3, #0] 80220de: f403 1380 and.w r3, r3, #1048576 ; 0x100000 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ 80220e2: 2b00 cmp r3, #0 80220e4: d02e beq.n 8022144 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 80220e6: 687b ldr r3, [r7, #4] 80220e8: 6c1b ldr r3, [r3, #64] ; 0x40 80220ea: 2b00 cmp r3, #0 80220ec: d12a bne.n 8022144 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); 80220ee: 4b51 ldr r3, [pc, #324] ; (8022234 ) 80220f0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80220f4: 0c1b lsrs r3, r3, #16 80220f6: f003 0303 and.w r3, r3, #3 80220fa: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); 80220fc: 4b4d ldr r3, [pc, #308] ; (8022234 ) 80220fe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8022102: 0f1b lsrs r3, r3, #28 8022104: f003 0307 and.w r3, r3, #7 8022108: 60fb str r3, [r7, #12] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); 802210a: 687b ldr r3, [r7, #4] 802210c: 695b ldr r3, [r3, #20] 802210e: 019a lsls r2, r3, #6 8022110: 693b ldr r3, [r7, #16] 8022112: 041b lsls r3, r3, #16 8022114: 431a orrs r2, r3 8022116: 687b ldr r3, [r7, #4] 8022118: 699b ldr r3, [r3, #24] 802211a: 061b lsls r3, r3, #24 802211c: 431a orrs r2, r3 802211e: 68fb ldr r3, [r7, #12] 8022120: 071b lsls r3, r3, #28 8022122: 4944 ldr r1, [pc, #272] ; (8022234 ) 8022124: 4313 orrs r3, r2 8022126: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 802212a: 4b42 ldr r3, [pc, #264] ; (8022234 ) 802212c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8022130: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 8022134: 687b ldr r3, [r7, #4] 8022136: 6a9b ldr r3, [r3, #40] ; 0x28 8022138: 3b01 subs r3, #1 802213a: 021b lsls r3, r3, #8 802213c: 493d ldr r1, [pc, #244] ; (8022234 ) 802213e: 4313 orrs r3, r2 8022140: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) 8022144: 687b ldr r3, [r7, #4] 8022146: 681b ldr r3, [r3, #0] 8022148: f403 1300 and.w r3, r3, #2097152 ; 0x200000 802214c: 2b00 cmp r3, #0 802214e: d022 beq.n 8022196 8022150: 687b ldr r3, [r7, #4] 8022152: 6fdb ldr r3, [r3, #124] ; 0x7c 8022154: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8022158: d11d bne.n 8022196 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 802215a: 4b36 ldr r3, [pc, #216] ; (8022234 ) 802215c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8022160: 0e1b lsrs r3, r3, #24 8022162: f003 030f and.w r3, r3, #15 8022166: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); 8022168: 4b32 ldr r3, [pc, #200] ; (8022234 ) 802216a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 802216e: 0f1b lsrs r3, r3, #28 8022170: f003 0307 and.w r3, r3, #7 8022174: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); 8022176: 687b ldr r3, [r7, #4] 8022178: 695b ldr r3, [r3, #20] 802217a: 019a lsls r2, r3, #6 802217c: 687b ldr r3, [r7, #4] 802217e: 6a1b ldr r3, [r3, #32] 8022180: 041b lsls r3, r3, #16 8022182: 431a orrs r2, r3 8022184: 693b ldr r3, [r7, #16] 8022186: 061b lsls r3, r3, #24 8022188: 431a orrs r2, r3 802218a: 68fb ldr r3, [r7, #12] 802218c: 071b lsls r3, r3, #28 802218e: 4929 ldr r1, [pc, #164] ; (8022234 ) 8022190: 4313 orrs r3, r2 8022192: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) 8022196: 687b ldr r3, [r7, #4] 8022198: 681b ldr r3, [r3, #0] 802219a: f003 0308 and.w r3, r3, #8 802219e: 2b00 cmp r3, #0 80221a0: d028 beq.n 80221f4 { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 80221a2: 4b24 ldr r3, [pc, #144] ; (8022234 ) 80221a4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80221a8: 0e1b lsrs r3, r3, #24 80221aa: f003 030f and.w r3, r3, #15 80221ae: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); 80221b0: 4b20 ldr r3, [pc, #128] ; (8022234 ) 80221b2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80221b6: 0c1b lsrs r3, r3, #16 80221b8: f003 0303 and.w r3, r3, #3 80221bc: 60fb str r3, [r7, #12] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); 80221be: 687b ldr r3, [r7, #4] 80221c0: 695b ldr r3, [r3, #20] 80221c2: 019a lsls r2, r3, #6 80221c4: 68fb ldr r3, [r7, #12] 80221c6: 041b lsls r3, r3, #16 80221c8: 431a orrs r2, r3 80221ca: 693b ldr r3, [r7, #16] 80221cc: 061b lsls r3, r3, #24 80221ce: 431a orrs r2, r3 80221d0: 687b ldr r3, [r7, #4] 80221d2: 69db ldr r3, [r3, #28] 80221d4: 071b lsls r3, r3, #28 80221d6: 4917 ldr r1, [pc, #92] ; (8022234 ) 80221d8: 4313 orrs r3, r2 80221da: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); 80221de: 4b15 ldr r3, [pc, #84] ; (8022234 ) 80221e0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80221e4: f423 3240 bic.w r2, r3, #196608 ; 0x30000 80221e8: 687b ldr r3, [r7, #4] 80221ea: 6adb ldr r3, [r3, #44] ; 0x2c 80221ec: 4911 ldr r1, [pc, #68] ; (8022234 ) 80221ee: 4313 orrs r3, r2 80221f0: f8c1 308c str.w r3, [r1, #140] ; 0x8c } #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 80221f4: 4b0f ldr r3, [pc, #60] ; (8022234 ) 80221f6: 681b ldr r3, [r3, #0] 80221f8: 4a0e ldr r2, [pc, #56] ; (8022234 ) 80221fa: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80221fe: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8022200: f7fe fc30 bl 8020a64 8022204: 6178 str r0, [r7, #20] /* Wait till PLLSAI is ready */ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8022206: e008 b.n 802221a { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8022208: f7fe fc2c bl 8020a64 802220c: 4602 mov r2, r0 802220e: 697b ldr r3, [r7, #20] 8022210: 1ad3 subs r3, r2, r3 8022212: 2b64 cmp r3, #100 ; 0x64 8022214: d901 bls.n 802221a { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8022216: 2303 movs r3, #3 8022218: e007 b.n 802222a while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 802221a: 4b06 ldr r3, [pc, #24] ; (8022234 ) 802221c: 681b ldr r3, [r3, #0] 802221e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8022222: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8022226: d1ef bne.n 8022208 } } } return HAL_OK; 8022228: 2300 movs r3, #0 } 802222a: 4618 mov r0, r3 802222c: 3720 adds r7, #32 802222e: 46bd mov sp, r7 8022230: bd80 pop {r7, pc} 8022232: bf00 nop 8022234: 40023800 .word 0x40023800 08022238 <__libc_init_array>: 8022238: b570 push {r4, r5, r6, lr} 802223a: 4e0d ldr r6, [pc, #52] ; (8022270 <__libc_init_array+0x38>) 802223c: 4c0d ldr r4, [pc, #52] ; (8022274 <__libc_init_array+0x3c>) 802223e: 1ba4 subs r4, r4, r6 8022240: 10a4 asrs r4, r4, #2 8022242: 2500 movs r5, #0 8022244: 42a5 cmp r5, r4 8022246: d109 bne.n 802225c <__libc_init_array+0x24> 8022248: 4e0b ldr r6, [pc, #44] ; (8022278 <__libc_init_array+0x40>) 802224a: 4c0c ldr r4, [pc, #48] ; (802227c <__libc_init_array+0x44>) 802224c: f000 f820 bl 8022290 <_init> 8022250: 1ba4 subs r4, r4, r6 8022252: 10a4 asrs r4, r4, #2 8022254: 2500 movs r5, #0 8022256: 42a5 cmp r5, r4 8022258: d105 bne.n 8022266 <__libc_init_array+0x2e> 802225a: bd70 pop {r4, r5, r6, pc} 802225c: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8022260: 4798 blx r3 8022262: 3501 adds r5, #1 8022264: e7ee b.n 8022244 <__libc_init_array+0xc> 8022266: f856 3025 ldr.w r3, [r6, r5, lsl #2] 802226a: 4798 blx r3 802226c: 3501 adds r5, #1 802226e: e7f2 b.n 8022256 <__libc_init_array+0x1e> 8022270: 080222c0 .word 0x080222c0 8022274: 080222c0 .word 0x080222c0 8022278: 080222c0 .word 0x080222c0 802227c: 080222c4 .word 0x080222c4 08022280 : 8022280: 4402 add r2, r0 8022282: 4603 mov r3, r0 8022284: 4293 cmp r3, r2 8022286: d100 bne.n 802228a 8022288: 4770 bx lr 802228a: f803 1b01 strb.w r1, [r3], #1 802228e: e7f9 b.n 8022284 08022290 <_init>: 8022290: b5f8 push {r3, r4, r5, r6, r7, lr} 8022292: bf00 nop 8022294: bcf8 pop {r3, r4, r5, r6, r7} 8022296: bc08 pop {r3} 8022298: 469e mov lr, r3 802229a: 4770 bx lr 0802229c <_fini>: 802229c: b5f8 push {r3, r4, r5, r6, r7, lr} 802229e: bf00 nop 80222a0: bcf8 pop {r3, r4, r5, r6, r7} 80222a2: bc08 pop {r3} 80222a4: 469e mov lr, r3 80222a6: 4770 bx lr