/** ****************************************************************************** * @file OSPI/OSPI_RAM_ReadWrite_DMA/Inc/main.h * @author MCD Application Team * @brief Header for main.c module ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MAIN_H #define __MAIN_H /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #include "stm32l4p5g_discovery.h" /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ #define DUMMY_CLOCK_CYCLES_READ 8 #define DUMMY_CLOCK_CYCLES_READ_QUAD 6 /* OSPI pins definition */ #define OSPI_P1_CS_PIN GPIO_PIN_11 #define OSPI_P1_CLK_PIN GPIO_PIN_10 #define OSPI_P1_NCLK_PIN GPIO_PIN_9 #define OSPI_P1_D0_PIN GPIO_PIN_12 #define OSPI_P1_D1_PIN GPIO_PIN_13 #define OSPI_P1_D2_PIN GPIO_PIN_7 #define OSPI_P1_D3_PIN GPIO_PIN_6 #define OSPI_P1_D4_PIN GPIO_PIN_4 #define OSPI_P1_D5_PIN GPIO_PIN_5 #define OSPI_P1_D6_PIN GPIO_PIN_3 #define OSPI_P1_D7_PIN GPIO_PIN_7 #define OSPI_P1_DQS_PIN GPIO_PIN_6 #define OSPI_P2_CS_PIN GPIO_PIN_12 #define OSPI_P2_CLK_PIN GPIO_PIN_4 #define OSPI_P2_NCLK_PIN GPIO_PIN_5 #define OSPI_P2_D0_PIN GPIO_PIN_0 #define OSPI_P2_D1_PIN GPIO_PIN_1 #define OSPI_P2_D2_PIN GPIO_PIN_2 #define OSPI_P2_D3_PIN GPIO_PIN_3 #define OSPI_P2_D4_PIN GPIO_PIN_0 #define OSPI_P2_D5_PIN GPIO_PIN_1 #define OSPI_P2_D6_PIN GPIO_PIN_9 #define OSPI_P2_D7_PIN GPIO_PIN_10 #define OSPI_P2_DQS_PIN GPIO_PIN_12 #define OSPI_P1_CS_GPIO_PORT GPIOE #define OSPI_P1_CLK_GPIO_PORT GPIOE #define OSPI_P1_NCLK_GPIO_PORT GPIOE #define OSPI_P1_D0_GPIO_PORT GPIOE #define OSPI_P1_D1_GPIO_PORT GPIOE #define OSPI_P1_D2_GPIO_PORT GPIOA #define OSPI_P1_D3_GPIO_PORT GPIOA #define OSPI_P1_D4_GPIO_PORT GPIOD #define OSPI_P1_D5_GPIO_PORT GPIOD #define OSPI_P1_D6_GPIO_PORT GPIOC #define OSPI_P1_D7_GPIO_PORT GPIOD #define OSPI_P1_DQS_GPIO_PORT GPIOG #define OSPI_P2_CS_GPIO_PORT GPIOG #define OSPI_P2_CLK_GPIO_PORT GPIOF #define OSPI_P2_NCLK_GPIO_PORT GPIOF #define OSPI_P2_D0_GPIO_PORT GPIOF #define OSPI_P2_D1_GPIO_PORT GPIOF #define OSPI_P2_D2_GPIO_PORT GPIOF #define OSPI_P2_D3_GPIO_PORT GPIOF #define OSPI_P2_D4_GPIO_PORT GPIOG #define OSPI_P2_D5_GPIO_PORT GPIOG #define OSPI_P2_D6_GPIO_PORT GPIOG #define OSPI_P2_D7_GPIO_PORT GPIOG #define OSPI_P2_DQS_GPIO_PORT GPIOF /* End address of the OSPI memory */ #define OSPI_PSRAM_END_ADDR (1 << OSPI_PSRAM_SIZE) /* Size of buffers */ #define BUFFERSIZE (COUNTOF(aTxBuffer) - 1) /* Exported macro ------------------------------------------------------------*/ #define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__))) /* Definition for OSPI clock resources */ #define OSPI_P1_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() #define OSPI_P1_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() #define OSPI_P1_NCLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() #define OSPI_P1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() #define OSPI_P1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() #define OSPI_P1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define OSPI_P1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define OSPI_P1_D4_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define OSPI_P1_D5_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define OSPI_P1_D6_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define OSPI_P1_D7_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define OSPI_P1_DQS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define OSPI_P2_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define OSPI_P2_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P2_NCLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P2_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P2_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P2_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P2_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P2_D4_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define OSPI_P2_D5_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define OSPI_P2_D6_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define OSPI_P2_D7_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define OSPI_P2_DQS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define OSPI_P1_CS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() #define OSPI_P1_CLK_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() #define OSPI_P1_NCLK_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() #define OSPI_P1_D0_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() #define OSPI_P1_D1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() #define OSPI_P1_D2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() #define OSPI_P1_D3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() #define OSPI_P1_D4_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() #define OSPI_P1_D5_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() #define OSPI_P1_D6_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() #define OSPI_P1_D7_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() #define OSPI_P1_DQS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() #define OSPI_P2_CS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() #define OSPI_P2_CLK_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() #define OSPI_P2_NCLK_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() #define OSPI_P2_D0_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() #define OSPI_P2_D1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() #define OSPI_P2_D2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() #define OSPI_P2_D3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() #define OSPI_P2_D4_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() #define OSPI_P2_D5_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() #define OSPI_P2_D6_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() #define OSPI_P2_D7_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() #define OSPI_P2_DQS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() /* USER CODE END ET */ #define FAST_READ_QUAD 0xEB #define QUAD_WRITE 0x38 #define ENTER_QUAD_MODE 0x35 #define EXIT_QUAD_MODE 0xF5 /* Exported functions ------------------------------------------------------- */ #define BUFFERSIZE (COUNTOF(aTxBuffer) - 1) #define EXTENDEDBUFFERSIZE (10240) /* Exported macro ------------------------------------------------------------*/ #define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__))) #endif /* __MAIN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/