#define DEFAULT_SEED UINT32_MAX static uint32_t software_crc32_calculate_with_seed(void const * const p_data, size_t length, uint32_t seed) { static const uint32_t crc32_table[256u] = { 0x00000000u, 0x77073096u, 0xEE0E612Cu, 0x990951BAu, 0x076DC419u, 0x706AF48Fu, 0xE963A535u, 0x9E6495A3u, 0x0EDB8832u, 0x79DCB8A4u, 0xE0D5E91Eu, 0x97D2D988u, 0x09B64C2Bu, 0x7EB17CBDu, 0xE7B82D07u, 0x90BF1D91u, 0x1DB71064u, 0x6AB020F2u, 0xF3B97148u, 0x84BE41DEu, 0x1ADAD47Du, 0x6DDDE4EBu, 0xF4D4B551u, 0x83D385C7u, 0x136C9856u, 0x646BA8C0u, 0xFD62F97Au, 0x8A65C9ECu, 0x14015C4Fu, 0x63066CD9u, 0xFA0F3D63u, 0x8D080DF5u, 0x3B6E20C8u, 0x4C69105Eu, 0xD56041E4u, 0xA2677172u, 0x3C03E4D1u, 0x4B04D447u, 0xD20D85FDu, 0xA50AB56Bu, 0x35B5A8FAu, 0x42B2986Cu, 0xDBBBC9D6u, 0xACBCF940u, 0x32D86CE3u, 0x45DF5C75u, 0xDCD60DCFu, 0xABD13D59u, 0x26D930ACu, 0x51DE003Au, 0xC8D75180u, 0xBFD06116u, 0x21B4F4B5u, 0x56B3C423u, 0xCFBA9599u, 0xB8BDA50Fu, 0x2802B89Eu, 0x5F058808u, 0xC60CD9B2u, 0xB10BE924u, 0x2F6F7C87u, 0x58684C11u, 0xC1611DABu, 0xB6662D3Du, 0x76DC4190u, 0x01DB7106u, 0x98D220BCu, 0xEFD5102Au, 0x71B18589u, 0x06B6B51Fu, 0x9FBFE4A5u, 0xE8B8D433u, 0x7807C9A2u, 0x0F00F934u, 0x9609A88Eu, 0xE10E9818u, 0x7F6A0DBBu, 0x086D3D2Du, 0x91646C97u, 0xE6635C01u, 0x6B6B51F4u, 0x1C6C6162u, 0x856530D8u, 0xF262004Eu, 0x6C0695EDu, 0x1B01A57Bu, 0x8208F4C1u, 0xF50FC457u, 0x65B0D9C6u, 0x12B7E950u, 0x8BBEB8EAu, 0xFCB9887Cu, 0x62DD1DDFu, 0x15DA2D49u, 0x8CD37CF3u, 0xFBD44C65u, 0x4DB26158u, 0x3AB551CEu, 0xA3BC0074u, 0xD4BB30E2u, 0x4ADFA541u, 0x3DD895D7u, 0xA4D1C46Du, 0xD3D6F4FBu, 0x4369E96Au, 0x346ED9FCu, 0xAD678846u, 0xDA60B8D0u, 0x44042D73u, 0x33031DE5u, 0xAA0A4C5Fu, 0xDD0D7CC9u, 0x5005713Cu, 0x270241AAu, 0xBE0B1010u, 0xC90C2086u, 0x5768B525u, 0x206F85B3u, 0xB966D409u, 0xCE61E49Fu, 0x5EDEF90Eu, 0x29D9C998u, 0xB0D09822u, 0xC7D7A8B4u, 0x59B33D17u, 0x2EB40D81u, 0xB7BD5C3Bu, 0xC0BA6CADu, 0xEDB88320u, 0x9ABFB3B6u, 0x03B6E20Cu, 0x74B1D29Au, 0xEAD54739u, 0x9DD277AFu, 0x04DB2615u, 0x73DC1683u, 0xE3630B12u, 0x94643B84u, 0x0D6D6A3Eu, 0x7A6A5AA8u, 0xE40ECF0Bu, 0x9309FF9Du, 0x0A00AE27u, 0x7D079EB1u, 0xF00F9344u, 0x8708A3D2u, 0x1E01F268u, 0x6906C2FEu, 0xF762575Du, 0x806567CBu, 0x196C3671u, 0x6E6B06E7u, 0xFED41B76u, 0x89D32BE0u, 0x10DA7A5Au, 0x67DD4ACCu, 0xF9B9DF6Fu, 0x8EBEEFF9u, 0x17B7BE43u, 0x60B08ED5u, 0xD6D6A3E8u, 0xA1D1937Eu, 0x38D8C2C4u, 0x4FDFF252u, 0xD1BB67F1u, 0xA6BC5767u, 0x3FB506DDu, 0x48B2364Bu, 0xD80D2BDAu, 0xAF0A1B4Cu, 0x36034AF6u, 0x41047A60u, 0xDF60EFC3u, 0xA867DF55u, 0x316E8EEFu, 0x4669BE79u, 0xCB61B38Cu, 0xBC66831Au, 0x256FD2A0u, 0x5268E236u, 0xCC0C7795u, 0xBB0B4703u, 0x220216B9u, 0x5505262Fu, 0xC5BA3BBEu, 0xB2BD0B28u, 0x2BB45A92u, 0x5CB36A04u, 0xC2D7FFA7u, 0xB5D0CF31u, 0x2CD99E8Bu, 0x5BDEAE1Du, 0x9B64C2B0u, 0xEC63F226u, 0x756AA39Cu, 0x026D930Au, 0x9C0906A9u, 0xEB0E363Fu, 0x72076785u, 0x05005713u, 0x95BF4A82u, 0xE2B87A14u, 0x7BB12BAEu, 0x0CB61B38u, 0x92D28E9Bu, 0xE5D5BE0Du, 0x7CDCEFB7u, 0x0BDBDF21u, 0x86D3D2D4u, 0xF1D4E242u, 0x68DDB3F8u, 0x1FDA836Eu, 0x81BE16CDu, 0xF6B9265Bu, 0x6FB077E1u, 0x18B74777u, 0x88085AE6u, 0xFF0F6A70u, 0x66063BCAu, 0x11010B5Cu, 0x8F659EFFu, 0xF862AE69u, 0x616BFFD3u, 0x166CCF45u, 0xA00AE278u, 0xD70DD2EEu, 0x4E048354u, 0x3903B3C2u, 0xA7672661u, 0xD06016F7u, 0x4969474Du, 0x3E6E77DBu, 0xAED16A4Au, 0xD9D65ADCu, 0x40DF0B66u, 0x37D83BF0u, 0xA9BCAE53u, 0xDEBB9EC5u, 0x47B2CF7Fu, 0x30B5FFE9u, 0xBDBDF21Cu, 0xCABAC28Au, 0x53B39330u, 0x24B4A3A6u, 0xBAD03605u, 0xCDD70693u, 0x54DE5729u, 0x23D967BFu, 0xB3667A2Eu, 0xC4614AB8u, 0x5D681B02u, 0x2A6F2B94u, 0xB40BBE37u, 0xC30C8EA1u, 0x5A05DF1Bu, 0x2D02EF8Du, }; const uint8_t * p_byte = (const uint8_t *)p_data; size_t bytes_remaining = length; uint32_t crc_remainder = seed; while (bytes_remaining != 0u) { crc_remainder = crc32_table[(crc_remainder ^ *p_byte) & 0xFFu] ^ (crc_remainder >> 8u); p_byte++; bytes_remaining--; } return crc_remainder; } #if defined(VT20X) CRC_HandleTypeDef hcrc1; static void crc_init() { __HAL_RCC_CRC_CLK_ENABLE(); hcrc1.Instance = CRC; hcrc1.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; hcrc1.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; hcrc1.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE; hcrc1.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_ENABLE; hcrc1.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; if(HAL_CRC_Init(&hcrc1)) { LOG_ERROR("Cannot initialize the CRC!"); osDelay(20); } } /**The seed must be 0xFFFFFFFF**/ static uint32_t hardware_crc_caculate_with_seed_u5(const void* const pdata, uint32_t len, uint32_t seed) { (void)seed; //uint32_t word_len = len/sizeof(uint32_t); //uint8_t byte_left = len%sizeof(uint32_t); uint32_t crc_result; crc_result = HAL_CRC_Calculate(&hcrc1,(uint32_t*)pdata, len); return crc_result; } #endif #if defined (L4) #define STM32L4A6_PERIPH_BASE (0x40000000UL) // Peripheral base address. #define STM32L4A6_AHB1PERIPH_BASE (STM32L4A6_PERIPH_BASE + 0x00020000UL) // AHB1PERIPH register base address. #define STM32L4A6_CRC_BASE (STM32L4A6_AHB1PERIPH_BASE + 0x3000UL) // CRC peripheral base. #define STM32L4A6_RCC_BASE (STM32L4A6_AHB1PERIPH_BASE + 0x1000UL) // RCC peripheral base. #define STM32L4A6_AHB1ENR_BASE (STM32L4A6_RCC_BASE + 0x48UL) // AHB1ENR register base address. #define STM32L4A6_RCC_AHB1ENR_CRCEN_BIT (0x1UL << 12u) // Bit to enable CRC peripheral clock. #else #define STM32L4A6_PERIPH_BASE (0x40000000UL) // Peripheral base address. #define STM32L4A6_AHB1PERIPH_BASE (STM32L4A6_PERIPH_BASE + 0x00020000UL) // AHB1PERIPH register base address. #define STM32L4A6_AHB3PERIPH_BASE (STM32L4A6_PERIPH_BASE + 0x06020000UL) // AHB1PERIPH register base address. #define STM32L4A6_CRC_BASE (STM32L4A6_AHB1PERIPH_BASE + 0x3000UL) // CRC peripheral base. #define STM32L4A6_RCC_BASE (STM32L4A6_AHB3PERIPH_BASE + 0x0C00UL) // RCC peripheral base. #define STM32L4A6_AHB1ENR_BASE (STM32L4A6_RCC_BASE + 0x88UL) // AHB1ENR register base address. #define STM32L4A6_RCC_AHB1ENR_CRCEN_BIT (0x1UL << 12u) // Bit to enable CRC peripheral clock. #endif // STM32L4A6 hardware CRC register configurations: // Set these bits to reset the CRC peripheral: #define STM32L4A6_HARDWARE_CRC_CONTROL_RESET_BITS_TO_SET (0x1UL) // Set these bits to reverse the input data: #define STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_BYTE_BITS_TO_SET (0x1UL << 5u) // Set these bits to reverse the input data as word: #define STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_WORD_BITS_TO_SET (0x3UL << 5u) // Set these bits to reverse the output data: #define STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_OUTPUT_BITS_TO_SET (0x1UL << 7u) // Clear these bits to configure the CRC peripheral to use a 32bit polynomial: #define STM32L4A6_HARDWARE_CRC_CONTROL_32BIT_POLYNOMIAL_BITS_TO_CLEAR (~(0x3UL << 3u)) // The default CRC32 polynomial: #define STM32L4A6_HARDWARE_CRC_DEFAULT_POLYNOMIAL (0x04C11DB7u) #define UNUSED_REGISTER(reg) ((void)(reg)) typedef struct { volatile uint32_t DR; // CRC Data register, Address offset: 0x00 volatile uint8_t IDR; // CRC Independent data register, Address offset: 0x04 uint8_t RESERVED0; // Reserved, Address offset: 0x05 uint8_t RESERVED1[2]; // Reserved, Address offset: 0x06 volatile uint32_t CR; // CRC Control register, Address offset: 0x08 uint32_t RESERVED2; // Reserved, Address offset: 0x0C volatile uint32_t INIT; // Initial CRC value register, Address offset: 0x10 volatile uint32_t POL; // CRC polynomial register, Address offset: 0x14 } hardware_crc_t; //lint -e{9078} "suppress conversion between pointer and integer type. To access the hardware registers" static hardware_crc_t * const p_hardware_crc = (hardware_crc_t *)STM32L4A6_CRC_BASE; //lint -e{9078} "suppress conversion between pointer and integer type. To access the hardware registers" static uint32_t * const p_ahb1enr_register = (uint32_t *)STM32L4A6_AHB1ENR_BASE; void hardware_crc32_initialise(void) { // Configure the CRC peripheral: // 1: Enable the CRC peripheral clock. *p_ahb1enr_register |= STM32L4A6_RCC_AHB1ENR_CRCEN_BIT; // 2: Configure the CRC polynomial as 32 bits wide. p_hardware_crc->CR &= STM32L4A6_HARDWARE_CRC_CONTROL_32BIT_POLYNOMIAL_BITS_TO_CLEAR; // 3: Configure the CRC module to reverse the output value. p_hardware_crc->CR |= STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_OUTPUT_BITS_TO_SET; // 4: Configure the CRC module to reverse the input value. p_hardware_crc->CR |= STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_WORD_BITS_TO_SET; //p_hardware_crc->CR |= STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_BYTE_BITS_TO_SET; // 5: Set the CRC polynomial register to the default CRC polynomial. p_hardware_crc->POL = STM32L4A6_HARDWARE_CRC_DEFAULT_POLYNOMIAL; // Unused registers: UNUSED_REGISTER(p_hardware_crc->IDR); UNUSED_REGISTER(p_hardware_crc->RESERVED0); UNUSED_REGISTER(p_hardware_crc->RESERVED1); UNUSED_REGISTER(p_hardware_crc->RESERVED2); } uint32_t hardware_crc32_calculate_with_seed(uint8_t p_data[], size_t length, uint32_t seed) { // 1: Set the seed. p_hardware_crc->INIT = seed; // 2: Reset CRC module, it loads the seed. //p_hardware_crc->CR |= STM32L4A6_HARDWARE_CRC_CONTROL_RESET_BITS_TO_SET; // 3: Check if the data can be processed as uint32_t; as 4 byte chunks. size_t i; for (i = 0u; i < (length / sizeof (uint32_t)); i++) { // Load the data 4 bytes at a time. p_hardware_crc->DR = ((uint32_t const * const)p_data)[i]; /* p_hardware_crc->DR = (uint32_t)((uint8_t const * const)p_data)[sizeof (uint32_t) * i] << 24 | \ (uint32_t)((uint8_t const * const)p_data)[(sizeof (uint32_t) * i) + 1] << 16 | \ (uint32_t)((uint8_t const * const)p_data)[(sizeof (uint32_t) * i) + 2] << 8 | \ (uint32_t)((uint8_t const * const)p_data)[(sizeof (uint32_t) * i) + 3]; */ } // 4: Check if any bytes left to process. const uint8_t bytes_left = length % sizeof (uint32_t); if (bytes_left != 0U) { p_hardware_crc->CR &= ~STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_WORD_BITS_TO_SET; p_hardware_crc->CR |= STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_BYTE_BITS_TO_SET; for (size_t j = 0U; j < bytes_left; j++) { // Need to load the data as one byte at a time, // Note that the last bytes must be carefully fed to the CRC calculator to ensure a // correct type handling by the peripheral. *((volatile uint8_t *)&p_hardware_crc->DR) = ((uint8_t const * const)p_data)[(sizeof (uint32_t) * i) + j]; } p_hardware_crc->CR |= STM32L4A6_HARDWARE_CRC_CONTROL_REVERSE_INPUT_WORD_BITS_TO_SET; } return p_hardware_crc->DR; } uint8_t tn_crc_check_test(void) { uint8_t test_data_4_times_bytes[] = {0x01, 0x02,0x03,0x04,5,6,7,8, 9, 10}; uint32_t crc_software_result = 0; uint32_t crc_hardware_result = 0; //for(int i = 3; i >= 0; i--) { //LOG_NOTICE("Now doing crc with byte*4 with %d extra bytes\n", i ); #if defined(L4) #else uint32_t crc_hardware_result_u5 = 0; #endif crc_software_result = software_crc32_calculate_with_seed(test_data_4_times_bytes, sizeof(test_data_4_times_bytes) , DEFAULT_SEED); LOG_NOTICE("the crc value from software calculation is %x", crc_software_result); osDelay(20); LOG_NOTICE("Start to initialize the CRC hardware L4 code.."); osDelay(20); hardware_crc32_initialise(); crc_hardware_result = hardware_crc32_calculate_with_seed(test_data_4_times_bytes, sizeof(test_data_4_times_bytes) , DEFAULT_SEED); LOG_NOTICE("The l4 code crc hardware result on the u5 board is %x", crc_hardware_result); osDelay(20); #if defined(L4) #else crc_init(); crc_hardware_result_u5 = hardware_crc_caculate_with_seed_u5(test_data_4_times_bytes, sizeof(test_data_4_times_bytes) , DEFAULT_SEED); LOG_NOTICE("The crc hardware u5 HAL code result is %x", crc_hardware_result_u5); osDelay(20); #endif if(crc_hardware_result != crc_software_result) { LOG_ERROR("CRC test is failed!!"); osDelay(20); return RES_ERROR; } } return RES_OK; }