/* * final_application.c * * Created on: 19-May-2023 * Author: D Raj */ /* * Pre-Processor Directives */ //#define new_protocol //#define shashwat_test #define i2c_state /* * Macro Definitions */ // I2C Power supply slave addresses #define SET 1 #define CLEAR 0 #define PS24_ADDR 0x07 // Power Supply 1 #define PS48_1_ADDR 0x02 // Power Supply 2 #define PS48_2_ADDR 0x03 // Power Supply 3 #define PRESS_1_SEC 1000 // long press of 1 sec for ACK, resume and homing button based on 1ms timer #define IP_CHECK_8 1 // Check MUX input at 8 ms, based on 8ms timer #define IP_CHECK_16 2 // Check MUX input at 16 ms, based on 8ms timer #define TRANSMIT_INTERVAL 125 // 125*8 = 1000ms ,based on 8ms timer #define PS_READ_TIME 26 // 13*8 = 104ms, based on 8ms timer #define PS_TRANS_TIME 37500 // 625*8 = 5000ms, based on 8ms timer #define IPC_TURN_OFF_TIME 375 // 375*8 = 3000ms, based on 8ms timer for IPC OFF #define IPC_TURN_ON_TIME 125 // 125*8 = 1000ms, based on 8ms timer for IPC ON #define PS_STABLE 1000 // 1000*1 = 1000ms, based on 1ms timer for PS_stable time #define RECV_TIMEOUT 4000 // 1000*4 = 4000ms, based on 1ms timer // Power Supply Internal Register Addresses #define PMB_READ_VOUT_ADDR 0x8B #define PMB_READ_IOUT_ADDR 0x8C #define PMB_READ_POUT_ADDR 0x96 #define PMB_MFR_AUX_VOUT_ADDR 0xC4 #define PMB_MFR_AUX_IOUT_ADDR 0xC5 #define PMB_MFR_FAULT_BIT_ADDR 0xC7 /* * Header Files inclusion */ #include "gpio_driver.h" #include "stm32f401xx.h" #include "USART_driver.h" #include // boolean header file ////////////////////////////////////////////////////////////// /* * Function Declarations */ void tim_init(); void Read_Input_8(); void Read_Input_16(); void Read_Output(); void cmd_transmit(); int Calculate_checksum(); int ack_checksum_calculate(); void RS232_Recieve(); void recieve_cmd_process(); void recieve_ack_process(); void enable_transmission(); void ack_transmit(); void UART_init(); void i2c_init(); void i2c_PS_read(uint8_t slave_addr, uint8_t read_register_addr, uint8_t *read_register_data); // Power Supply Read //void i2c_PS_read(uint8_t i2c_S, uint8_t slave_addr, uint8_t pointer_addr, uint8_t *read_register_data); void i2c_tmp_read(uint8_t slave_addr, uint8_t pointer_addr, uint8_t *temperature); #ifdef new_protocol void analog_transmit(); void digital_transmit(); int analog_checksum(); int digital_checksum(); #endif ////////////////////////////////////////////////////////////// /* * Structure Definitions */ // Transmit Frame Structure #ifdef new_protocol typedef struct { uint8_t SOF; uint8_t command; uint8_t NOB; uint8_t serial_no; uint8_t IP_status[3]; uint8_t OP_status[2]; uint8_t link_trans_state; uint8_t future_use; uint8_t checksum[2]; uint8_t EOF; // End of Frame }digital_trasnmit; digital_trasnmit digital_data; char *digital=(char*)&digital_data; typedef struct { uint8_t SOF; uint8_t command; uint8_t NOB; uint8_t PS_24_data[12]; uint8_t PS_48_1_data[12]; uint8_t PS_48_2_data[12]; uint8_t checksum[2]; uint8_t EOF; // End of Frame }analog_trasnmit; analog_trasnmit analog_data; char *analog=(char*)&analog_data; #else typedef struct { //char dummy; uint8_t SOF; // start of Frame uint8_t command; // command : 0xCC and ACK : 0x55 uint8_t NOB; // Number of Bytes uint8_t serial_no; uint8_t PS_24_data[12]; uint8_t PS_48_1_data[12]; uint8_t PS_48_2_data[12]; uint8_t IP_status[3]; uint8_t OP_status[2]; uint8_t link_trans_state; uint8_t future_use; uint8_t checksum[2]; uint8_t EOF; // End of Frame }transmit; transmit trans_packet; char *t=(char*)&trans_packet; #endif // Acknowledgment Frame Structure typedef struct { uint8_t SOF; uint8_t ack; uint8_t NOB; uint8_t serial_no; uint8_t response; uint8_t future_use[2]; uint8_t checksum[2]; uint8_t EOF; }ack; ack ACK; char *a = (char*)&ACK; ///////////////////////////////////////////////////////////////// /* * Enum Declarations */ // Receive Packet (ACK and Command) typedef enum { SOF_trans_state = 0, type_check, Len_check_trans_state, Data_Recv_trans_state, checksum_check, EOF_trans_state }UART_recv_trans_state; UART_recv_trans_state Recv_trans_state = 0; // Transmit Packet (ACK and Command) #ifdef new_protocol typedef enum { transmit_ack_1, transmit_ack_2, transmit_ack_3, transmit_ack_4, transmit_ack_5, transmit_ack_6, transmit_ack_7, transmit_ack_8, transmit_ack_9, transmit_ack_10, digi_transmited_1, digi_transmited_2, digi_transmited_3, digi_transmited_4, digi_transmited_5, digi_transmited_6, digi_transmited_7, digi_transmited_8, digi_transmited_9, digi_transmited_10, digi_transmited_11, digi_transmited_12, digi_transmited_13, digi_transmited_14, analog_transmited_1, analog_transmited_2, analog_transmited_3, analog_transmited_4, analog_transmited_5, analog_transmited_6, analog_transmited_7, analog_transmited_8, analog_transmited_9, analog_transmited_10, analog_transmited_11, analog_transmited_12, analog_transmited_13, analog_transmited_14, analog_transmited_15, analog_transmited_16, analog_transmited_17, analog_transmited_18, analog_transmited_19, analog_transmited_20, analog_transmited_21, analog_transmited_22, analog_transmited_23, analog_transmited_24, analog_transmited_25, analog_transmited_26, analog_transmited_27, analog_transmited_28, analog_transmited_29, analog_transmited_30, analog_transmited_31, analog_transmited_32, analog_transmited_33, analog_transmited_34, analog_transmited_35, analog_transmited_36, analog_transmited_37, analog_transmited_38, analog_transmited_39, analog_transmited_40, analog_transmited_41, analog_transmited_42, }transmit_bytes; transmit_bytes trans_state = 0; #else typedef enum { transmit_ack_1, transmit_ack_2, transmit_ack_3, transmit_ack_4, transmit_ack_5, transmit_ack_6, transmit_ack_7, transmit_ack_8, transmit_ack_9, transmit_ack_10, bytes_transmited_1, bytes_transmited_2, bytes_transmited_3, bytes_transmited_4, bytes_transmited_5, bytes_transmited_6, bytes_transmited_7, bytes_transmited_8, bytes_transmited_9, bytes_transmited_10, bytes_transmited_11, bytes_transmited_12, bytes_transmited_13, bytes_transmited_14, bytes_transmited_15, bytes_transmited_16, bytes_transmited_17, bytes_transmited_18, bytes_transmited_19, bytes_transmited_20, bytes_transmited_21, bytes_transmited_22, bytes_transmited_23, bytes_transmited_24, bytes_transmited_25, bytes_transmited_26, bytes_transmited_27, bytes_transmited_28, bytes_transmited_29, bytes_transmited_30, bytes_transmited_31, bytes_transmited_32, bytes_transmited_33, bytes_transmited_34, bytes_transmited_35, bytes_transmited_36, bytes_transmited_37, bytes_transmited_38, bytes_transmited_39, bytes_transmited_40, bytes_transmited_41, bytes_transmited_42, bytes_transmited_43, bytes_transmited_44, bytes_transmited_45, bytes_transmited_46, bytes_transmited_47, bytes_transmited_48, bytes_transmited_49, bytes_transmited_50 }transmit_bytes; transmit_bytes trans_state = 0; #endif // PS_state checking for input reading typedef enum { PS_24_PMB_READ_VOUT = 0, PS_24_PMB_READ_IOUT, PS_24_PMB_READ_POUT, PS_24_PMB_MFR_AUX_VOUT, PS_24_PMB_MFR_AUX_IOUT, PS_24_PMB_MFR_FAULT_BIT, PS_48_1_PMB_READ_VOUT, PS_48_1_PMB_READ_IOUT, PS_48_1_PMB_READ_POUT, PS_48_1_PMB_MFR_AUX_VOUT, PS_48_1_PMB_MFR_AUX_IOUT, PS_48_1_PMB_MFR_FAULT_BIT, PS_48_2_PMB_READ_VOUT, PS_48_2_PMB_READ_IOUT, PS_48_2_PMB_READ_POUT, PS_48_2_PMB_MFR_AUX_VOUT, PS_48_2_PMB_MFR_AUX_IOUT, PS_48_2_PMB_MFR_FAULT_BIT, }ps_state; ps_state PS_STATE; typedef enum { Start_Bit_SET_24, Send_Slave_Addr_Read_24, Send_Slave_Addr_Write_24, Send_Mem_Addr_24, ReStart_Bit_SET_24, BTF_24, BTF_R_24, Stop_Condition_24, NACK_24, Read_data_24, }I2C_State; I2C_State i2c_S; uint8_t data, data1, dummy, data; /* * Instrument ID's */ typedef enum { Pro_Grasp_Forceps = 1, Tip_up_Fenestrated_Grasper, Medium_Large_Clip_Applier, Monopolar_Curved_Scissors_Hot_Shears, Permanent_Cautery_Spatulax, Permanent_cautery_Hook, Fenestrated_Bipolar_Forceps, Debakey_Forceps, Maryland_Bipolar_Forceps, Curved_Bipolar_Dissector, Micro_Bipolar_Forceps, Black_Diamond_Micro_Forceps, Large_Clip_Applier, Small_Clip_Applier, Potts_Scissors, Round_Tip_Scissors, Large_Needle_Driver, Mega_Suture_Cut_Needle_Driver, Long_Tip_Forceps, }instrument_id; instrument_id inst_id; /* * Link Status */ typedef enum { Healthy_Comm = 0xF8, Checksum_Failure = 0xF9, Format_mismatch = 0xFA, No_Response = 0xFB, }link_status; link_status link_state; /* * Flag Structure */ typedef struct { bool Flag3; bool Flag_RS232_Trans; bool Flag_RS232_Rec; bool Flag_8; bool Flag_16; bool ack_complete; bool cmd_complete; //Button Status flag bool resume_pres_state; bool resume_prev_state; bool resume_interm1_state; bool resume_interm2_state; bool ack_pres_state; bool ack_prev_state; bool ack_interm1_state; bool ack_interm2_state; bool homing_pres_state; bool homing_prev_state; bool homing_interm1_state; bool homing_interm2_state; bool power_on_pres_state; bool power_off_pres_state; bool power_prev_state; bool emer_pres_state; bool emer_prev_state; bool emergency_flag; // Mux Input Flags bool FP1_NO_pres; bool FP1_NO_prev; bool FP1_NO_interm1; bool FP1_NC_interm1; bool FP1_NC_pres; bool FP1_NC_prev; bool FP1_NO_interm2; bool FP1_NC_interm2; bool FP2_NO_pres; bool FP2_NO_prev; bool FP2_NO_interm1; bool FP2_NC_interm1; bool FP2_NC_pres; bool FP2_NC_prev; bool FP2_NO_interm2; bool FP2_NC_interm2; bool FP3_NO_pres; bool FP3_NO_prev; bool FP3_NO_interm1; bool FP3_NC_interm1; bool FP3_NC_pres; bool FP3_NC_prev; bool FP3_NO_interm2; bool FP3_NC_interm2; bool FP4_NO_pres; bool FP4_NO_prev; bool FP4_NO_interm1; bool FP4_NC_interm1; bool FP4_NC_pres; bool FP4_NC_prev; bool FP4_NO_interm2; bool FP4_NC_interm2; bool F4_to_MCU_interm1; bool F3_to_MCU_interm1; bool F2_to_MCU_interm1; bool F1_to_MCU_interm1; bool F4_to_MCU_interm2; bool F3_to_MCU_interm2; bool F2_to_MCU_interm2; bool F1_to_MCU_interm2; bool F4_to_MCU_pres; bool F4_to_MCU_prev; bool F3_to_MCU_pres; bool F3_to_MCU_prev; bool F2_to_MCU_pres; bool F2_to_MCU_prev; bool F1_to_MCU_pres; bool F1_to_MCU_prev; bool mono_cut; bool mono_coag; bool bi_cut; bool bi_coag; // Power Supply Flags bool PS24_pres; bool PS48_1_pres; bool PS48_2_pres; bool PS24_prev; bool PS48_1_prev; bool PS48_2_prev; bool IPC_ON; bool IPC_OFF; bool IPC_state; // FAN Flags bool FAN1_pres; bool FAN2_pres; bool FAN1_prev; bool FAN2_prev; // Temp Flag bool TMP_pres; bool TMP_prev; bool force_shut_down; bool cmd_under_process; bool checksum_val_failure; bool FP1_Relay_pres; bool FP2_Relay_pres; bool FP3_Relay_pres; bool FP4_Relay_pres; bool PS24_Relay_pres; bool PS48_1_Relay_pres; bool PS48_2_Relay_pres; bool IPC_ON_pres; bool IPC_Reset_pres; bool FAN1_CTR_pres; bool FAN2_CTR_pres; bool RT_LED_pres; bool first_ON; bool send_ACK_Flag; bool ANA_TIM_DONE; bool ACK_RC; bool CMD_RC; bool IPC_Stable; }FLAG; FLAG status_flag; /* * Vairable Structure */ typedef struct { uint8_t ON_CNT; uint8_t status_byte; uint8_t data; uint8_t ack_checksum; uint8_t cmd_checksum; uint8_t buff; uint8_t i; uint8_t cmd_buffer[14]; uint8_t recieve_cmd_process_buffer[14]; uint8_t ack_buffer[10]; uint8_t recieve_ack_process_buffer[10]; uint8_t j; uint8_t command_flag; uint8_t time_check; uint8_t trans_state; uint8_t rec_cmd_cnt; uint8_t rec_ack_cnt; uint8_t trans_cmd_cnt; uint8_t trans_ack_cnt; uint8_t PS_time; uint8_t PS_var; #ifdef new_protocol uint8_t digi_var; uint8_t analog_var; #endif uint16_t IPC_OFF_time; uint16_t IPC_ON_time; uint16_t PS_stable_time; uint16_t tim; uint16_t time1; uint16_t time3; uint16_t time4; uint16_t time5; uint16_t timeout; uint16_t resume_time; uint16_t ack_time; uint16_t homing_time; #ifdef new_protocol uint16_t analog_trans_time; #endif uint8_t cmd_serial_no; uint8_t ack_serial_no; }VAR; VAR var; uint16_t tx; /* * Peripheral Variable Declarations */ GPIO_HANDLE MUX_1, MUX_2, USART, i2c, Relay; USART_Handle USART_2; /* * Response Byte Array */ char response_byte[4] = {0x01,0xFF,0x03,0x04}; /* * Link State Array */ //char link_state[4] = {0xF8, 0xF9, 0xFA, 0xFB}; ////////////////// Timer Init ///////////////////// void tim_init() { // Enable clock for timer 2 TIM2_EN; // will have to be used as PWM_FAN_2 // Generate 1ms delay from 16MHz clock, prescalar value is 16000-1 TIM2->TIMx_PSC = 16000 - 1; // Store the count in ARR TIM2->TIMx_ARR = 8; // 10 milliseconds // Timer Count = 0 TIM2->TIMx_CNT = 0; // counter reset // Enable clock for timer 3 // will have to be used as PWM_FAN_1 TIM3_EN; // Generate 1ms delay from 16MHz clock, prescalar value is 16000-1 TIM3->TIMx_PSC = 16000 - 1; // Store the count in ARR TIM3->TIMx_ARR = 10; // 10 milliseconds // Timer Count = 0 TIM3->TIMx_CNT = 0; // counter reset // Timer // Enable clock for timer 4 TIM4_EN; // Generate 1ms delay from 16MHz clock, prescalar value is 16000-1 TIM4->TIMx_PSC = 16000 - 1; // Store the count in ARR TIM4->TIMx_ARR = 1; // 1 milliseconds // Timer Count = 0 TIM4->TIMx_CNT = 0; // counter reset // Enable clock for timer 5 TIM5_EN; // Generate 1ms delay from 16MHz clock, prescalar value is 16000-1 TIM5->TIMx_PSC = 16000 - 1; // Store the count in ARR TIM5->TIMx_ARR = 1; // 1 milliseconds // Timer Count = 0 TIM5->TIMx_CNT = 0; // counter reset // Interrupt Priority //GPIO_IRQPriorityConfig(TIM3_IRQ, 1); //GPIO_IRQPriorityConfig(TIM2_IRQ, 10); // Enable Timer Interrupt GPIO_IRQInterruptConfig(TIM2_IRQ, 1); GPIO_IRQInterruptConfig(TIM3_IRQ, 1); GPIO_IRQInterruptConfig(TIM4_IRQ, 1); GPIO_IRQInterruptConfig(TIM5_IRQ, 1); // Enable Timer Interrupt TIM2->TIMx_DIER |= (1 << 0); TIM3->TIMx_DIER |= (1 << 0); TIM4->TIMx_DIER |= (1 << 0); TIM5->TIMx_DIER |= (1 << 0); } void i2c_init() { // I2C3 CLK enable I2C3_CLK_EN; // Freq setting 16MHz I2C3->CR2 |= (16 << 0); //CCR configuration I2C3->CCR = 0x50; // T-Rise configuration I2C3->TRISE = 0x17; // Peripheral Enable I2C3->CR1 |= (1 << 0); //I2C3->CR1 |= (1 << 10); // Set OAR bit I2C3->OAR1 |= (1 << 14); } void UART_init() { // RCC enable USART2_CLK_EN; USART_2.pUSARTx = USART2; USART_2.USART_Config.Baud_Rate = USART_BAUD_9600; USART_2.USART_Config.NoOfStopBits = USART_STOPB_1_; USART_2.USART_Config.WordLength = USART_WORDLEN_8; USART_2.USART_Config.USART_Mode = USART_TxRx; USART_2.USART_Config.ParityControl = USART_Parity_Disable; USART_2.USART_Config.HWFlowControl = USART_DI_RTS_CTS; // USART Init USART_Init(&USART_2); // Enable UART RxNE Interrupt USART_2.pUSARTx->USART_CR1 |= ((1 << 5)); // USART NVIC Setting GPIO_IRQInterruptConfig(IRQ_NO_USART2, 1); // USART Peripheral Enable USART_EnDi(USART_2.pUSARTx, 1); } bool state; int main() { // Peripheral Clock Enable GPIOA_PCLK_EN; GPIOB_PCLK_EN; GPIOC_PCLK_EN; ///////////////////////// I2C Initialization /////////////////////////// // Alternate functionality i2c.pGPIOx = GPIOA; i2c.GPIO_PinConfig.GPIO_PinAltFunMode = 4; // i2c3 SCL i2c.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_AF; i2c.GPIO_PinConfig.GPIO_PinNumber = 8; i2c.GPIO_PinConfig.GPIO_PinOPType = GPIO_OUT_OD; i2c.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_NO_PUPD; i2c.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_LOW; GPIO_Init(&i2c); i2c.pGPIOx = GPIOC; i2c.GPIO_PinConfig.GPIO_PinAltFunMode = 4; // i2c3 SDA i2c.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_AF; i2c.GPIO_PinConfig.GPIO_PinNumber = 9; i2c.GPIO_PinConfig.GPIO_PinOPType = GPIO_OUT_OD; i2c.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_NO_PUPD; i2c.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_LOW; GPIO_Init(&i2c); ///////////////////////// MUX 1 Pin Initialization //////////////////// // MUX Input MUX_1.pGPIOx = GPIOA; MUX_1.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_OUT; MUX_1.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_PU; MUX_1.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; MUX_1.GPIO_PinConfig.GPIO_PinNumber = 4; // MUX_1_A GPIO_Init(&MUX_1); MUX_1.GPIO_PinConfig.GPIO_PinNumber = 5; // MUX_1_B GPIO_Init(&MUX_1); MUX_1.GPIO_PinConfig.GPIO_PinNumber = 6; // MUX_1_C GPIO_Init(&MUX_1); // MUX1 Output MUX_1.pGPIOx = GPIOA; MUX_1.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_IN; MUX_1.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; MUX_1.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_NO_PUPD; MUX_1.GPIO_PinConfig.GPIO_PinNumber = 10; // MUX_1_OP GPIO_Init(&MUX_1); ///////////////////////// MUX 2 Pin Initialization //////////////////// // MUX1 Input MUX_2.pGPIOx = GPIOC; MUX_2.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_OUT; MUX_2.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_PU; MUX_2.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; MUX_2.GPIO_PinConfig.GPIO_PinNumber = 10; // MUX_2_A GPIO_Init(&MUX_2); MUX_2.GPIO_PinConfig.GPIO_PinNumber = 11; // MUX_2_B GPIO_Init(&MUX_2); MUX_2.GPIO_PinConfig.GPIO_PinNumber = 12; // MUX_2_C GPIO_Init(&MUX_2); // MUX1 Output MUX_2.pGPIOx = GPIOA; MUX_2.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_IN; MUX_2.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_NO_PUPD; MUX_2.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; MUX_2.GPIO_PinConfig.GPIO_PinNumber = 11; // MUX_2_OP GPIO_Init(&MUX_2); //////////////////////// Relay Configuration //////////////////////// Relay.pGPIOx = GPIOC; Relay.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_OUT; Relay.GPIO_PinConfig.GPIO_PinOPType = GPIO_OUT_PUSHPULL; Relay.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; Relay.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_PU; Relay.GPIO_PinConfig.GPIO_PinNumber = 4; GPIO_Init(&Relay); // 48V power supply 1 Relay.GPIO_PinConfig.GPIO_PinNumber = 5; GPIO_Init(&Relay); // 48V power supply 2 Relay.pGPIOx = GPIOA; Relay.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_OUT; Relay.GPIO_PinConfig.GPIO_PinOPType = GPIO_OUT_PUSHPULL; Relay.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; Relay.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_PU; Relay.GPIO_PinConfig.GPIO_PinNumber = 12; GPIO_Init(&Relay); // 24V power supply Relay.GPIO_PinConfig.GPIO_PinNumber = 0; GPIO_Init(&Relay); // Mono Cut Output Relay Relay.GPIO_PinConfig.GPIO_PinNumber = 1; GPIO_Init(&Relay); // Mono GOAG Output Relay Relay.pGPIOx = GPIOA; Relay.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_OUT; Relay.GPIO_PinConfig.GPIO_PinOPType = GPIO_OUT_PUSHPULL; Relay.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; Relay.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_PU; Relay.GPIO_PinConfig.GPIO_PinNumber = 1; GPIO_Init(&Relay); // IPC turn ON ///////////////////////// UART Alternate Functionality Pin Initialization //////////////////// USART.pGPIOx = GPIOA; USART.GPIO_PinConfig.GPIO_PinMode = GPIO_MODE_AF; USART.GPIO_PinConfig.GPIO_PinAltFunMode = 7; USART.GPIO_PinConfig.GPIO_PinOPType = GPIO_OUT_PUSHPULL; USART.GPIO_PinConfig.GPIO_PinOutSpeed = GPIO_OUT_SPEED_HIGH; USART.GPIO_PinConfig.GPIO_PinPuPdControl = GPIO_OUT_PU; // Here it is very important to call the GPIO_init func for each and every pin initialization // bcoz or else pinmode selection does not happen properly if dealing with multiple pin init. // Rx Pin USART.GPIO_PinConfig.GPIO_PinNumber = PIN_NO_3; GPIO_Init(&USART); // Tx Pin USART.GPIO_PinConfig.GPIO_PinNumber = PIN_NO_2; GPIO_Init(&USART); // USART 2 Peripheral initialization UART_init(); // Timer Init tim_init(); // I2C Init i2c_init(); ///////////////////// EXTI Interrupt Initialization ///////////////////// // Enable SYSCFG RCC->APB2ENR |= (1 << 14); // Port B, EXTI for pin 0 (Emergency Button) SYSCFG->SYSCFG_EXTICR1 |= (1 << 0); // Port A, EXTI for pin 9 (Power Button) SYSCFG->SYSCFG_EXTICR3 |= (0 << 4); // Mask Disable for pin 0 (Emergency Button) EXTI->EXTI_IMR |= (1 << 0); #ifdef shashwat_test // Port C, EXTI for pin 14 (Power ON Button) SYSCFG->SYSCFG_EXTICR4 |= (2 << 4); // Mask Disable for pin 0 (Power Button) EXTI->EXTI_IMR |= (1 << 13); // Enabling the falling edge trigger for pin 9 (Power Button) EXTI->EXTI_FTSR |= (1 << 13); EXTI->EXTI_RTSR &= ~(1 << 13); //Setting Configuration for EXTI GPIO_IRQInterruptConfig(IRQ_NO_EXTI10_15, SET); #else // Mask Disable for pin 0 (Power Button) EXTI->EXTI_IMR |= (1 << 9); // Enabling the falling edge trigger for pin 9 (Power Button) EXTI->EXTI_FTSR |= (1 << 9); EXTI->EXTI_RTSR &= ~(1 << 9); #endif // Enabling the falling edge trigger for pin 0 (Emergency Button) EXTI->EXTI_FTSR |= (1 << 0); EXTI->EXTI_RTSR |= (1 << 0); //Setting Configuration for EXTI GPIO_IRQInterruptConfig(IRQ_NO_EXTI0, SET); GPIO_IRQInterruptConfig(IRQ_NO_EXTI5_9, SET); // UART interrupt setting GPIO_IRQInterruptConfig(IRQ_NO_USART2, SET); // Check Emergency BTN at power ON if(GPIO_ReadInputPin(GPIOB, 0) == 0) { status_flag.emer_pres_state = SET; // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 1); // 48V GPIO_WriteOutputPin(GPIOC, 5, 1); // 48V } TIM2->TIMx_CR1 |= (1 << 0); // Timer2 Enable for 8ms while(1) { if(status_flag.emergency_flag == SET) { if(GPIO_ReadInputPin(GPIOB, 0) == 0) // Emergency Stop pressed { status_flag.emer_prev_state = status_flag.emer_pres_state; status_flag.emer_pres_state = SET; // Mask Enable for pin 0 (Power Button) //EXTI->EXTI_IMR &= ~(1 << 9); // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 0); // 48V GPIO_WriteOutputPin(GPIOC, 5, 0); // 48V } if(GPIO_ReadInputPin(GPIOB, 0) == 1) // Emergency Stop released { status_flag.emer_prev_state = status_flag.emer_pres_state; status_flag.emer_pres_state = CLEAR; if (status_flag.first_ON == 1) { // Switch ON 48V power supplies (Active-Low Configuration) GPIO_WriteOutputPin(GPIOC, 4, 1); // 48V GPIO_WriteOutputPin(GPIOC, 5, 1); // 48V var.tim = 0; //var.time1 = 0; } } // clear the flag status_flag.emergency_flag = CLEAR; } if(status_flag.IPC_OFF == SET) { // clear Flag status_flag.IPC_OFF = 0; } if(status_flag.IPC_ON == SET) { // SET IPC_State status_flag.IPC_state = 1; // SET IPC_ON flag status_flag.IPC_ON = CLEAR; TIM2->TIMx_CR1 |= (1 << 0); } if (status_flag.Flag3 == SET) { var.time3 = 0; if ((var.ON_CNT % 2) != 0) { // SET Link_state as No_response for the first communication until ACK is received #ifdef new_protocol digital_data.link_trans_state = No_Response; // No response state #endif GPIO_WriteOutputPin(GPIOA, 12, 1); // 24V // Enable for 1sec, for stabilizing Power supply TIM4->TIMx_CR1 |= (1 << 0); if(status_flag.emer_pres_state == CLEAR) { // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 1); // 48V GPIO_WriteOutputPin(GPIOC, 5, 1); // 48V } status_flag.power_prev_state = status_flag.power_on_pres_state; status_flag.power_on_pres_state = !status_flag.power_on_pres_state; status_flag.first_ON = 1; TIM2->TIMx_CR1 |= (1 << 0); // Timer2 Enable for 8ms } else { GPIO_WriteOutputPin(GPIOC, 4, 0); // 48V GPIO_WriteOutputPin(GPIOC, 5, 0); // 48V GPIO_WriteOutputPin(GPIOA, 12, 0); // 24V status_flag.power_prev_state = status_flag.power_on_pres_state; status_flag.power_on_pres_state = !status_flag.power_on_pres_state; status_flag.first_ON = 0; // Disable the first power-On // ON CNT reset var.ON_CNT = 0; // IPC state reset status_flag.IPC_state = 0; // reset timer value var.IPC_ON_time = 0; // reset time1 var.time1 = 0; TIM2->TIMx_CR1 &= ~(1 << 0); // Timer2 Disable for 8ms } // clear the flag status_flag.Flag3 = CLEAR; } if(status_flag.Flag_8 == SET && status_flag.emer_pres_state == 0) // 8ms IO Check { Read_Input_8(); status_flag.Flag_8 = CLEAR; } if(status_flag.Flag_16 == SET && status_flag.emer_pres_state == 0) // 16ms Check { Read_Input_16(); status_flag.Flag_16 = CLEAR; } if(status_flag.Flag_RS232_Trans == SET) // Transmit at every 1sec { var.time1 = 0; // reset time1 counter at every 1sec #ifdef new_protocol digital_transmit(); #else cmd_transmit(); // call transmit function #endif //Flag_RS232_Trans = 0; } if(status_flag.cmd_complete == SET) { recieve_cmd_process(); // processing the IPC data once completely fetched status_flag.cmd_complete = CLEAR; } if(status_flag.ack_complete == SET) { recieve_ack_process(); // processing the ACK data once completely fetched status_flag.ack_complete = CLEAR; } if(status_flag.send_ACK_Flag == SET) { ack_transmit(); // ACK Transmit Flag status_flag.send_ACK_Flag = CLEAR; } /////////////// Timer ISR's count checking //////////////////////// /* * Count checking for 3 second debounce and long press for Power Button ON/OFF */ if (var.time3 == 300) // 3 second long-press timer check { // Read the input status again at every 10ms if (GPIO_ReadInputPin(GPIOA, 9) == 0) { TIM3->TIMx_CR1 &= ~(1 << 0); // Disable timer counting var.ON_CNT++; var.time3 = 0; status_flag.Flag3 = SET; } } /* * Count checking for Power Supply Input Reading based on state variable */ if(var.PS_time == PS_READ_TIME) { switch(PS_STATE) { /* // 24V Power Supply Reading case PS_24_PMB_READ_VOUT: { // clear variable var.PS_var = 0; // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_READ_IOUT; #ifdef new_protocol // i2c_PS_read(PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); i2c_PS_read( PS24_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS24_ADDR, PMB_READ_VOUT_ADDR, &trans_packet.PS_24_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_24_PMB_READ_IOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_READ_POUT; #ifdef new_protocol //i2c_PS_read(PS24_ADDR, PMB_READ_IOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS24_ADDR, PMB_READ_IOUT_ADDR, &trans_packet.PS_24_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_24_PMB_READ_POUT: { // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_MFR_AUX_VOUT; #ifdef new_protocol //i2c_PS_read(PS24_ADDR, PMB_READ_POUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS24_ADDR, PMB_READ_POUT_ADDR, &trans_packet.PS_24_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_24_PMB_MFR_AUX_VOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_MFR_AUX_IOUT; #ifdef new_protocol //i2c_PS_read(PS24_ADDR, PMB_MFR_AUX_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS24_ADDR, PMB_MFR_AUX_VOUT_ADDR, &trans_packet.PS_24_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_24_PMB_MFR_AUX_IOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_MFR_FAULT_BIT; #ifdef new_protocol //i2c_PS_read(PS24_ADDR, PMB_MFR_AUX_IOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS24_ADDR, PMB_MFR_AUX_IOUT_ADDR, &trans_packet.PS_24_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_24_PMB_MFR_FAULT_BIT: { // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_READ_VOUT; #ifdef new_protocol //i2c_PS_read(PS24_ADDR, PMB_MFR_FAULT_BIT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS24_ADDR, PMB_MFR_FAULT_BIT_ADDR, &trans_packet.PS_24_data[var.PS_var]); #endif var.PS_var +=2; break; } */ /* // 48V Power Supply 1 Reading case PS_48_1_PMB_READ_VOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_1_PMB_READ_IOUT; #ifdef new_protocol i2c_PS_read(PS48_1_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_1_ADDR, PMB_READ_VOUT_ADDR, &trans_packet.PS_48_1_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_1_PMB_READ_IOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_1_PMB_READ_POUT; #ifdef new_protocol i2c_PS_read(PS48_1_ADDR, PMB_READ_IOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_1_ADDR, PMB_READ_IOUT_ADDR, &trans_packet.PS_48_1_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_1_PMB_READ_POUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_1_PMB_MFR_AUX_VOUT; #ifdef new_protocol i2c_PS_read(PS48_1_ADDR, PMB_READ_POUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_1_ADDR, PMB_READ_POUT_ADDR, &trans_packet.PS_48_1_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_1_PMB_MFR_AUX_VOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_1_PMB_MFR_AUX_IOUT; #ifdef new_protocol i2c_PS_read(PS48_1_ADDR, PMB_MFR_AUX_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_1_ADDR, PMB_MFR_AUX_VOUT_ADDR, &trans_packet.PS_48_1_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_1_PMB_MFR_AUX_IOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_1_PMB_MFR_FAULT_BIT; #ifdef new_protocol i2c_PS_read(PS48_1_ADDR, PMB_MFR_AUX_IOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_1_ADDR, PMB_MFR_AUX_IOUT_ADDR, &trans_packet.PS_48_1_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_1_PMB_MFR_FAULT_BIT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_2_PMB_READ_VOUT; #ifdef new_protocol i2c_PS_read(PS48_1_ADDR, PMB_MFR_FAULT_BIT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_1_ADDR, PMB_MFR_FAULT_BIT_ADDR, &trans_packet.PS_48_1_data[var.PS_var]); #endif var.PS_var +=2; break; } */ // 48V Power Supply 2 Reading /* case PS_48_2_PMB_READ_VOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_2_PMB_READ_IOUT; #ifdef new_protocol i2c_PS_read(PS48_2_ADDR, PMB_READ_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_2_ADDR, PMB_READ_VOUT_ADDR, &trans_packet.PS_48_2_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_2_PMB_READ_IOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_2_PMB_READ_POUT; #ifdef new_protocol i2c_PS_read(PS48_2_ADDR, PMB_READ_IOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_2_ADDR, PMB_READ_IOUT_ADDR, &trans_packet.PS_48_2_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_2_PMB_READ_POUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_2_PMB_MFR_AUX_VOUT; #ifdef new_protocol i2c_PS_read(PS48_2_ADDR, PMB_READ_POUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_2_ADDR, PMB_READ_POUT_ADDR, &trans_packet.PS_48_2_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_2_PMB_MFR_AUX_VOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_2_PMB_MFR_AUX_IOUT; #ifdef new_protocol i2c_PS_read(PS48_2_ADDR, PMB_MFR_AUX_VOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_2_ADDR, PMB_MFR_AUX_VOUT_ADDR, &trans_packet.PS_48_2_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_2_PMB_MFR_AUX_IOUT: { // clear timer var.PS_time = 0; PS_STATE = PS_48_2_PMB_MFR_FAULT_BIT; #ifdef new_protocol i2c_PS_read(PS48_2_ADDR, PMB_MFR_AUX_IOUT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_2_ADDR, PMB_MFR_AUX_IOUT_ADDR, &trans_packet.PS_48_2_data[var.PS_var]); #endif var.PS_var +=2; break; } case PS_48_2_PMB_MFR_FAULT_BIT: { // clear timer var.PS_time = 0; PS_STATE = PS_24_PMB_READ_VOUT; #ifdef new_protocol i2c_PS_read(PS48_2_ADDR, PMB_MFR_FAULT_BIT_ADDR, &analog_data.PS_24_data[var.PS_var]); #else i2c_PS_read(PS48_2_ADDR, PMB_MFR_FAULT_BIT_ADDR, &trans_packet.PS_48_2_data[var.PS_var]); #endif var.PS_var = 0; break; }*/ } } if(status_flag.ACK_RC == 1) { status_flag.ACK_RC = 0; // Clear the flag uint8_t Check_CS = var.ack_buffer[4]; // Calculate Checksum for(int i = 5; i < 7; i++) { Check_CS += var.ack_buffer[i]; Check_CS <<= 1; // Left Shift Data } // Checking calculated checksum with received checksum if((Check_CS == var.ack_buffer[8]) && (var.ack_buffer[7] == 0xFF)) { for (; var.rec_ack_cnt > 0; var.rec_ack_cnt--) { var.recieve_ack_process_buffer[var.rec_ack_cnt] = var.ack_buffer[var.rec_ack_cnt];// data copying var.ack_buffer[var.rec_ack_cnt] = 0; } var.recieve_ack_process_buffer[var.rec_ack_cnt] = var.ack_buffer[var.rec_ack_cnt]; var.ack_buffer[var.rec_ack_cnt] = 0; if (var.rec_ack_cnt == 0) { status_flag.ack_complete = 1;// Flag set for data copy Recv_trans_state = SOF_trans_state; // sending back to first trans_state var.command_flag = 0; // clear command_flag } // change the link_state to healthy communication #ifdef new_protocol digital_data.link_trans_state = Healthy_Comm; #endif if ((var.recieve_ack_process_buffer[3] == var.cmd_serial_no) && (var.recieve_ack_process_buffer[4] == 0x1))// command under process mode { status_flag.cmd_under_process = SET; var.cmd_serial_no++; // Global Serial Number count } } else { Recv_trans_state = SOF_trans_state; // sending back to first trans_state } } if(status_flag.CMD_RC == 1) { status_flag.CMD_RC = 0; // Clear the flag uint8_t Check_CS = var.cmd_buffer[4]; // Calculate Checksum for(int i = 5; i < 11; i++) { Check_CS += var.cmd_buffer[i]; Check_CS <<= 1; // Left Shift Data } // Checking calculated checksum with received checksum if((Check_CS == var.cmd_buffer[12]) && (var.cmd_buffer[11] == 0xFF)) { for (; var.rec_cmd_cnt > 0; var.rec_cmd_cnt--) { var.recieve_cmd_process_buffer[var.rec_cmd_cnt] = var.cmd_buffer[var.rec_cmd_cnt];// data copying var.cmd_buffer[var.rec_cmd_cnt] = 0; } var.recieve_cmd_process_buffer[var.rec_cmd_cnt] = var.cmd_buffer[var.rec_cmd_cnt]; var.cmd_buffer[var.rec_cmd_cnt] = 0; if (var.rec_cmd_cnt == 0) { status_flag.cmd_complete = 1;// Flag set for data copy Recv_trans_state = SOF_trans_state; // sending back to first trans_state var.command_flag = 0; // clear command_flag } // change the link_state to healthy communication #ifdef new_protocol digital_data.link_trans_state = Healthy_Comm; #endif } else { Recv_trans_state = SOF_trans_state; // sending back to first trans_state } } ///////////////////////////////////////////////////////////////////// #ifdef new_protocol /* * Counting for 5 minutes interval for sending analog data at once */ if(status_flag.ANA_TIM_DONE == 1) { analog_transmit(); TIM2->TIMx_CR1 |= (1 << 0); // Enable Timer for 8ms } #endif } } /* * Stop Button ISR Handler */ void EXTI0_IRQHandler() // Stop Button { // clear the interrupt 0 EXTI->EXTI_PR |= (1 << 0); status_flag.emergency_flag = SET; } /* * Power Button ISR Handler */ #ifdef shashwat_test void EXTI15_10_IRQHandler() // Power Button { // clear the interrupt 0 EXTI->EXTI_PR |= (1 << 14); var.time3 = 0; // Set time3 to 0 at every button press TIM3->TIMx_CR1 |= (1 << 0); // Timer3 Enable on button press } #else void EXTI9_5_IRQHandler() // Power Button { // clear the interrupt 9 EXTI->EXTI_PR |= (1 << 9); var.time3 = 0; // Set time3 to 0 at every button press TIM3->TIMx_CR1 |= (1 << 0); // Timer3 Enable on button press } #endif /* * Timer for 8ms, 16ms and 1second data transfer */ void TIM2_IRQHandler(void) { // clear timer interrupt TIM2->TIMx_SR &= ~(1 << 0); var.tim++; var.time1++; var.PS_time++; #ifdef new_protocol var.analog_trans_time++; #endif var.IPC_ON_time++; // IPC ON timer /* * Count checking for 8 ms debounce and input checking */ if(var.tim == IP_CHECK_8) { status_flag.Flag_8 = SET; } /* * Count checking for 16 ms debounce and input checking */ else if(var.tim == IP_CHECK_16) { var.tim = 0; // reset tim at every 16ms status_flag.Flag_16 = SET; } /* * Count checking for 1 second transmit interval */ if(var.time1 == TRANSMIT_INTERVAL) { TIM2->TIMx_CR1 &= ~(1 << 0); // Disable Timer for 8ms var.time1 = 0; //reset time status_flag.Flag_RS232_Trans = SET; } #ifdef new_protocol if(var.analog_trans_time == PS_TRANS_TIME) { // disable TIM2->TIMx_CR1 &= ~(1 << 0); status_flag.ANA_TIM_DONE = 1; // reset the 5min timer var.analog_trans_time = 0; // At every 5 min interval transmit the Analog Data packet //analog_transmit(); } #endif /* * IPC Turn ON time */ // if(status_flag.IPC_state == 0 && var.IPC_ON_time == IPC_TURN_ON_TIME) { // IPC ON Pin release GPIO_WriteOutputPin(GPIOA, 1, 0); // reset timer value var.IPC_ON_time = 0; // IPC ON status_flag.IPC_ON = 1; // Disable Timer TIM2->TIMx_CR1 &= ~(1 << 0); } } void TIM3_IRQHandler(void) { // clear timer interrupt TIM3->TIMx_SR &= ~(1 << 0); //time4++; var.time3++; //time5++; var.IPC_OFF_time++; // IPC OFF timer if(GPIO_ReadInputPin(GPIOA, 9) != 0) { var.time3 = 0; } /* * IPC Turn OFF */ // if(var.IPC_OFF_time == IPC_TURN_OFF_TIME) // { // // Active LOW config for IPC turn OFF // GPIO_WriteOutputPin(GPIOA, 1, 0); // // reset timer // var.IPC_OFF_time = 0; // // Set Flag // status_flag.IPC_OFF = 1; // // Disable Timer // TIM3->TIMx_CR1 &= ~(1 << 0); // } } /* * Timeout Timer Check ISR */ void TIM4_IRQHandler(void) { // clear timer interrupt TIM4->TIMx_SR &= ~(1 << 0); var.PS_stable_time++; var.timeout--; if(status_flag.IPC_Stable == 0 && var.PS_stable_time == PS_STABLE) { status_flag.IPC_Stable = 1; // reset stable timer var.PS_stable_time = 0; // reset ON timer //var.IPC_ON_time = 0; // IPC ON Active LOW Config GPIO_WriteOutputPin(GPIOA, 1, 1); // Enable 1 sec IPC ON Timer TIM2->TIMx_CR1 |= (1 << 0); // Disable the timer TIM4->TIMx_CR1 &= ~(1 << 0); // Clear state status_flag.IPC_state = 0; } if(var.timeout == 0) { // Disable UART TxE Interrupt USART_2.pUSARTx->USART_CR1 &= ~(1 << 7); Recv_trans_state = SOF_trans_state; } } /* * ACK, RESUME and HOMING BTN ISR, for 1 sec long press */ void TIM5_IRQHandler(void) { // clear timer interrupt TIM5->TIMx_SR &= ~(1 << 0); var.resume_time++; var.ack_time++; var.homing_time++; /* * Count checking for 1 second long press homing button */ if(var.homing_time == PRESS_1_SEC) { GPIO_WriteOutputPin(GPIOC, 10, 1); //D7 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 1); if(GPIO_ReadInputPin(GPIOA, 11)== 0) { // pause effect var.homing_time = 0; // set resume pres state 1 status_flag.homing_pres_state = SET; // disable 1 second long press timer TIM5->TIMx_CR1 &= ~(1 << 0); // Enable transmission enable_transmission(); } } /* * Count checking for 1 second long press resume button */ if(var.resume_time == PRESS_1_SEC) { GPIO_WriteOutputPin(GPIOC, 10, 0); //D6 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 1); if(GPIO_ReadInputPin(GPIOA, 11) == 0) { // pause effect var.resume_time = 0; // set resume pres state 1 status_flag.resume_pres_state = SET; // disable 1 second long press timer TIM5->TIMx_CR1 &= ~(1 << 0); // Enable transmission enable_transmission(); } } /* * Count checking for 1 second long press ACK button */ if(var.ack_time == PRESS_1_SEC) { GPIO_WriteOutputPin(GPIOC, 10, 1); //D5 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 1); if(GPIO_ReadInputPin(GPIOA, 11)== 0) { // pause effect var.ack_time = 0; // set resume pres state 1 status_flag.ack_pres_state = SET; // disable 1 second long press timer TIM5->TIMx_CR1 &= ~(1 << 0); // Enable transmission enable_transmission(); } } } /* * UART 2 interrupt handler for receiving as well as transmitting of ACK and Command Packet */ void USART2_IRQHandler(void) { if(USART_2.pUSARTx->USART_SR >> 5) // RxNE { // clear interrupt //USART_2.pUSARTx->USART_CR1 &= ~((1 << 5)); switch(Recv_trans_state) { case SOF_trans_state: { //var.timeout = RECV_TIMEOUT; // Enable Timer 4 for timeout //TIM4->TIMx_CR1 |= (1 << 0); var.buff = USART_2.pUSARTx->USART_DR; if(var.buff == 0xAA) { var.cmd_buffer[var.rec_cmd_cnt] = var.buff; var.ack_buffer[var.rec_ack_cnt] = var.buff; var.rec_cmd_cnt++; var.rec_ack_cnt++; Recv_trans_state = type_check; } else { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; Recv_trans_state = SOF_trans_state; } break; } case type_check: { //var.timeout = RECV_TIMEOUT; var.buff = USART_2.pUSARTx->USART_DR; if((var.buff == 0xCC) || (var.buff == 0x55)) { if (var.buff == 0xCC) // command { var.command_flag = 0xCC; var.cmd_buffer[var.rec_cmd_cnt] = var.buff; //var.cmd_checksum = var.buff; var.rec_cmd_cnt++; Recv_trans_state = Len_check_trans_state; var.rec_ack_cnt = 0; // clear ack_buffer } else if (var.buff == 0x55) // ACK { var.command_flag = 0x55; var.ack_buffer[var.rec_ack_cnt] = var.buff; //var.ack_checksum = var.buff; var.rec_ack_cnt++; Recv_trans_state = Len_check_trans_state; var.rec_cmd_cnt = 0; // clear temp_buffer } else { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; Recv_trans_state = SOF_trans_state; } } else { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; Recv_trans_state = SOF_trans_state; } //var.buff = 0; break; } case Len_check_trans_state: { //var.timeout = RECV_TIMEOUT; var.buff = USART_2.pUSARTx->USART_DR; if((var.buff == 14) || (var.buff == 10)) { Recv_trans_state = Data_Recv_trans_state; if((var.command_flag = 0xCC) && (var.buff == 14)) { var.cmd_buffer[var.rec_cmd_cnt] = var.buff; //var.cmd_checksum += var.buff; //var.cmd_checksum <<= 1; var.rec_cmd_cnt++; var.rec_ack_cnt = 0; } else if((var.command_flag = 0x55) && (var.buff == 10)) { var.ack_buffer[var.rec_ack_cnt] = var.buff; //var.ack_checksum += var.buff; //var.ack_checksum <<= 1; var.rec_ack_cnt++; var.rec_cmd_cnt=0; } } else { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; Recv_trans_state = SOF_trans_state; } var.buff = 0; break; } case Data_Recv_trans_state: { //var.timeout = RECV_TIMEOUT; var.buff = USART_2.pUSARTx->USART_DR; if (var.command_flag == 0xCC) { if ((var.rec_cmd_cnt > 1) && (var.rec_cmd_cnt < 13)) // i<9 { if(var.rec_cmd_cnt == 3) { var.ack_serial_no = var.buff; // store the serial_no received so that same can be send back in the ACK packet } var.cmd_buffer[var.rec_cmd_cnt] = var.buff; var.rec_cmd_cnt++; if(var.rec_cmd_cnt == 13) { Recv_trans_state = EOF_trans_state; } } else Recv_trans_state = SOF_trans_state; } else if (var.command_flag == 0x55) { if((var.rec_ack_cnt > 1) && (var.rec_ack_cnt < 9)) { var.ack_buffer[var.rec_ack_cnt] = var.buff; var.rec_ack_cnt++; if(var.rec_ack_cnt == 9) { Recv_trans_state = EOF_trans_state; } } else Recv_trans_state = SOF_trans_state; } else { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; Recv_trans_state = SOF_trans_state; } var.buff = 0; break; } case EOF_trans_state: { //var.timeout = RECV_TIMEOUT; var.buff = USART_2.pUSARTx->USART_DR; if(var.buff == 0xBB) { if(var.command_flag == 0xCC) { var.cmd_buffer[var.rec_cmd_cnt] = var.buff; status_flag.CMD_RC = 1; // Set the CMD Received flag } else if(var.command_flag == 0x55) { var.ack_buffer[var.rec_ack_cnt] = var.buff; //status_flag.ACK_RC = 1; // Set the ACK Received flag uint8_t Check_CS = var.ack_buffer[4]; // Calculate Checksum for(int i = 5; i < 7; i++) { Check_CS += var.ack_buffer[i]; Check_CS <<= 1; // Left Shift Data } // Checking calculated checksum with received checksum if((Check_CS == var.ack_buffer[8]) && (var.ack_buffer[7] == 0xFF)) { for (; var.rec_ack_cnt > 0; var.rec_ack_cnt--) { var.recieve_ack_process_buffer[var.rec_ack_cnt] = var.ack_buffer[var.rec_ack_cnt];// data copying var.ack_buffer[var.rec_ack_cnt] = 0; } var.recieve_ack_process_buffer[var.rec_ack_cnt] = var.ack_buffer[var.rec_ack_cnt]; var.ack_buffer[var.rec_ack_cnt] = 0; if (var.rec_ack_cnt == 0) { status_flag.ack_complete = 1;// Flag set for data copy Recv_trans_state = SOF_trans_state; // sending back to first trans_state var.command_flag = 0; // clear command_flag } if ((var.recieve_ack_process_buffer[3] == var.cmd_serial_no) && (var.recieve_ack_process_buffer[4] == 0x1))// command under process mode { status_flag.cmd_under_process = SET; var.cmd_serial_no++; // Global Serial Number count } } } } else if((var.command_flag != 0xCC) || (var.command_flag != 0x55)) { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; var.command_flag = 0; Recv_trans_state = SOF_trans_state; // start again } Recv_trans_state = SOF_trans_state; //var.buff = 0; break; } default: { var.rec_cmd_cnt = 0; var.rec_ack_cnt = 0; Recv_trans_state = SOF_trans_state; var.command_flag = 0; } } } if(USART_2.pUSARTx->USART_SR >> 7 && USART_2.pUSARTx->USART_CR1 >> 7) // TxE { //Disable UART TxE Interrupt //USART_2.pUSARTx->USART_CR1 &= ~((1 << 7)); //time_check = 0; switch(trans_state) { case transmit_ack_1: { trans_state = transmit_ack_2; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_2: { trans_state = transmit_ack_3; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_3: { trans_state = transmit_ack_4; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_4: { trans_state = transmit_ack_5; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_5: { trans_state = transmit_ack_6; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_6: { trans_state = transmit_ack_7; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_7: { trans_state = transmit_ack_8; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_8: { trans_state = transmit_ack_9; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_9: { trans_state = transmit_ack_10; USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_ack_cnt++; break; } case transmit_ack_10: { trans_state = 0; // Disable TxE interrupt USART_2.pUSARTx->USART_CR1 &= ~(1 << 7); // Clear TxE bit in SR register USART_2.pUSARTx->USART_SR &= ~(1 << 7); TIM2->TIMx_CR1 |= (1 << 0); // Enable Timer for 8ms USART_2.pUSARTx->USART_DR = a[var.trans_ack_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.trans_ack_cnt=0; // Disable the Timeout Timer //TIM4->TIMx_CR1 &= ~(1 << 0); // Disable Timer4 for 1ms break; } #ifdef new_protocol case digi_transmited_1: { //clear the variable var.digi_var = 0; trans_state = digi_transmited_2; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_2: { trans_state = digi_transmited_3; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_3: { trans_state = digi_transmited_4; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_4: { trans_state = digi_transmited_5; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_5: { trans_state = digi_transmited_6; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_6: { trans_state = digi_transmited_7; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_7: { trans_state = digi_transmited_8; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_8: { trans_state = digi_transmited_9; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_9: { trans_state = digi_transmited_10; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_10: { trans_state = digi_transmited_11; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_11: { trans_state = digi_transmited_12; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_12: { trans_state = digi_transmited_13; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_13: { trans_state = digi_transmited_14; USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var++; break; } case digi_transmited_14: { trans_state = digi_transmited_1; // Disable TxE interrupt USART_2.pUSARTx->USART_CR1 &= ~(1 << 7); // Clear TxE bit in SR register USART_2.pUSARTx->USART_SR &= ~(1 << 7); // Enable Timer 2 for 8ms TIM2->TIMx_CR1 |= (1 << 0); // Enable Timer for 8ms USART_2.pUSARTx->USART_DR = digital[var.digi_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.digi_var = 0; // Disable Timer 4 for 8ms TIM4->TIMx_CR1 &= ~(1 << 0); // Disable Timer4 for 1ms break; } case analog_transmited_1: { var.analog_var = 0; trans_state = analog_transmited_2; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_2: { trans_state = analog_transmited_3; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_3: { trans_state = analog_transmited_4; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_4: { trans_state = analog_transmited_5; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_5: { trans_state = analog_transmited_6; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_6: { trans_state = analog_transmited_7; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_7: { trans_state = analog_transmited_8; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_8: { trans_state = analog_transmited_9; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_9: { trans_state = analog_transmited_10; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_10: { trans_state = analog_transmited_11; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_11: { trans_state = analog_transmited_12; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_12: { trans_state = analog_transmited_13; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_13: { trans_state = analog_transmited_14; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_14: { trans_state = analog_transmited_15; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_15: { trans_state = analog_transmited_16; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_16: { trans_state = analog_transmited_17; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_17: { trans_state = analog_transmited_18; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_18: { trans_state = analog_transmited_19; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_19: { trans_state = analog_transmited_20; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_20: { trans_state = analog_transmited_21; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_21: { trans_state = analog_transmited_22; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_22: { trans_state = analog_transmited_23; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_23: { trans_state = analog_transmited_24; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_24: { trans_state = analog_transmited_25; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_25: { trans_state = analog_transmited_26; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_26: { trans_state = analog_transmited_27; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_27: { trans_state = analog_transmited_28; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_28: { trans_state = analog_transmited_29; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_29: { trans_state = analog_transmited_30; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_30: { trans_state = analog_transmited_31; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_31: { trans_state = analog_transmited_32; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_32: { trans_state = analog_transmited_33; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_33: { trans_state = analog_transmited_34; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_34: { trans_state = analog_transmited_35; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_35: { trans_state = analog_transmited_36; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_36: { trans_state = analog_transmited_37; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_37: { trans_state = analog_transmited_38; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_38: { trans_state = analog_transmited_39; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_39: { trans_state = analog_transmited_40; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_40: { trans_state = analog_transmited_41; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_41: { trans_state = analog_transmited_42; USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var++; break; } case analog_transmited_42: { trans_state = analog_transmited_1; // Disable TxE interrupt USART_2.pUSARTx->USART_CR1 &= ~(1 << 7); // Clear TxE bit in SR register USART_2.pUSARTx->USART_SR &= ~(1 << 7); USART_2.pUSARTx->USART_DR = analog[var.analog_var]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.analog_var = 0; // Enable Timer 2 for 8ms TIM2->TIMx_CR1 |= (1 << 0); // Disable Timer 4 for 1ms TIM4->TIMx_CR1 &= ~(1 << 0); break; } #else case bytes_transmited_1: { trans_state = bytes_transmited_2; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_2: { trans_state = bytes_transmited_3; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_3: { trans_state = bytes_transmited_4; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_4: { trans_state = bytes_transmited_5; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_5: { trans_state = bytes_transmited_6; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_6: { trans_state = bytes_transmited_7; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_7: { trans_state = bytes_transmited_8; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_8: { trans_state = bytes_transmited_9; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_9: { trans_state = bytes_transmited_10; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_10: { trans_state = bytes_transmited_11; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_11: { trans_state = bytes_transmited_12; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_12: { trans_state = bytes_transmited_13; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_13: { trans_state = bytes_transmited_14; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_14: { trans_state = bytes_transmited_15; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_15: { trans_state = bytes_transmited_16; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_16: { trans_state = bytes_transmited_17; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_17: { trans_state = bytes_transmited_18; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_18: { trans_state = bytes_transmited_19; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_19: { trans_state = bytes_transmited_20; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_20: { trans_state = bytes_transmited_21; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_21: { trans_state = bytes_transmited_22; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_22: { trans_state = bytes_transmited_23; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_23: { trans_state = bytes_transmited_24; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_24: { trans_state = bytes_transmited_25; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_25: { trans_state = bytes_transmited_26; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_26: { trans_state = bytes_transmited_27; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_27: { trans_state = bytes_transmited_28; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_28: { trans_state = bytes_transmited_29; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_29: { trans_state = bytes_transmited_30; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_30: { trans_state = bytes_transmited_31; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_31: { trans_state = bytes_transmited_32; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_32: { trans_state = bytes_transmited_33; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_33: { trans_state = bytes_transmited_34; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_34: { trans_state = bytes_transmited_35; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_35: { trans_state = bytes_transmited_36; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_36: { trans_state = bytes_transmited_37; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_37: { trans_state = bytes_transmited_38; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_38: { trans_state = bytes_transmited_39; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_39: { trans_state = bytes_transmited_40; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_40: { trans_state = bytes_transmited_41; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_41: { trans_state = bytes_transmited_42; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_42: { trans_state = bytes_transmited_43; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_43: { trans_state = bytes_transmited_44; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_44: { trans_state = bytes_transmited_45; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_45: { trans_state = bytes_transmited_46; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_46: { trans_state = bytes_transmited_47; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_47: { trans_state = bytes_transmited_48; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_48: { trans_state = bytes_transmited_49; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_49: { trans_state = bytes_transmited_50; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); //enable_transmission(); var.trans_cmd_cnt++; break; } case bytes_transmited_50: { status_flag.Flag_RS232_Trans = 0; // Disable TxE interrupt USART_2.pUSARTx->USART_CR1 &= ~(1 << 7); // Clear TxE bit in SR register //USART_2.pUSARTx->USART_SR &= ~(1 << 7); TIM2->TIMx_CR1 |= (1 << 0); // Enable Timer for 8ms trans_state = bytes_transmited_1; USART_2.pUSARTx->USART_DR = t[var.trans_cmd_cnt]; while (!(USART_2.pUSARTx->USART_SR >> 6) & 1); var.trans_cmd_cnt = 0; // Disable Timeout //TIM4->TIMx_CR1 &= ~(1 << 0); // Timer4 Disable tx++; break; } #endif default: { #ifdef new_protocol trans_state = digi_transmited_1 ; #else trans_state = bytes_transmited_1; #endif status_flag.Flag_RS232_Trans = 0; } } } // if(USART_2.pUSARTx->USART_SR >> 3) // { // uint8_t dummy = USART_2.pUSARTx->USART_DR; // dummy read // uint8_t dummy1 = USART_2.pUSARTx->USART_SR; // Clear SR // USART_2.pUSARTx->USART_SR &= ~(1 << 3); // } } /* * User Functions */ // Function for MUX reading at 8 ms void Read_Input_8() { //Mux1 GPIO_WriteOutputPin(GPIOA, 4, 0); //D0 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP2_NC_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D1 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP2_NO_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 0); //D2 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP1_NC_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D3 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP1_NO_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 0); //D4 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP4_NO_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D5 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP4_NC_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 0); //D6 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP3_NO_interm1 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D7 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP3_NC_interm1 = GPIO_ReadInputPin(GPIOA, 10); // Mux2 GPIO_WriteOutputPin(GPIOC, 10, 0); //D0 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F4_to_MCU_interm1 = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 1); //D1 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F3_to_MCU_interm1 = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 0); //D2 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F2_to_MCU_interm1 = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 1); //D3 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F1_to_MCU_interm1 = GPIO_ReadInputPin(GPIOA, 11); // GPIO_WriteOutputPin(GPIOC, 10, 0); //D4 (Not used) // GPIO_WriteOutputPin(GPIOC, 11, 0); // GPIO_WriteOutputPin(GPIOC, 12, 1); GPIO_WriteOutputPin(GPIOC, 10, 1); //D5 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 1); status_flag.ack_interm1_state = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 0); //D6 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 1); status_flag.resume_interm1_state = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 1); //D7 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 1); status_flag.homing_interm1_state = GPIO_ReadInputPin(GPIOA, 11); } // Function for MUX reading at 16 ms void Read_Input_16() { //Mux1 GPIO_WriteOutputPin(GPIOA, 4, 0); //D0 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP2_NC_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D1 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP2_NO_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 0); //D2 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP1_NC_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D3 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 0); status_flag.FP1_NO_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 0); //D4 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP4_NO_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D5 GPIO_WriteOutputPin(GPIOA, 5, 0); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP4_NC_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 0); //D6 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP3_NO_interm2 = GPIO_ReadInputPin(GPIOA, 10); GPIO_WriteOutputPin(GPIOA, 4, 1); //D3 GPIO_WriteOutputPin(GPIOA, 5, 1); GPIO_WriteOutputPin(GPIOA, 6, 1); status_flag.FP3_NC_interm2 = GPIO_ReadInputPin(GPIOA, 10); // Mux2 GPIO_WriteOutputPin(GPIOC, 10, 0); //D0 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F4_to_MCU_interm2 = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 1); //D1 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F3_to_MCU_interm2 = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 0); //D2 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F2_to_MCU_interm2 = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 1); //D3 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 0); status_flag.F1_to_MCU_interm2 = GPIO_ReadInputPin(GPIOA, 11); // GPIO_WriteOutputPin(GPIOC, 10, 0); //D4 (Not used) // GPIO_WriteOutputPin(GPIOC, 11, 0); // GPIO_WriteOutputPin(GPIOC, 12, 1); GPIO_WriteOutputPin(GPIOC, 10, 1); //D5 GPIO_WriteOutputPin(GPIOC, 11, 0); GPIO_WriteOutputPin(GPIOC, 12, 1); status_flag.ack_interm2_state = GPIO_ReadInputPin(GPIOA, 11); //11 GPIO_WriteOutputPin(GPIOC, 10, 0); //D6 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 1); status_flag.resume_interm2_state = GPIO_ReadInputPin(GPIOA, 11); GPIO_WriteOutputPin(GPIOC, 10, 1); //D7 GPIO_WriteOutputPin(GPIOC, 11, 1); GPIO_WriteOutputPin(GPIOC, 12, 1); status_flag.homing_interm2_state = GPIO_ReadInputPin(GPIOA, 11); // Check for state change for IO's //////////////////// if((status_flag.FP2_NC_interm2 == status_flag.FP2_NC_interm1) && (status_flag.FP2_NC_interm2 == 0)) { status_flag.FP2_NC_pres = SET; // Enable transmission enable_transmission(); } else status_flag.FP2_NC_pres = CLEAR; /////////////////////////////// if((status_flag.FP2_NO_interm2 == status_flag.FP2_NO_interm1) && (status_flag.FP2_NO_interm2 == 0)) { status_flag.FP2_NO_pres = SET; GPIO_WriteOutputPin(GPIOC, 1, 0); status_flag.mono_coag = 0; // Enable transmission enable_transmission(); } else { GPIO_WriteOutputPin(GPIOC, 1, 1); status_flag.mono_coag = 1; status_flag.FP2_NO_pres = CLEAR; } //////////////////// if((status_flag.FP1_NC_interm2 == status_flag.FP1_NC_interm1) && (status_flag.FP1_NC_interm2 == 0)) { status_flag.FP1_NC_pres = SET; // Enable transmission enable_transmission(); } else status_flag.FP1_NC_pres = CLEAR; ////////////////////////////////// if((status_flag.FP1_NO_interm2 == status_flag.FP1_NO_interm1) && (status_flag.FP1_NO_interm2 == 0)) { status_flag.FP1_NO_pres = SET; // MONO_Cut Relay Active Low Config GPIO_WriteOutputPin(GPIOC, 0, 0); status_flag.mono_cut = 0; // Enable transmission enable_transmission(); } else { status_flag.FP1_NO_pres = CLEAR; // MONO_Cut Relay OFF GPIO_WriteOutputPin(GPIOC, 0, 1); status_flag.mono_cut = 1; } ///////////////////////////////// if((status_flag.FP3_NC_interm2 == status_flag.FP3_NC_interm1) && (status_flag.FP3_NC_interm2 == 0)) { status_flag.FP3_NC_pres = SET; // Enable transmission enable_transmission(); } else status_flag.FP3_NC_pres = CLEAR; if((status_flag.FP3_NO_interm2 == status_flag.FP3_NO_interm1) && (status_flag.FP3_NO_interm2 == 0)) { status_flag.FP3_NO_pres = SET; // Enable transmission enable_transmission(); } else status_flag.FP3_NO_pres = CLEAR; if((status_flag.FP4_NC_interm2 == status_flag.FP4_NC_interm1) && (status_flag.FP4_NC_interm2 == 0)) { status_flag.FP4_NC_pres = SET; // Enable transmission enable_transmission(); } else status_flag.FP4_NC_pres = CLEAR; if((status_flag.FP4_NO_interm2 == status_flag.FP4_NO_interm1) && (status_flag.FP4_NO_interm2 == 0)) { status_flag.FP4_NO_pres = SET; // Enable transmission enable_transmission(); } else status_flag.FP4_NO_pres = CLEAR; if((status_flag.F4_to_MCU_interm2 == status_flag.F4_to_MCU_interm1) && (status_flag.F4_to_MCU_interm2 == 0)) { status_flag.F4_to_MCU_pres = SET; // Enable transmission enable_transmission(); } else status_flag.F4_to_MCU_pres = CLEAR; if((status_flag.F3_to_MCU_interm2 == status_flag.F3_to_MCU_interm1) && (status_flag.F3_to_MCU_interm2 == 0)) { status_flag.F3_to_MCU_pres = SET; // Enable transmission enable_transmission(); } else status_flag.F3_to_MCU_pres = CLEAR; /////////////////////////// if((status_flag.F2_to_MCU_interm2 == status_flag.F2_to_MCU_interm1) && (status_flag.F2_to_MCU_interm2 == 0)) { status_flag.F2_to_MCU_pres = SET; // Enable transmission enable_transmission(); } else status_flag.F2_to_MCU_pres = CLEAR; /////////////////////// if((status_flag.F1_to_MCU_interm2 == status_flag.F1_to_MCU_interm1) && (status_flag.F1_to_MCU_interm2 == 0)) { status_flag.F1_to_MCU_pres = SET; // Enable transmission enable_transmission(); } else status_flag.F1_to_MCU_pres = CLEAR; //////////////////////// if((status_flag.ack_interm2_state == status_flag.ack_interm1_state) && (status_flag.ack_interm2_state == 0)) { // enable 1 second long press timer TIM5->TIMx_CR1 |= (1 << 0); } else { // clear ack time var.ack_time = 0; // clear pres state status_flag.ack_pres_state = CLEAR; // disable 1 second long press timer //TIM5->TIMx_CR1 &= ~(1 << 0); } if((status_flag.homing_interm2_state == status_flag.homing_interm1_state) && (status_flag.homing_interm2_state == 0)) { // enable 1 second long press timer TIM5->TIMx_CR1 |= (1 << 0); } else { // clear homing time var.homing_time = 0; // clear pres state status_flag.homing_pres_state = CLEAR; // disable 1 second long press timer //TIM5->TIMx_CR1 &= ~(1 << 0); } if((status_flag.resume_interm2_state == status_flag.resume_interm1_state) && (status_flag.resume_interm2_state == 0)) { // enable 1 second long press timer TIM5->TIMx_CR1 |= (1 << 0); } else { // clear resume time var.resume_time = 0; // clear pres state status_flag.resume_pres_state = CLEAR; // disable 1 second long press timer //TIM5->TIMx_CR1 &= ~(1 << 0); } } /* * Received Command Processing Module */ void recieve_cmd_process() { if(var.recieve_cmd_process_buffer[5] == 1) // Emergency Stop byte checking { // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 1); // 48V GPIO_WriteOutputPin(GPIOC, 5, 1); // 48V } if(var.recieve_cmd_process_buffer[6] == 1) // Power ON/OFF byte checking { // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 1); // 48V GPIO_WriteOutputPin(GPIOC, 5, 1); // 48V GPIO_WriteOutputPin(GPIOA, 12, 1); // 24V } if(var.recieve_cmd_process_buffer[9]) // Foot Pedal Status { // read and process foot pedal status } } /* * Received ACK Processing Module */ void recieve_ack_process() { // if((var.recieve_ack_process_buffer[3] == var.cmd_serial_no) && (var.recieve_ack_process_buffer[4] == 0x1)) // command under process mode // { // status_flag.cmd_under_process = SET; // var.cmd_serial_no++; // Global Serial Number count // } if(var.recieve_ack_process_buffer[4] == 0xFF) // safe shut approved mode { // Normal Shutdown status_flag.force_shut_down = CLEAR; // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 0); // 48V GPIO_WriteOutputPin(GPIOC, 5, 0); // 48V GPIO_WriteOutputPin(GPIOA, 12, 0); // 24V // first ON Clear status_flag.first_ON = 0; // Disable the 8ms timer TIM2->TIMx_CR1 &= ~(1 << 0); // RESET time1 var.time1 = 0; // ON CNT reset var.ON_CNT = 0; // IPC state reset status_flag.IPC_state = 0; // reset timer value var.IPC_ON_time = 0; } else if(var.recieve_ack_process_buffer[4] == 0x03) // command not processed bcoz of checksum validation failure { status_flag.checksum_val_failure = SET; // resend the previous frame } else if(var.recieve_ack_process_buffer[4] == 0x04) // command not processed bcoz of application not responding { // Force shut down status_flag.force_shut_down = SET; // Switch off 48V power supplies (Active-Low Config) GPIO_WriteOutputPin(GPIOC, 4, 0); // 48V GPIO_WriteOutputPin(GPIOC, 5, 0); // 48V GPIO_WriteOutputPin(GPIOA, 12, 0); // 24V } } /* * Transmit ACK Module */ void ack_transmit() { var.time1 = 0; ACK.SOF = 0xAA; ACK.ack = 0x55; ACK.NOB = 0x10; ACK.serial_no = var.ack_serial_no; ACK.response = response_byte[0]; ACK.future_use[0] = 0xDD; ACK.future_use[1] = 0xDD; ACK.checksum[0] = ack_checksum_calculate(); ACK.checksum[1] = 0xFF; //dummy ACK.EOF = 0xBB; trans_state = transmit_ack_1; // trans_state setting for transmit of ACK // Enable UART TxE Interrupt USART_2.pUSARTx->USART_CR1 |= (1 << 7); // Call function to enable UART Tx interrupt enable_transmission(); } /* * Transmit Command Module */ #ifdef new_protocol void analog_transmit() { analog_data.SOF = 0xAA; analog_data.command = 0xCC; analog_data.NOB = 0x42; analog_data.checksum[0] = analog_checksum(); analog_data.checksum[1] = 0xFF; analog_data.EOF = 0xBB; // set the trans_state to start with trans_state = analog_transmited_1; // Disable the Flag status_flag.ANA_TIM_DONE = 0; // Enable UART TxE Interrupt USART_2.pUSARTx->USART_CR1 |= (1 << 7); // Enable transmission enable_transmission(); } void digital_transmit() { digital_data.SOF = 0xAA; digital_data.command = 0xDD; digital_data.NOB = 0x14; digital_data.serial_no = var.cmd_serial_no; digital_data.IP_status[0] = ((status_flag.power_on_pres_state << 0)|(status_flag.emer_pres_state << 1)|(status_flag.ack_pres_state << 2)|(status_flag.resume_pres_state << 3)|(status_flag.homing_pres_state << 4)|(status_flag.FP1_NO_pres << 5)|(status_flag.FP1_NC_pres << 6)|(status_flag.FP2_NO_pres << 7)) ; digital_data.IP_status[1] = ((status_flag.FP2_NC_pres << 0)|(status_flag.FP3_NO_pres << 1)|(status_flag.FP3_NC_pres << 2)|(status_flag.FP4_NO_pres << 3)|(status_flag.FP4_NC_pres << 4)|(status_flag.PS24_pres << 5)|(status_flag.PS48_1_pres << 6)|(status_flag.PS48_2_pres << 7)); digital_data.IP_status[2] = ((status_flag.FAN1_pres << 0)|(status_flag.FAN2_pres << 1)|(status_flag.TMP_pres << 2)|(status_flag.F1_to_MCU_pres << 3)|(status_flag.F2_to_MCU_pres << 4)|(status_flag.F3_to_MCU_pres << 5)|(status_flag.F4_to_MCU_pres << 6)|(status_flag.power_off_pres_state << 7)); digital_data.OP_status[0] = ((status_flag.FP1_Relay_pres << 0)|(status_flag.FP2_Relay_pres << 1)|(status_flag.FP3_Relay_pres << 2)|(status_flag.FP4_Relay_pres << 3)|(status_flag.PS24_Relay_pres << 4)|(status_flag.PS48_1_Relay_pres << 5)|(status_flag.PS48_2_Relay_pres << 6)|(status_flag.IPC_ON_pres << 7)); digital_data.OP_status[1] = ((status_flag.IPC_Reset_pres << 0)|(status_flag.FAN1_CTR_pres << 1)|(status_flag.FAN2_CTR_pres << 2)|(status_flag.RT_LED_pres << 3)|(0 << 4)|(0 << 5)|(0 <<6 )|(0 << 7)); digital_data.future_use = 0xFF; // Default Future Use Value digital_data.checksum[0] = digital_checksum(); digital_data.checksum[1] = 0xFF; // dummy digital_data.EOF = 0xBB; // set the trans_state to start with trans_state = digi_transmited_1; // Disable the Flag status_flag.Flag_RS232_Trans = CLEAR; // Enable UART TxE Interrupt USART_2.pUSARTx->USART_CR1 |= (1 << 7); // Enable transmission enable_transmission(); } #else uint8_t t1,t2,t3,t4,t5; void cmd_transmit() { trans_packet.SOF = 0xAA; trans_packet.command = 0xCC; trans_packet.NOB = 0x48; trans_packet.serial_no = var.cmd_serial_no; // trans_packet.IP_status[0] = ((status_flag.power_on_pres_state << 0)|(status_flag.emer_pres_state << 1)|(status_flag.ack_pres_state << 2)|(status_flag.resume_pres_state << 3)|(status_flag.homing_pres_state << 4)|(status_flag.FP1_NO_pres << 5)|(status_flag.FP1_NC_pres << 6)|(status_flag.FP2_NO_pres << 7)) ; // trans_packet.IP_status[1] = ((status_flag.FP2_NC_pres << 0)|(status_flag.FP3_NO_pres << 1)|(status_flag.FP3_NC_pres << 2)|(status_flag.FP4_NO_pres << 3)|(status_flag.FP4_NC_pres << 4)|(status_flag.PS24_pres << 5)|(status_flag.PS48_1_pres << 6)|(status_flag.PS48_2_pres << 7)); // trans_packet.IP_status[2] = ((status_flag.FAN1_pres << 0)|(status_flag.FAN2_pres << 1)|(status_flag.TMP_pres << 2)|(status_flag.F1_to_MCU_pres << 3)|(status_flag.F2_to_MCU_pres << 4)|(status_flag.F3_to_MCU_pres << 5)|(status_flag.F4_to_MCU_pres << 6)|(0 << 7)); // // trans_packet.OP_status[0] = ((status_flag.FP1_Relay_pres << 0)|(status_flag.FP2_Relay_pres << 1)|(status_flag.FP3_Relay_pres << 2)|(status_flag.FP4_Relay_pres << 3)|(status_flag.PS24_Relay_pres << 4)|(status_flag.PS48_1_Relay_pres << 5)|(status_flag.PS48_2_Relay_pres << 6)|(status_flag.IPC_ON_pres << 7)); // trans_packet.OP_status[1] = ((status_flag.IPC_Reset_pres << 0)|(status_flag.FAN1_CTR_pres << 1)|(status_flag.FAN2_CTR_pres << 2)|(status_flag.RT_LED_pres << 3)|(0 << 4)|(0 << 5)|(0 <<6 )|(0 << 7)); for(int i=0;i<12;i++) { trans_packet.PS_24_data[i] = 1; trans_packet.PS_48_1_data[i] = 1; trans_packet.PS_48_2_data[i] = 1; } trans_packet.IP_status[0] = t1++; trans_packet.IP_status[1] = t2++; trans_packet.IP_status[2] = t3++; trans_packet.OP_status[0] = t4++; trans_packet.OP_status[1] = t5++; trans_packet.link_trans_state = Healthy_Comm; // link trans_state healthy trans_packet.future_use = 0xFF; // Default Future Use Value trans_packet.checksum[0] = 0xFF; // dummy trans_packet.checksum[1] = Calculate_checksum(); trans_packet.EOF = 0xBB; // set the trans_state to start with trans_state = bytes_transmited_1; // Disable the Flag status_flag.Flag_RS232_Trans = CLEAR; // Enable UART TxE Interrupt USART_2.pUSARTx->USART_CR1 |= (1 << 7); // Enable transmission enable_transmission(); } #endif /* * UART Transmit Enable Function */ void enable_transmission() { // clear the time1, sending data at every 1 second //var.time1 = 0; // Enabling TxE bit in SR register USART_2.pUSARTx->USART_SR |= (1 << 7); } /* * Command Checksum Calculate Function */ #ifdef new_protocol int analog_checksum() { uint8_t temp, temp1; temp = analog[3]; // storing No of bytes in temp before shifting for (int i = 4; i < 39; i++) { temp1 = analog[i]; temp += temp1; temp <<= 1; } return (temp & 0xFF); // sending only 1 byte } int digital_checksum() { uint8_t temp, temp1; temp = digital[4]; // storing No of bytes in temp before shifting for (int i = 5; i < 11; i++) { temp1 = digital[i]; temp += temp1; temp <<= 1; } return (temp & 0xFF); // sending only 1 byte } #else int Calculate_checksum() { uint8_t temp, temp1; temp = t[4]; // storing No of bytes in temp before shifting for (int i = 5; i < 47; i++) { temp1 = t[i]; temp += temp1; temp <<= 1; } return (temp & 0xFF); // sending only 1 byte } #endif /* * ACK Checksum Calculate Function */ int ack_checksum_calculate() { uint8_t temp, temp1; temp = a[1]; for (int i = 2; i < 7; i++) { temp1 = a[i]; temp += temp1; temp <<= 1; } return (temp & 0xFF); // sending only 1 byte } /* void i2c_PS_read(uint8_t slave_addr, uint8_t pointer_addr, uint8_t *read_register_data) { switch(i2c_S) { case Start_Bit_SET_24: { // Start condition generation I2C3->CR1 |= (1 << 8); // checking SB bit in SR1 register if(I2C3->SR1 & 1) { // dummy read of SR1 register dummy = I2C3->SR1; //i2c_S = Send_Slave_Addr_Write_24; } break; } case Send_Slave_Addr_Write_24: { slave_addr <<= 1; // 1 left shift of Slave Address for Performing Write Operation // write slave address with write command I2C3->DR = slave_addr; // wait till ADDR bit is set if ((I2C3->SR1 >> 1) & 1) { // dummy read SR1 and SR2 dummy = I2C3->SR1; dummy = I2C3->SR2; i2c_S = Send_Mem_Addr_24; } break; } case Send_Mem_Addr_24: { // sending memory address I2C3->DR = pointer_addr; // sending address of pointer register signifying which register to read if(((I2C3->SR1 >> 7) & 1)) { i2c_S = BTF_24; } break; } case BTF_24: { if(((I2C3->SR1 >> 2) &1)) { i2c_S = ReStart_Bit_SET_24; } break; } case ReStart_Bit_SET_24: { // Start condition generation I2C3->CR1 |= (1 << 8); // checking SB bit in SR1 register if(I2C3->SR1 & 1) { // dummy read of SR1 register dummy = I2C3->SR1; i2c_S = Send_Slave_Addr_Read_24; } break; } case Send_Slave_Addr_Read_24: { slave_addr <<= 1; // 1 left shift of Slave Address for Performing Write Operation // write slave address with write command I2C3->DR = slave_addr | 1; // wait till ADDR bit is set if ((I2C3->SR1 >> 1) & 1) { // dummy read SR1 and SR2 dummy = I2C3->SR1; dummy = I2C3->SR2; i2c_S = NACK_24; } break; } case NACK_24: { // send a NACK by clearing the ACK bit I2C3->CR1 &= ~(1 << 10); // set POS high I2C3->CR1 |= (1 << 11); // dummy read SR1 and SR2 for clearing the ADDR bit dummy = I2C3->SR1; dummy = I2C3->SR2; i2c_S = BTF_R_24; break; } case BTF_R_24: { if(((I2C3->SR1 >> 2) &1)) { i2c_S = Read_data_24; } break; } case Read_data_24: { // check if RxNE bit is set or not if((I2C3->SR1 >> 6) & 1) { // read the data data = I2C3->DR; // check if RxNE bit is set or not if((I2C3->SR1 >> 6) & 1) { // read the data data1 = I2C3->DR; i2c_S = Stop_Condition_24; } } break; } case Stop_Condition_24: { // stop generation I2C3->CR1 |= (1 << 9); *read_register_data = data; read_register_data++; *read_register_data = data1; i2c_S = Start_Bit_SET_24; break; } } } */ /* * I2C Read Function For Power Supply */ void i2c_PS_read(uint8_t slave_addr, uint8_t read_register_addr, uint8_t *read_register_data) { uint8_t data, data1, dummy; slave_addr <<= 1; // 1 left shift of Slave Address for Performing Write Operation /* * last bit 0 : Write Operation * last bit 1 : Read Operation * * No Stop condition needed after the first write cycle, Power Supply responds to repeated start */ // Start condition generation I2C3->CR1 |= (1 << 8); // checking SB bit in SR1 register while(!(I2C3->SR1 & 1)); // dummy read of SR1 register dummy = I2C3->SR1; // write slave address with write command I2C3->DR = slave_addr; // wait till ADDR bit is set while(!((I2C3->SR1 >> 1) & 1)); // dummy read SR1 and SR2 dummy = I2C3->SR1; dummy = I2C3->SR2; // sending memory address I2C3->DR = read_register_addr; // sending address of pointer register signifying which register to read while(!((I2C3->SR1 >> 7) & 1)); // BTF while(!((I2C3->SR1 >> 2) &1)); // Start condition generation I2C3->CR1 |= (1 << 8); // checking SB bit in SR1 register while(!(I2C3->SR1 & 1)); // dummy read of SR1 register dummy = I2C3->SR1; // write slave address with read command slave_addr |= (1 << 0); I2C3->DR = slave_addr; // wait till ADDR bit is set while(!((I2C3->SR1 >> 1) & 1)); // send a NACK by clearing the ACK bit I2C3->CR1 &= ~(1 << 10); // set POS high I2C3->CR1 |= (1 << 11); // dummy read SR1 and SR2 for clearing the ADDR bit dummy = I2C3->SR1; dummy = I2C3->SR2; // BTF while(!((I2C3->SR1 >> 2) & 1)); // check if RxNE bit is set or not while(!((I2C3->SR1 >> 6) & 1)); // read the data data = I2C3->DR; // check if RxNE bit is set or not while(!((I2C3->SR1 >> 6) & 1)); // read the data data1 = I2C3->DR; // stop generation I2C3->CR1 |= (1 << 9); *read_register_data = data; read_register_data++; *read_register_data = data1; //*final = ((data1 << 8) + data); } void i2c_tmp_read(uint8_t slave_addr, uint8_t pointer_addr, uint8_t *temperature) { uint8_t data, data1, dummy; // Start condition generation I2C3->CR1 |= (1 << 8); // checking SB bit in SR1 register while(!(I2C3->SR1 & 1)); // dummy read of SR1 register dummy = I2C3->SR1; // write slave address with write command I2C3->DR = slave_addr; // wait till ADDR bit is set while(!((I2C3->SR1 >> 1) & 1)); // dummy read SR1 and SR2 dummy = I2C3->SR1; dummy = I2C3->SR2; // sending memory address I2C3->DR = pointer_addr; // sending address of pointer register signifying which register to read while(!((I2C3->SR1 >> 7) & 1)); // BTF while(!((I2C3->SR1 >> 2) &1)); // stop condition I2C3->CR1 |= (1 << 9); // Start condition generation I2C3->CR1 |= (1 << 8); // checking SB bit in SR1 register while(!(I2C3->SR1 & 1)); // dummy read of SR1 register dummy = I2C3->SR1; // write slave address with read command slave_addr |= (1 << 0); I2C3->DR = slave_addr; // wait till ADDR bit is set while(!((I2C3->SR1 >> 1) & 1)); // send a NACK by clearing the ACK bit I2C3->CR1 &= ~(1 << 10); // set POS high I2C3->CR1 |= (1 << 11); // dummy read SR1 and SR2 for clearing the ADDR bit dummy = I2C3->SR1; dummy = I2C3->SR2; // BTF while(!((I2C3->SR1 >> 2) & 1)); // check if RxNE bit is set or not while(!((I2C3->SR1 >> 6) & 1)); // read the data data = I2C3->DR; // check if RxNE bit is set or not while(!((I2C3->SR1 >> 6) & 1)); // read the data data1 = I2C3->DR; // stop generation I2C3->CR1 |= (1 << 9); *temperature = ((data1 << 8) + data); }