RCC configuration Master void RCC_Configuration(void)//72MHz(Master module) { RCC_DeInit(); RCC_ClearFlag(); RCC_HSEConfig(RCC_HSE_ON); FLASH->ACR|=FLASH_Latency_2; FLASH->ACR|=FLASH_PrefetchBuffer_Enable; RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_9); RCC_PCLK1Config(RCC_HCLK_Div2); RCC_PCLK2Config(RCC_HCLK_Div1); RCC_ADCCLKConfig(RCC_PCLK2_Div6); RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); RCC_PLLCmd(ENABLE); while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY)==RESET); while(RCC_WaitForHSEStartUp()==ERROR); } void RCC_Configuration(void)//8MHz(Master module) { RCC_DeInit(); RCC_ClearFlag(); RCC_HSEConfig(RCC_HSE_ON); FLASH->ACR|=FLASH_Latency_2; FLASH->ACR|=FLASH_PrefetchBuffer_Enable; RCC_PLLConfig(RCC_PLLSource_HSE_Div2,RCC_PLLMul_2); RCC_PCLK1Config(RCC_HCLK_Div2); RCC_PCLK2Config(RCC_HCLK_Div1); RCC_ADCCLKConfig(RCC_PCLK2_Div6); RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); RCC_PLLCmd(ENABLE); while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY)==RESET); while(RCC_WaitForHSEStartUp()==ERROR); } USART1 Configuration (Master) void USART_Configuration(void) { USART_InitTypeDef USART_InitStruct; USART_InitStruct.USART_BaudRate = 115200; USART_InitStruct.USART_WordLength = USART_WordLength_8b; USART_InitStruct.USART_StopBits = USART_StopBits_1; USART_InitStruct.USART_Parity = USART_Parity_No; USART_InitStruct.USART_Mode = USART_Mode_Tx|USART_Mode_Rx; USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_Init(USART1,&USART_InitStruct); USART_ITConfig(USART1, USART_IT_RXNE,ENABLE); USART_Cmd(USART1,ENABLE); // the alternate function and NVIC thing i have done } RCC configuration (Slave) #define __RCC_CFGR_VAL 0x00038402 #define __RCC_CR_VAL 0x01010082 void RCC_Configuration(void) { RCC->CFGR = __RCC_CFGR_VAL; // RCC->CR = __RCC_CR_VAL; // set clock control register if (__RCC_CR_VAL & RCC_CR_HSION) { // if HSI enabled while ((RCC->CR & RCC_CR_HSIRDY) == 0); // Wait for HSIRDY = 1 (HSI is ready) } if (__RCC_CR_VAL & RCC_CR_HSEON) { // if HSE enabled while ((RCC->CR & RCC_CR_HSERDY) == 0); // Wait for HSERDY = 1 (HSE is ready) } if (__RCC_CR_VAL & RCC_CR_PLLON) { // if PLL enabled while ((RCC->CR & RCC_CR_PLLRDY) == 0); // Wait for PLLRDY = 1 (PLL is ready) } /* Wait till SYSCLK is stabilized (depending on selected clock) */ while ((RCC->CFGR & RCC_CFGR_SWS) != ((__RCC_CFGR_VAL<<2) & RCC_CFGR_SWS)); } USART1 Configuration (Slave) void USART1_CONFIGURATION() { RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function AFIO->MAPR &= ~(1 << 2); // clear USART1 remap GPIOA->CRH &= 0xFFFFF00F; GPIOA->CRH |= 0x400; GPIOA->CRH |= 0xB0; RCC->APB2ENR |= RCC_APB2ENR_USART1EN; // enable clock for USART1 USART1->BRR = 0x45;//0x68;//0xD0;//0x271;//0xD0;//0X68;//0x8A;//0x1D4C;//0x271;//0x1D4C; //__USART_BRR(__PCLK2, __USART1_BAUDRATE); // set baudrate USART1->CR1 = __USART1_DATABITS; // set Data bits USART1->CR2 = __USART1_STOPBITS; // set Stop bits USART1->CR1 |= __USART1_PARITY; // set Parity USART1->CR3 = __USART1_FLOWCTRL; // Set Flow Control USART1->CR1 |= (USART_CR1_TE | USART_CR1_RE); // RX, TX enable USART1->CR1 |= USART_FLAG_RXNE; USART1->CR2 |= __USART1_CR2; USART1->CR3 |= __USART1_CR3; USART1->CR1 |= 0x00002000; NVIC->ISER[1] |= (1 << (0x25 & 0x1F)); // enable interrupt }