/* * stm32l47x.h * * Created on: Jul 17, 2023 * Author: 158593 */ #include "stdint.h" #ifndef INC_STM32L47X_H_ #define INC_STM32L47X_H_ #define __vo volatile /**********************************START:Processor Specific Details **********************************/ /* * ARM Cortex Mx Processor NVIC ISERx register Addresses */ #define NVIC_ISER0 ( (__vo uint32_t*)0xE000E100 ) #define NVIC_ISER1 ( (__vo uint32_t*)0xE000E104 ) #define NVIC_ISER2 ( (__vo uint32_t*)0xE000E108 ) #define NVIC_ISER3 ( (__vo uint32_t*)0xE000E10c ) /* * ARM Cortex Mx Processor NVIC ICERx register Addresses */ #define NVIC_ICER0 ((__vo uint32_t*)0XE000E180) #define NVIC_ICER1 ((__vo uint32_t*)0XE000E184) #define NVIC_ICER2 ((__vo uint32_t*)0XE000E188) #define NVIC_ICER3 ((__vo uint32_t*)0XE000E18C) /* * ARM Cortex Mx Processor Priority Register Address Calculation */ #define NVIC_PR_BASE_ADDR ((__vo uint32_t*)0xE000E400) /* * ARM Cortex Mx Processor number of priority bits implemented in Priority Register */ #define NO_PR_BITS_IMPLEMENTED 4 /* * Base addresses of Flash and SRAM memories */ #define FLASH_BASEADDR 0x00000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x10000000U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR /* * AHBx and APBx Bus Peripheral Base Addresses */ #define PERIPH_BASE 0x40000000U //Corresponds to TIM2_CR1 #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE 0x40010000U //Corresponds to SYSCNFG_MEMRMP #define AHB1PERIPH_BASE 0x40020000U //Corresponds to DMA_ISR #define AHB2PERIPH_BASE 0x48000000U // Corresponds to GPIOA_MODER #define RCC_BASEADDR (AHB1PERIPH_BASE + 0x1000) /* * Base Addresses of peripherals which are hanging on AHB1 Bus */ /* #define DMA1_BASEADDR (AHB1PERIPH_BASE + 0x0000) #define DMA2_BASEADDR (AHB1PERIPH_BASE + 0x0400) #define RCC_BASEADDR (AHB1PERIPH_BASE + 0x1000) #define FLASH_REG_BASEADDR (AHB1PERIPH_BASE + 0x2000) #define CRC_BASEADDR (AHB1PERIPH_BASE + 0x3000) #define TSC_BASEADDR (AHB1PERIPH_BASE + 0x4000) */ /* * Base Addresses of peripherals which are hanging on AHB2 Bus */ #define GPIOA_BASEADDR (AHB2PERIPH_BASE + 0x0000) #define GPIOB_BASEADDR (AHB2PERIPH_BASE + 0x0400) #define GPIOC_BASEADDR (AHB2PERIPH_BASE + 0x0800) #define GPIOD_BASEADDR (AHB2PERIPH_BASE + 0x0C00) #define GPIOE_BASEADDR (AHB2PERIPH_BASE + 0x1000) #define GPIOH_BASEADDR (AHB2PERIPH_BASE + 0x1C00) /* * Base Addresses of peripherals which are hanging on APB1 Bus */ #define TIM2_BASEADDR (APB1PERIPH_BASE + 0x0000) #define TIM3_BASEADDR (APB1PERIPH_BASE + 0x0400) #define TIM4_BASEADDR (APB1PERIPH_BASE + 0x0800) #define TIM5_BASEADDR (APB1PERIPH_BASE + 0x0C00) #define TIM6_BASEADDR (APB1PERIPH_BASE + 0x1000) #define TIM7_BASEADDR (APB1PERIPH_BASE + 0x1400) #define RTC_BASEADDR (APB1PERIPH_BASE + 0x2800) #define WWDG_BASEADDR (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASEADDR (APB1PERIPH_BASE + 0x3000) #define SPI2_BASEADDR (APB1PERIPH_BASE + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASE + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASE + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASE + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASE + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASE + 0x5000) #define I2C1_BASEADDR (APB1PERIPH_BASE + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASE + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASE + 0x5C00) #define CAN1_BASEADDR (APB1PERIPH_BASE + 0x6400) #define DAC1_BASEADDR (APB1PERIPH_BASE + 0x7400) #define OPAMP_BASEADDR (APB1PERIPH_BASE + 0x7800) #define LPTIM1_BASEADDR (APB1PERIPH_BASE + 0x7C00) #define LPUART1_BASEADDR (APB1PERIPH_BASE + 0x8000) #define SWPMI1_BASEADDR (APB1PERIPH_BASE + 0x8800) #define LPTIM2_BASEADDR (APB1PERIPH_BASE + 0x9400) /* * Base Addresses of peripherals which are hanging on APB2 Bus */ #define SYSCFG_BASEADDR (APB2PERIPH_BASE + 0x0000) #define VREFBUF_BASEADDR (APB2PERIPH_BASE + 0x0030) #define COMP_BASEADDR (APB2PERIPH_BASE + 0x0200) #define EXTI_BASEADDR (APB2PERIPH_BASE + 0x0400) #define FIREWALL_BASEADDR (APB2PERIPH_BASE + 0x1C00) #define SDMMC1_BASEADDR (APB2PERIPH_BASE + 0x2800) #define TIM1_BASEADDR (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASEADDR (APB2PERIPH_BASE + 0x3000) #define TIM8_BASEADDR (APB2PERIPH_BASE + 0x3400) #define USART1_BASEADDR (APB2PERIPH_BASE + 0x3800) #define TIM15_BASEADDR (APB2PERIPH_BASE + 0x4000) #define TIM16_BASEADDR (APB2PERIPH_BASE + 0x4400) #define TIM17_BASEADDR (APB2PERIPH_BASE + 0x4800) #define SAI1_BASEADDR (APB2PERIPH_BASE + 0x5400) #define SAI2_BASEADDR (APB2PERIPH_BASE + 0x5800) #define DFSDM1_BASEADDR (APB2PERIPH_BASE + 0x6000) /***************************Peripheral Register Definition Structure***************/ /* * Structure of GPIO Registers */ typedef struct { __vo uint32_t MODER; //GPIO port mode register __vo uint32_t OTYPER; //GPIO port output type register __vo uint32_t OSPEEDR; //GPIO port output speed register __vo uint32_t PUPDR; //GPIO port pull-up/pull-down register __vo uint32_t IDR; //GPIO port input data register __vo uint32_t ODR; //GPIO port output data register __vo uint32_t BSRR; //GPIO port bit set/reset register __vo uint32_t LCKR; //GPIO port configuration lock register __vo uint32_t AFR[2]; //AF[0] :GPIO alternate function low register ; AF[1] :GPIO alternate function high register __vo uint32_t BRR; //GPIO port bit reset register __vo uint32_t ASCR; //GPIO port analog switch control register }GPIO_RegDef_t; typedef struct { __vo uint32_t CR; //Address Offset 0x00 __vo uint32_t ICSCR; //Address Offset 0x04 __vo uint32_t CFGR; //Address Offset 0x08 __vo uint32_t PLLCFGR; //Address Offset 0x0C __vo uint32_t PLLSAI1CFGR; //Address Offset 0x10 __vo uint32_t PLLSAI2CFGR; //Address Offset 0x14 __vo uint32_t CIER; //Address Offset 0x18 __vo uint32_t CIFR; //Address Offset 0x1C __vo uint32_t CICR; //Address Offset 0x20 __vo uint32_t AHB1RSTR; //Address Offset 0x28 __vo uint32_t AHB2RSTR; //Address Offset 0x2C __vo uint32_t AHB3RSTR; //Address Offset 0x30 __vo uint32_t APB1RSTR1; //Address Offset 0x38 __vo uint32_t APB1RSTR2; //Address Offset 0x3C __vo uint32_t APB2RSTR; //Address Offset 0x40 __vo uint32_t AHB1ENR; //Address Offset 0x48 __vo uint32_t AHB2ENR; //Address Offset 0x4C __vo uint32_t AHB3ENR; //Address Offset 0x50 __vo uint32_t APB1ENR1; //Address Offset 0x58 __vo uint32_t APB1ENR2; //Address Offset 0x5C __vo uint32_t APB2ENR; //Address Offset 0x60 __vo uint32_t AHB1SMENR; //Address Offset 0x68 __vo uint32_t AHB2SMENR; //Address Offset 0x6C __vo uint32_t AHB3SMENR; //Address Offset 0x70 __vo uint32_t APB1SMENR1; //Address Offset 0x78 __vo uint32_t APB1SMENR2; //Address Offset 0x7C __vo uint32_t APB2SMENR; //Address Offset 0x80 __vo uint32_t CCIPR; //Address Offset 0x88 __vo uint32_t BDCR; //Address Offset 0x90 __vo uint32_t CSR; //Address Offset 0x94 }RCC_RegDef_t; /* * peripheral register definition structure for EXTI */ typedef struct { __vo uint32_t IMR[2]; /*!< Interrupt Mask Register :- IMR[0] Address offset: 0x00 ; IMR[1] Address offset :0x20*/ __vo uint32_t EMR[2]; /*!< Event Mask Register :- EMR[0] Address offset: 0x04 ; EMR[1] Address offset:0x24 */ __vo uint32_t RTSR[2]; /*!< Rising Trigger selection Register :- RTSR[0] Address offset: 0x08 ; RTSR[1] Address offset:0x28 */ __vo uint32_t FTSR[2]; /*!< Falling Trigger selection Register :- FTSR[0] Address offset: 0x0C ; FTSR[1] Address offset:0x2C */ __vo uint32_t SWIER[2]; /*!< Software Interrupt event Register :- SWIER[0] Address offset: 0x10 ; SWIER[1] Address offset:0x30 */ __vo uint32_t PR[2]; /*!< Pending Register :- PR[0] Address offset: 0x14 ; PR[1] Address offset: 0x34 */ }EXTI_RegDef_t; /* * peripheral register definition structure for SYSCFG */ typedef struct { __vo uint32_t MEMRMP; /* Address offset: 0x00 */ __vo uint32_t CFGR[2]; /*CFGR[0]: CFGR1 with Address offset: 0x04 ;CFGR[1]: CFGR2 with Address offset: 0x1C */ __vo uint32_t EXTICR[4]; /*EXTICR[0]:- EXTICR1 with Address offset: 0x08 ; EXTICR[1]:- EXTICR2 with Address offset: 0x0C ;EXTICR[2]:- EXTICR3 with Address offset: 0x10 ;EXTICR[3]:- EXTICR4 with Address offset :0x1C */ __vo uint32_t SCSR; /* Address offset: 0x18 */ __vo uint32_t SWPR; /* Address offset: 0x20 */ __vo uint32_t SKR; /* Address offset: 0x24 */ } SYSCFG_RegDef_t; /* * Peripheral Definitions (Peripheral Base addresses typecasted to xxx_RegDef_t) */ #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) /* * Clock Enable Macros for GPIOx peripherals */ #define GPIOA_PCLK_EN() (RCC->AHB2ENR |= (1 << 0)) #define GPIOB_PCLK_EN() (RCC->AHB2ENR |= (1 << 1)) #define GPIOC_PCLK_EN() (RCC->AHB2ENR |= (1 << 2)) #define GPIOD_PCLK_EN() (RCC->AHB2ENR |= (1 << 3)) #define GPIOE_PCLK_EN() (RCC->AHB2ENR |= (1 << 4)) #define GPIOH_PCLK_EN() (RCC->AHB2ENR |= (1 << 7)) /* * Clock Enable Macros for I2Cx Peripherals */ #define I2C1_PCLK_EN() (RCC->APB1ENR1 |= (1 << 21)) #define I2C2_PCLK_EN() (RCC->APB1ENR1 |= (1 << 22)) #define I2C3_PCLK_EN() (RCC->APB1ENR1 |= (1 << 23)) /* * Clock Enable Macros for SPIx Peripherals */ #define SPI1_PCLK_EN() (RCC->APB2ENR |= (1 << 12)) #define SPI2_PCLK_EN() (RCC->APB1ENR1 |= (1 << 14)) #define SPI3_PCLK_EN() (RCC->APB1ENR1 |= (1 << 15)) /* * Clock Enable Macros for USARTx Peripherals */ #define USART1_PCLK_EN() (RCC->APB2ENR |=(1 << 14)) #define USART2_PCLK_EN() (RCC->APB1ENR1 |=(1 << 17)) #define USART3_PCLK_EN() (RCC->APB1ENR1 |=(1 << 18)) /* * Clock Enable Macros for SYSCFG peripheral */ #define SYSCFG_PCLK_EN() (RCC->APB2ENR |= (1 << 0)) /* * Clock Disable Macros for GPIOx peripherals */ #define GPIOA_PCLK_DI() (RCC->AHB2ENR &= ~(1 << 0)) #define GPIOB_PCLK_DI() (RCC->AHB2ENR &= ~(1 << 1)) #define GPIOC_PCLK_DI() (RCC->AHB2ENR &= ~(1 << 2)) #define GPIOD_PCLK_DI() (RCC->AHB2ENR &= ~(1 << 3)) #define GPIOE_PCLK_DI() (RCC->AHB2ENR &= ~(1 << 4)) #define GPIOH_PCLK_DI() (RCC->AHB2ENR &= ~(1 << 7)) /* * Clock Disable Macros for I2Cx Peripherals */ #define I2C1_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 21)) #define I2C2_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 22)) #define I2C3_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 23)) /* *Clock Disable Macros for SPIx Peripherals */ #define SPI1_PCLK_DI() (RCC->APB2ENR &= ~(1 << 12)) #define SPI2_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 14)) #define SPI3_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 15)) /* *Clock Disable Macros for USARTx Peripherals */ #define USART1_PCLK_DI() (RCC->APB2ENR &= ~(1 << 14)) #define USART2_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 17)) #define USART3_PCLK_DI() (RCC->APB1ENR1 &= ~(1 << 18)) /* * Clock Disable Macros for SYSCFG Peripherals */ #define SYSCFG_PCLK_DI() (RCC->APB2ENR &= ~(1 << 0)) /*In my MCU model number STM32VGT6 series this feature is not available Kindly Configure according to your model*/ /* * Macros to reset GPIOx peripherals */ #define GPIOA_REG_RESET() do{ (RCC->AHB2RSTR |= (1 << 0)); (RCC->AHB2RSTR &= ~(1 << 0)); }while(0) #define GPIOB_REG_RESET() do{ (RCC->AHB2RSTR |= (1 << 1)); (RCC->AHB2RSTR &= ~(1 << 1)); }while(0) #define GPIOC_REG_RESET() do{ (RCC->AHB2RSTR |= (1 << 2)); (RCC->AHB2RSTR &= ~(1 << 2)); }while(0) #define GPIOD_REG_RESET() do{ (RCC->AHB2RSTR |= (1 << 3)); (RCC->AHB2RSTR &= ~(1 << 3)); }while(0) #define GPIOE_REG_RESET() do{ (RCC->AHB2RSTR |= (1 << 4)); (RCC->AHB2RSTR &= ~(1 << 4)); }while(0) #define GPIOH_REG_RESET() do{ (RCC->AHB2RSTR |= (1 << 7)); (RCC->AHB2RSTR &= ~(1 << 7)); }while(0) /* * returns port code for given GPIOx base address */ /* * This macro returns a code( between 0 to 7) for a given GPIO base address(x) */ #define GPIO_BASEADDR_TO_CODE(x) ( (x == GPIOA)?0:\ (x == GPIOB)?1:\ (x == GPIOC)?2:\ (x == GPIOD)?3:\ (x == GPIOE)?4:\ (x == GPIOH)?7:0) /* * IRQ(Interrupt Request) Numbers of STM32L47x MCU * NOTE: update these macros with valid values according to your MCU * TODO: You may complete this list for other peripherals */ #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Some generic Macros #define Enable 1 #define Disable 0 #define SET Enable #define RESET Disable #define GPIO_PIN_SET Enable #define GPIO_PIN_RESET Disable #include "stm32l47x_gpio_driver.h" #endif /* INC_STM32L47X_H_ */