// Read the IIS3DWB Chip ID register
  uint8_t c = MemsIIS3DWB_readByte(iis3dwb, IIS3DWB_WHO_AM_I);
  if (c != 0x7B) // check
  {
    return(false);
  }

  // reset IIS3DWB to start fresh
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_CTRL1_XL, 0x00); // set accel to power down mode
  uint8_t temp = MemsIIS3DWB_readByte(iis3dwb, IIS3DWB_CTRL3_C);
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_CTRL3_C, temp | 0x01); // Set bit 0 to 1 to reset IIS3DWB
  delay_us(1000);

// enable data ready interrupt on INT1
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_INT1_CTRL, 0x01);
  
   // enable pulsed (not latched) data ready interrupt    
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_COUNTER_BDR_REG1, 0x80);

  // enable block update (bit 6 = 1), auto-increment registers (bit 2 = 1)
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_CTRL3_C, 0x40 | 0x04);
  // by default, interrupts active HIGH, push pull 
  // (can be changed by writing to bits 5 and 4, resp to above register)

  //  mask data ready until filter settle complete (bit 3 == 1), disable I2C (bit 2 == 1)
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_CTRL4_C, 0x08 | 0x04);

   // set accel full scale and enable accel
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_CTRL1_XL, 0xA0 | iis3dwb->eIIS3DWBScale << 2);

  // High pass filter selection, comment out for full 6.3 kHz bandwidth
  // Set HPF to ODR/800 (bits 5 - 7 == 1), set HP Ref Mode (bit 4 == 1)
  // Set HP fast settle mode (bit 3 == 1), set filter select to 1 (bit 2 == 1)
//  writeByte(IIS3DWB_CTRL8_XL, 0xFC);  
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_CTRL8_XL, 0xEC);  // Don't set HP reference mode

  // fifo
  uint8_t fifo_mode = 0x06; // continouous mode
  fifo_size = 128;
    // FIFO size if 9 bits here stored in a 16-bit uint16_t, maximum is 0x01FF = 511
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_FIFO_CTRL1, (fifo_size & 0x00FF));        // write lowest 8 bits
  //writeByte(IIS3DWB_FIFO_CTRL2, 0x80 | (fifo_size & 0x0100) >> 8); // write highest of 9 bits to bit 0, enable stop on watermark (bit 7 == 1)
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_FIFO_CTRL2, (fifo_size & 0x0100) >> 8); // write highest of 9 bits to bit 0, do not stop on watermark (bit 7 == 0)
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_FIFO_CTRL3, 0x0A);                       // write to FIFO at 26667 Hz
// time stamp (bits 6-7 == 0) and temperature (bits 4 - 5 == 0) not stored in FIFO 
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_FIFO_CTRL4, fifo_mode);                   // select FIFO mode
  MemsIIS3DWB_writeByte(iis3dwb, IIS3DWB_INT1_CTRL, 0x08);                         // enable FIFO threshold interrupt on INT1