/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file           : main.c
  * @brief          : Main program body
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2025 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"

/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "commande.h"
/* USER CODE END Includes */

/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */

/* USER CODE END PTD */

/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */

/* Non-secure Vector table to jump to (internal Flash Bank2 here)             */
/* Caution: address must correspond to non-secure internal Flash where is     */
/*          mapped in the non-secure vector table                             */
#define VTOR_TABLE_NS_START_ADDR  0x08040000UL

/* USER CODE END PD */

/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
#define STATUS_ERROR 0xABABABAB
#define STATUS_SUCCESS 0xCDCDCDCD

/* SAU constants */
#define SAU_REGION_NOT_NSC (0x0UL)
#define SRAM_ADDR_SECURE_BIT_Pos 28U
#define SRAM_ADDR_SECURE_BIT_Mask (0x1U << SRAM_ADDR_SECURE_BIT_Pos)
/* MPU constants */
#define MPU_ARMV8M_ATTR_INNER_NON_CACHABLE_Pos (0x0U)
#define MPU_ARMV8M_ATTR_INNER_NON_CACHABLE_Msk (0x4U << MPU_ARMV8M_ATTR_INNER_NON_CACHABLE_Pos )
#define MPU_ARMV8M_ATTR_OUTER_NON_CACHABLE_Pos (0x4U)
#define MPU_ARMV8M_ATTR_OUTER_NON_CACHABLE_Msk (0x4U << MPU_ARMV8M_ATTR_OUTER_NON_CACHABLE_Pos )

#define MPU_ARMV8M_RW_ANY (MPU_RBAR_AP_Msk & (0x01U << MPU_RBAR_AP_Pos) )
#define MPU_ARMV8M_XN_Msk (MPU_RBAR_XN_Msk)
#define MPU_ARMV8M_X_Msk (MPU_RBAR_XN_Msk & (0x0U << MPU_RBAR_XN_Pos))
#define MPU_ARMV8M_NON_SH_Msk (MPU_RBAR_SH_Msk & (0x0U << MPU_RBAR_SH_Pos))
#define MPU_ARMV8M_RO_ANY_Msk (MPU_RBAR_AP_Msk & (0x3U << MPU_RBAR_AP_Pos))

#define EXIT_ON_ERROR( result, expected_result)\
  if( (result) != (expected_result) )\
  {\
    goto exit;\
  }
/* USER CODE END PM */

/* Private variables ---------------------------------------------------------*/

RNG_HandleTypeDef hrng;

CRYP_HandleTypeDef hcryp;

UART_HandleTypeDef huart1;

/* USER CODE BEGIN PV */

uint8_t rx_length = 0;           // Variable pour stocker la longueur des données reçues
uint8_t command_length=0;
uint8_t command[PLAINTEXT_SIZE];
uint8_t ok_command[] = "OK";  // Données à envoyer

/* USER CODE END PV */

/* Private function prototypes -----------------------------------------------*/
static void NonSecure_Init(void);
void SystemClock_Config(void);
static void SystemPower_Config(void);
static void MX_GPIO_Init(void);
static void MX_GTZC_S_Init(void);
static void MX_ICACHE_Init(void);
static void MX_SAU_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_RNG_Init(void);
static void MX_SAES_AES_Init(void);
/* USER CODE BEGIN PFP */
void initPeriph(void);
/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void waitforcommand(void){
	while (command_length == 0) {
		// Receive the command (a single byte)

		command_length = receive_command();

		if (command_length == 0) {
			// If the command has not been received, wait a bit before retrying
			HAL_Delay(1000);
		}
	}
    send_data(ok_command, sizeof(ok_command-1)); // Send "OK" via UART (without including the null-terminator '\0')
}

void initPeriph(void){
	MX_GPIO_Init();
	MX_ICACHE_Init();
	MX_SAU_Init();
	//MX_USART1_UART_Init();
	MX_RNG_Init();
	MX_SAES_AES_Init();

}



static uint32_t rswe_configureMPUContextNPriv(void)
{
	  uint32_t status = STATUS_ERROR;

	  SET_BIT(MPU->CTRL, (MPU_CTRL_PRIVDEFENA_Msk |  MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_ENABLE_Msk));
	  EXIT_ON_ERROR(MPU->CTRL, (MPU_CTRL_PRIVDEFENA_Msk |  MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_ENABLE_Msk));

	  /* First slot: User flash */
	  WRITE_REG(MPU->RNR, 1);
	  WRITE_REG(MPU->RBAR, (0x0C000000U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
	  WRITE_REG(MPU->RLAR, ((0x0C080000U & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));


	  /* Third slot: SRAM */
	  WRITE_REG(MPU->RNR, 3);
	  WRITE_REG(MPU->RBAR, (0x30000000U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
	  WRITE_REG(MPU->RLAR, ((0x30040000U & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));

	  //SRAM 4
	  WRITE_REG(MPU->RNR, 4);
	  WRITE_REG(MPU->RBAR, (0x38000000U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
	  WRITE_REG(MPU->RLAR, ((0x38004000U & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));

	  /* 4 slot: USART1 */
	  WRITE_REG(MPU->RNR, 2);
	  WRITE_REG(MPU->RBAR, (0x50013800U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
	  WRITE_REG(MPU->RLAR, ((0x50013BFFU & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));

	  //FLASH_NSC




	  __DSB();
	  __ISB();

	  /* EXIT_ON_ERROR means go to exit label
		  * this will cause to return early in case of error with status set to STATUS_ERROR */
		  EXIT_ON_ERROR(MPU->RBAR, (0x0C000000U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
		  EXIT_ON_ERROR(MPU->RLAR, ((0x0C080000U & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));

		  EXIT_ON_ERROR(MPU->RBAR, (0x30000000U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
		  EXIT_ON_ERROR(MPU->RLAR, ((0x30040000U & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));

		  EXIT_ON_ERROR(MPU->RBAR, (0x38000000U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
		  EXIT_ON_ERROR(MPU->RLAR, ((0x38004000U & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));

		  EXIT_ON_ERROR(MPU->RBAR, (0x50013800U & MPU_RBAR_BASE_Msk) | MPU_ARMV8M_RW_ANY);
		  EXIT_ON_ERROR(MPU->RLAR, ((0x50013BFFU & MPU_RLAR_LIMIT_Msk) | ((0x0U) << MPU_RLAR_AttrIndx_Pos) | MPU_RLAR_EN_Msk));
	  status = STATUS_SUCCESS;

	exit:
	  return status;
}

/* USER CODE END 0 */

/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
  /* SAU/IDAU, FPU and interrupts secure/non-secure allocation setup done */
/* in SystemInit() based on partition_ file's definitions. */

  /* USER CODE BEGIN 1 */

  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();

  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();

  /* Configure the System Power */
  SystemPower_Config();
  /* GTZC initialisation */
  MX_GTZC_S_Init();

  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */

  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */

  /*************** Setup and jump to non-secure *******************************/


  /* Non-secure software does not return, this code is not executed */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
    /* USER CODE END WHILE */

    /* USER CODE BEGIN 3 */
	  if((command[0]=='S')&&(command[1]=='U')){

		  uint32_t status = STATUS_ERROR;
    	  status = rswe_configureMPUContextNPriv();
    	  __set_CONTROL(__get_CONTROL() | 1U);
    	 //  __ISB();


	  }
	  command_length=0;
	  waitforcommand();
      if (command_length > 0) {
          // Use switch-case to process commands
          switch (command[0]) {  // Check the first character of the command
              case 'C':  // Command for encryption (starts with "C")

                  // Complete rx_buffer with zeros to reach 16 bytes
                  receive_and_Crypted();

                  break;

              case 'D':  // Command for decryption (starts with "D")

                  receive_and_Decrypted();
                  break;

              case 'R':
                  // send_data(ok_command, sizeof(ok_command-1));  // Send "OK" via UART (without including the null-terminator '\0')
                  NVIC_SystemReset();
              default:
                  // If the command is not recognized, send an error message
                  const char* error_msg = "Unknown command\n";
                  send_data((uint8_t*)error_msg, strlen(error_msg));
                  break;
          }
          // Reset rx_length and command_length after processing
          rx_length = 0;
          command_length = 0; // Reset command length as well
      }

  }
  /* USER CODE END 3 */
}

/**
  * @brief  Non-secure call function
  *         This function is responsible for Non-secure initialization and switch
  *         to non-secure state
  * @retval None
  */
static void NonSecure_Init(void)
{
  funcptr_NS NonSecure_ResetHandler;

  SCB_NS->VTOR = VTOR_TABLE_NS_START_ADDR;

  /* Set non-secure main stack (MSP_NS) */
  __TZ_set_MSP_NS((*(uint32_t *)VTOR_TABLE_NS_START_ADDR));

  /* Get non-secure reset handler */
  NonSecure_ResetHandler = (funcptr_NS)(*((uint32_t *)((VTOR_TABLE_NS_START_ADDR) + 4U)));

  /* Start non-secure state software application */
  NonSecure_ResetHandler();
}

/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE3) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_MSI
                              |RCC_OSCILLATORTYPE_SHSI;
  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4;
  RCC_OscInitStruct.SHSIState = RCC_SHSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_PCLK3;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
  {
    Error_Handler();
  }
}

/**
  * @brief Power Configuration
  * @retval None
  */
static void SystemPower_Config(void)
{

  /*
   * Switch to SMPS regulator instead of LDO
   */
  if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK)
  {
    Error_Handler();
  }
/* USER CODE BEGIN PWR */
/* USER CODE END PWR */
}

/**
  * @brief GTZC_S Initialization Function
  * @param None
  * @retval None
  */
static void MX_GTZC_S_Init(void)
{

  /* USER CODE BEGIN GTZC_S_Init 0 */
	uint8_t nsecure='0';
  /* USER CODE END GTZC_S_Init 0 */

  MPCBB_ConfigTypeDef MPCBB_Area_Desc = {0};

  /* USERd CODE BEGIN GTZC_S_Init 1 */

  /* USER CODE END GTZC_S_Init 1 */
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_USART1, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_PRIV) != HAL_OK)
  {
    Error_Handler();
  }
  MX_USART1_UART_Init();




  waitforcommand();
  if((command[0]=='S')&&(command[1]=='P')){

	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_RNG, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_PRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_SAES, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_PRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  initPeriph();

  }
  if((command[0]=='S')&&(command[1]=='U')){
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_RNG, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_SAES, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_USART1, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  initPeriph();

  }
  if((command[0]=='N')&&(command[1]=='S')&&(command[2]=='P')){
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_RNG, GTZC_TZSC_PERIPH_NSEC|GTZC_TZSC_PERIPH_PRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_SAES, GTZC_TZSC_PERIPH_NSEC|GTZC_TZSC_PERIPH_PRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  initPeriph();
	  nsecure='N';



  }
  if((command[0]=='N')&&(command[1]=='S')&&(command[2]=='U')){
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_RNG, GTZC_TZSC_PERIPH_NSEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_SAES, GTZC_TZSC_PERIPH_NSEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
	  {
	    Error_Handler();
	  }
	  initPeriph();
	  nsecure='N';



  }

  MPCBB_Area_Desc.SecureRWIllegalMode = GTZC_MPCBB_SRWILADIS_ENABLE;
  MPCBB_Area_Desc.InvertSecureState = GTZC_MPCBB_INVSECSTATE_NOT_INVERTED;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[0] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[1] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[2] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[3] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_LockConfig_array[0] =   0x00000000;
  if (HAL_GTZC_MPCBB_ConfigMem(SRAM2_BASE, &MPCBB_Area_Desc) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN GTZC_S_Init 2 */
	if(nsecure=='N'){
		NonSecure_Init();
	}
  /* USER CODE END GTZC_S_Init 2 */

}

/**
  * @brief ICACHE Initialization Function
  * @param None
  * @retval None
  */
static void MX_ICACHE_Init(void)
{

  /* USER CODE BEGIN ICACHE_Init 0 */

  /* USER CODE END ICACHE_Init 0 */

  /* USER CODE BEGIN ICACHE_Init 1 */

  /* USER CODE END ICACHE_Init 1 */

  /** Enable instruction cache in 1-way (direct mapped cache)
  */
  if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_ICACHE_Enable() != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN ICACHE_Init 2 */

  /* USER CODE END ICACHE_Init 2 */

}

/**
  * @brief RNG Initialization Function
  * @param None
  * @retval None
  */
static void MX_RNG_Init(void)
{

  /* USER CODE BEGIN RNG_Init 0 */

  /* USER CODE END RNG_Init 0 */

  /* USER CODE BEGIN RNG_Init 1 */

  /* USER CODE END RNG_Init 1 */
  hrng.Instance = RNG;
  hrng.Init.ClockErrorDetection = RNG_CED_ENABLE;
  if (HAL_RNG_Init(&hrng) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN RNG_Init 2 */

  /* USER CODE END RNG_Init 2 */

}

/**
  * @brief SAES Initialization Function
  * @param None
  * @retval None
  */
static void MX_SAES_AES_Init(void)
{

  /* USER CODE BEGIN SAES_Init 0 */

  /* USER CODE END SAES_Init 0 */

  /* USER CODE BEGIN SAES_Init 1 */

  /* USER CODE END SAES_Init 1 */
  hcryp.Instance = SAES;
  hcryp.Init.DataType = CRYP_NO_SWAP;
  hcryp.Init.KeySize = CRYP_KEYSIZE_256B;
  hcryp.Init.Algorithm = CRYP_AES_ECB;
  hcryp.Init.KeyIVConfigSkip = CRYP_KEYIVCONFIG_ALWAYS;
  hcryp.Init.KeyMode = CRYP_KEYMODE_NORMAL;
  hcryp.Init.KeySelect = CRYP_KEYSEL_HW;
  hcryp.Init.KeyProtection = CRYP_KEYPROT_DISABLE;
  if (HAL_CRYP_Init(&hcryp) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN SAES_Init 2 */

  /* USER CODE END SAES_Init 2 */

}

/**
  * @brief SAU Initialization Function
  * @param None
  * @retval None
  */
static void MX_SAU_Init(void)
{

  /* USER CODE BEGIN SAU_Init 0 */

  /* USER CODE END SAU_Init 0 */

  /* USER CODE BEGIN SAU_Init 1 */

  /* USER CODE END SAU_Init 1 */
  /* USER CODE BEGIN SAU_Init 2 */

  /* USER CODE END SAU_Init 2 */

}

/**
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{

  /* USER CODE BEGIN USART1_Init 0 */

  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
  huart1.Init.BaudRate = 115200;
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
  huart1.Init.StopBits = UART_STOPBITS_1;
  huart1.Init.Parity = UART_PARITY_NONE;
  huart1.Init.Mode = UART_MODE_TX_RX;
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
  if (HAL_UART_Init(&huart1) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}

/**
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();

  /*IO attributes management functions */
  HAL_GPIO_ConfigPinAttributes(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin, GPIO_PIN_NSEC);

  /*IO attributes management functions */
  HAL_GPIO_ConfigPinAttributes(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_NSEC);

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}

/* USER CODE BEGIN 4 */

/* USER CODE END 4 */

/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
  {
  }
  /* USER CODE END Error_Handler_Debug */
}

#ifdef  USE_FULL_ASSERT
/**
  * @brief  Reports the name of the source file and the source line number
  *         where the assert_param error has occurred.
  * @param  file: pointer to the source file name
  * @param  line: assert_param error line source number
  * @retval None
  */
void assert_failed(uint8_t *file, uint32_t line)
{
  /* USER CODE BEGIN 6 */
  /* User can add his own implementation to report the file name and line number,
     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
  /* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */