/**
  ******************************************************************************
  * @file    stm32h7s3xx.h
  * @author  MCD Application Team
  * @brief   CMSIS STM32H7S3xx Device Peripheral Access Layer Header File.
  *
  *          This file contains:
  *           - Data structures and the address mapping for all peripherals
  *           - Peripheral's registers declarations and bits definition
  *           - Macros to access peripheral's registers hardware
  *
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2022 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

#ifndef STM32H7S3xx_H
#define STM32H7S3xx_H

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/** @addtogroup ST
  * @{
  */


/** @addtogroup STM32H7S3xx
  * @{
  */


/** @addtogroup Configuration_of_CMSIS
  * @{
  */


/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum
{
/* =======================================  ARM Cortex-M7 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                 = -15,    /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn        = -14,    /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn             = -13,    /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn      = -12,    /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                 and No Match                                                         */
  BusFault_IRQn              = -11,    /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                 related Fault                                                        */
  UsageFault_IRQn            = -10,    /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn                =  -5,    /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn          =  -4,    /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn                =  -2,    /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn               =  -1,    /*!< -1 System Tick Timer                                                      */

/* ===========================================  STM32H7S3xx Specific Interrupt Numbers  ====================================== */
  PVD_PVM_IRQn               = 0,      /*!< PVD/PVM through EXTI Line detection                              */
  DTS_IRQn                   = 2,      /*!< Digital Temperature Sensor interrupt                             */
  IWDG_IRQn                  = 3,      /*!< Internal Watchdog interrupt                                      */
  WWDG_IRQn                  = 4,      /*!< Window Watchdog interrupt                                        */
  RCC_IRQn                   = 5,      /*!< RCC global interrupts through EXTI Line detection                */
  FLASH_IRQn                 = 8,      /*!< FLASH interrupts                                                 */
  RAMECC_IRQn                = 9,      /*!< RAMECC interrupts                                                */
  FPU_IRQn                   = 10,     /*!< FPU interrupt                                                    */
  TAMP_IRQn                  = 13,     /*!< Tamper and TimeStamp interrupts through EXTI Line detection      */
  EXTI0_IRQn                 = 16,     /*!< EXTI Line0 interrupt                                             */
  EXTI1_IRQn                 = 17,     /*!< EXTI Line1 interrupt                                             */
  EXTI2_IRQn                 = 18,     /*!< EXTI Line2 interrupt                                             */
  EXTI3_IRQn                 = 19,     /*!< EXTI Line3 interrupt                                             */
  EXTI4_IRQn                 = 20,     /*!< EXTI Line4 interrupt                                             */
  EXTI5_IRQn                 = 21,     /*!< EXTI Line5 interrupt                                             */
  EXTI6_IRQn                 = 22,     /*!< EXTI Line6 interrupt                                             */
  EXTI7_IRQn                 = 23,     /*!< EXTI Line7 interrupt                                             */
  EXTI8_IRQn                 = 24,     /*!< EXTI Line8 interrupt                                             */
  EXTI9_IRQn                 = 25,     /*!< EXTI Line9 interrupt                                             */
  EXTI10_IRQn                = 26,     /*!< EXTI Line10 interrupt                                            */
  EXTI11_IRQn                = 27,     /*!< EXTI Line11 interrupt                                            */
  EXTI12_IRQn                = 28,     /*!< EXTI Line12 interrupt                                            */
  EXTI13_IRQn                = 29,     /*!< EXTI Line13 interrupt                                            */
  EXTI14_IRQn                = 30,     /*!< EXTI Line14 interrupt                                            */
  EXTI15_IRQn                = 31,     /*!< EXTI Line15 interrupt                                            */
  RTC_IRQn                   = 32,     /*!< RTC Wakeup and Alarm interrupts through EXTI Line detection      */
  SAES_IRQn                  = 33,     /*!< SAES interrupt                                                   */
  CRYP_IRQn                  = 34,     /*!< CRYP interrupt                                                   */
  PKA_IRQn                   = 35,     /*!< PKA interrupt                                                    */
  HASH_IRQn                  = 36,     /*!< HASH interrupt                                                   */
  RNG_IRQn                   = 37,     /*!< RNG global interrupt                                             */
  ADC1_2_IRQn                = 38,     /*!< ADC1 & ADC2 interrupt                                            */
  GPDMA1_Channel0_IRQn       = 39,     /*!< GPDMA1 Channel 0 interrupt                                       */
  GPDMA1_Channel1_IRQn       = 40,     /*!< GPDMA1 Channel 1 interrupt                                       */
  GPDMA1_Channel2_IRQn       = 41,     /*!< GPDMA1 Channel 2 interrupt                                       */
  GPDMA1_Channel3_IRQn       = 42,     /*!< GPDMA1 Channel 3 interrupt                                       */
  GPDMA1_Channel4_IRQn       = 43,     /*!< GPDMA1 Channel 4 interrupt                                       */
  GPDMA1_Channel5_IRQn       = 44,     /*!< GPDMA1 Channel 5 interrupt                                       */
  GPDMA1_Channel6_IRQn       = 45,     /*!< GPDMA1 Channel 6 interrupt                                       */
  GPDMA1_Channel7_IRQn       = 46,     /*!< GPDMA1 Channel 7 interrupt                                       */
  TIM1_BRK_IRQn              = 47,     /*!< TIM1 Break interrupt                                             */
  TIM1_UP_IRQn               = 48,     /*!< TIM1 Update interrupt                                            */
  TIM1_TRG_COM_IRQn          = 49,     /*!< TIM1 Trigger and Commutation interrupt                           */
  TIM1_CC_IRQn               = 50,     /*!< TIM1 Capture Compare interrupt                                   */
  TIM2_IRQn                  = 51,     /*!< TIM2 global interrupt                                            */
  TIM3_IRQn                  = 52,     /*!< TIM3 global interrupt                                            */
  TIM4_IRQn                  = 53,     /*!< TIM4 global interrupt                                            */
  TIM5_IRQn                  = 54,     /*!< TIM5 global interrupt                                            */
  TIM6_IRQn                  = 55,     /*!< TIM6 global interrupt                                            */
  TIM7_IRQn                  = 56,     /*!< TIM7 global interrupt                                            */
  TIM9_IRQn                  = 57,     /*!< TIM9 global interrupt                                            */
  SPI1_IRQn                  = 58,     /*!< SPI1 global interrupt                                            */
  SPI2_IRQn                  = 59,     /*!< SPI2 global interrupt                                            */
  SPI3_IRQn                  = 60,     /*!< SPI3 global interrupt                                            */
  SPI4_IRQn                  = 61,     /*!< SPI4 global interrupt                                            */
  SPI5_IRQn                  = 62,     /*!< SPI5 global interrupt                                            */
  SPI6_IRQn                  = 63,     /*!< SPI6 global interrupt                                            */
  HPDMA1_Channel0_IRQn       = 64,     /*!< HPDMA1 Channel 0 global interrupt                                */
  HPDMA1_Channel1_IRQn       = 65,     /*!< HPDMA1 Channel 1 global interrupt                                */
  HPDMA1_Channel2_IRQn       = 66,     /*!< HPDMA1 Channel 2 global interrupt                                */
  HPDMA1_Channel3_IRQn       = 67,     /*!< HPDMA1 Channel 3 global interrupt                                */
  HPDMA1_Channel4_IRQn       = 68,     /*!< HPDMA1 Channel 4 global interrupt                                */
  HPDMA1_Channel5_IRQn       = 69,     /*!< HPDMA1 Channel 5 global interrupt                                */
  HPDMA1_Channel6_IRQn       = 70,     /*!< HPDMA1 Channel 6 global interrupt                                */
  HPDMA1_Channel7_IRQn       = 71,     /*!< HPDMA1 Channel 7 global interrupt                                */
  SAI1_A_IRQn                = 72,     /*!< Serial Audio Interface 1 block A interrupt                       */
  SAI1_B_IRQn                = 73,     /*!< Serial Audio Interface 1 block B interrupt                       */
  SAI2_A_IRQn                = 74,     /*!< Serial Audio Interface 2 block A interrupt                       */
  SAI2_B_IRQn                = 75,     /*!< Serial Audio Interface 2 block B interrupt                       */
  I2C1_EV_IRQn               = 76,     /*!< I2C1 event interrupt                                             */
  I2C1_ER_IRQn               = 77,     /*!< I2C1 error interrupt                                             */
  I2C2_EV_IRQn               = 78,     /*!< I2C2 event interrupt                                             */
  I2C2_ER_IRQn               = 79,     /*!< I2C2 error interrupt                                             */
  I2C3_EV_IRQn               = 80,     /*!< I2C3 event interrupt                                             */
  I2C3_ER_IRQn               = 81,     /*!< I2C3 error interrupt                                             */
  USART1_IRQn                = 82,     /*!< USART1 global interrupt                                          */
  USART2_IRQn                = 83,     /*!< USART2 global interrupt                                          */
  USART3_IRQn                = 84,     /*!< USART3 global interrupt                                          */
  UART4_IRQn                 = 85,     /*!< UART4 global interrupt                                           */
  UART5_IRQn                 = 86,     /*!< UART5 global interrupt                                           */
  UART7_IRQn                 = 87,     /*!< UART7 global interrupt                                           */
  UART8_IRQn                 = 88,     /*!< UART8 global interrupt                                           */
  I3C1_EV_IRQn               = 89,     /*!< I3C1 event interrupt                                             */
  I3C1_ER_IRQn               = 90,     /*!< I3C1 error interrupt                                             */
  OTG_HS_IRQn                = 91,     /*!< USB OTG HS interrupt                                             */
  ETH_IRQn                   = 92,     /*!< Ethernet global interrupt                                        */
  CORDIC_IRQn                = 93,     /*!< CORDIC global interrupt                                          */
  GFXTIM_IRQn                = 94,     /*!< GFXTIM global interrupt                                          */
  DCMIPP_IRQn                = 95,     /*!< DCMIPP global interrupt                                          */
  DMA2D_IRQn                 = 98,     /*!< DMA2D global interrupt                                           */
  JPEG_IRQn                  = 99,     /*!< JPEG global interrupt                                            */
  GFXMMU_IRQn                = 100,    /*!< GFXMMU global interrupt                                          */
  I3C1_WKUP_IRQn             = 101,    /*!< I3C1 wakeup global interrupt                                     */
  MCE1_IRQn                  = 102,    /*!< MCE1 global interrupt                                            */
  MCE2_IRQn                  = 103,    /*!< MCE2 global interrupt                                            */
  MCE3_IRQn                  = 104,    /*!< MCE3 global interrupt                                            */
  XSPI1_IRQn                 = 105,    /*!< XSPI1 global interrupt                                           */
  XSPI2_IRQn                 = 106,    /*!< XSPI2 global interrupt                                           */
  FMC_IRQn                   = 107,    /*!< FMC global interrupt                                             */
  SDMMC1_IRQn                = 108,    /*!< SDMMC1 global interrupt                                          */
  SDMMC2_IRQn                = 109,    /*!< SDMMC2 global interrupt                                          */
  OTG_FS_IRQn                = 112,    /*!< USB OTG FS interrupt                                             */
  TIM12_IRQn                 = 113,    /*!< TIM12 global interrupt                                           */
  TIM13_IRQn                 = 114,    /*!< TIM13 global interrupt                                           */
  TIM14_IRQn                 = 115,    /*!< TIM14 global interrupt                                           */
  TIM15_IRQn                 = 116,    /*!< TIM15 global interrupt                                           */
  TIM16_IRQn                 = 117,    /*!< TIM16 global interrupt                                           */
  TIM17_IRQn                 = 118,    /*!< TIM17 global interrupt                                           */
  LPTIM1_IRQn                = 119,    /*!< LPTIM1 global interrupt                                          */
  LPTIM2_IRQn                = 120,    /*!< LPTIM2 global interrupt                                          */
  LPTIM3_IRQn                = 121,    /*!< LPTIM3 global interrupt                                          */
  LPTIM4_IRQn                = 122,    /*!< LPTIM4 global interrupt                                          */
  LPTIM5_IRQn                = 123,    /*!< LPTIM5 global interrupt                                          */
  SPDIF_RX_IRQn              = 124,    /*!< SPDIF_RX global interrupt                                        */
  MDIOS_IRQn                 = 125,    /*!< MDIOS global interrupt                                           */
  ADF1_FLT0_IRQn             = 126,    /*!< ADF1 Filter 0 global Interrupt                                   */
  CRS_IRQn                   = 127,    /*!< CRS global interrupt                                             */
  UCPD1_IRQn                 = 128,    /*!< UCPD1 global interrupt                                           */
  CEC_IRQn                   = 129,    /*!< HDMI_CEC global Interrupt                                        */
  PSSI_IRQn                  = 130,    /*!< PSSI global interrupt                                            */
  LPUART1_IRQn               = 131,    /*!< LPUART1 global interrupt                                         */
  WAKEUP_PIN_IRQn            = 132,    /*!< Wake-up pins interrupt                                           */
  GPDMA1_Channel8_IRQn       = 133,    /*!< GPDMA1 Channel 8 global interrupt                                */
  GPDMA1_Channel9_IRQn       = 134,    /*!< GPDMA1 Channel 9 global interrupt                                */
  GPDMA1_Channel10_IRQn      = 135,    /*!< GPDMA1 Channel 10 global interrupt                               */
  GPDMA1_Channel11_IRQn      = 136,    /*!< GPDMA1 Channel 11 global interrupt                               */
  GPDMA1_Channel12_IRQn      = 137,    /*!< GPDMA1 Channel 12 global interrupt                               */
  GPDMA1_Channel13_IRQn      = 138,    /*!< GPDMA1 Channel 13 global interrupt                               */
  GPDMA1_Channel14_IRQn      = 139,    /*!< GPDMA1 Channel 14 global interrupt                               */
  GPDMA1_Channel15_IRQn      = 140,    /*!< GPDMA1 Channel 15 global interrupt                               */
  HPDMA1_Channel8_IRQn       = 141,    /*!< HPDMA1 Channel 8 global interrupt                                */
  HPDMA1_Channel9_IRQn       = 142,    /*!< HPDMA1 Channel 9 global interrupt                                */
  HPDMA1_Channel10_IRQn      = 143,    /*!< HPDMA1 Channel 10 global interrupt                               */
  HPDMA1_Channel11_IRQn      = 144,    /*!< HPDMA1 Channel 11 global interrupt                               */
  HPDMA1_Channel12_IRQn      = 145,    /*!< HPDMA1 Channel 12 global interrupt                               */
  HPDMA1_Channel13_IRQn      = 146,    /*!< HPDMA1 Channel 13 global interrupt                               */
  HPDMA1_Channel14_IRQn      = 147,    /*!< HPDMA1 Channel 14 global interrupt                               */
  HPDMA1_Channel15_IRQn      = 148,    /*!< HPDMA1 Channel 15 global interrupt                               */
  FDCAN1_IT0_IRQn            = 152,    /*!< FDCAN1 interrupt 0                                               */
  FDCAN1_IT1_IRQn            = 153,    /*!< FDCAN1 interrupt 1                                               */
  FDCAN2_IT0_IRQn            = 154,    /*!< FDCAN2 interrupt 0                                               */
  FDCAN2_IT1_IRQn            = 155     /*!< FDCAN2 interrupt 1                                               */
} IRQn_Type;


/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/**
  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
   */
#define __CM7_REV                 0x0102U /*!< Cortex-M7 revision r1p2                       */
#define __MPU_PRESENT             1U      /*!< CM7 provides an MPU                           */
#define __MPU_REGIONCOUNT        16U      /*!< CM7 provides MPU region number                */
#define __NVIC_PRIO_BITS          4U      /*!< CM7 uses 4 Bits for the Priority Levels       */
#define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used  */
#define __FPU_PRESENT             1U      /*!< FPU present                                   */
#define __ICACHE_PRESENT          1U      /*!< CM7 instruction cache present                 */
#define __DCACHE_PRESENT          1U      /*!< CM7 data cache present                        */

/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm7.h>                     /*!< ARM Cortex-M7 processor and core peripherals  */
#include "system_stm32h7rsxx.h"             /*!< STM32H7RSxx System */


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup STM32H7RSxx_peripherals
  * @{
  */

/**
  * @brief Analog to Digital Converter
  */

typedef struct
{
  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
       uint32_t RESERVED10[4];/*!< Reserved,                                             0x0B8 - 0x0BC */
  __IO uint32_t OR;           /*!< ADC option register,                           Address offset: 0xC8 */
} ADC_TypeDef;

typedef struct
{
  __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
  uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
  __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
  __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;

/**
  * @brief AXIM ASIB
  */
typedef struct
{
  uint32_t RESERVED1[9];       /*!< Reserved,                             Address offset: 0x00-0x20 */
  __IO uint32_t FNMOD2;        /*!< AXIM ASIB fn_mod2 register            Address offset: 0x24 */
  uint32_t RESERVED3[54];      /*!< Reserved,                             Address offset: 0x28-0xFC */
  __IO uint32_t READQOS;       /*!< AXIM ASIB read_qos register           Address offset: 0x100 */
  __IO uint32_t WRITEQOS;      /*!< AXIM ASIB write_qos register          Address offset: 0x104 */
  __IO uint32_t FNMOD;         /*!< AXIM ASIB fn_mod register             Address offset: 0x108 */
} AXIM_ASIB_TypeDef;

typedef struct
{
  uint32_t RESERVED1[2];       /*!< Reserved,                             Address offset: 0x00-0x04 */
  __IO uint32_t FNMODBMISS;    /*!< AXIM AMIB fn_mod_bm_iss register      Address offset: 0x08 */
  uint32_t RESERVED2[6];       /*!< Reserved,                             Address offset: 0x0C-0x20 */
  __IO uint32_t FNMOD2;        /*!< AXIM AMIB fn_mod2 register            Address offset: 0x24 */
  uint32_t RESERVED3[1];       /*!< Reserved,                             Address offset: 0x28 */
  __IO uint32_t FNMODLB;       /*!< AXIM AMIB fn_mod_lb register          Address offset: 0x2C */
  uint32_t RESERVED5[54];      /*!< Reserved,                             Address offset: 0x30-0x104 */
  __IO uint32_t FNMOD;         /*!< AXIM AMIB fn_mod register             Address offset: 0x108 */
} AXIM_AMIB_TypeDef;

/**
  * @brief VREFBUF
  */

typedef struct
{
  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
} VREFBUF_TypeDef;

/**
  * @brief Consumer Electronics Control
  */

typedef struct
{
  __IO uint32_t CR;            /*!< CEC control register,                           Address offset:0x00 */
  __IO uint32_t CFGR;          /*!< CEC configuration register,                     Address offset:0x04 */
  __IO uint32_t TXDR;          /*!< CEC Tx data register ,                          Address offset:0x08 */
  __IO uint32_t RXDR;          /*!< CEC Rx Data Register,                           Address offset:0x0C */
  __IO uint32_t ISR;           /*!< CEC Interrupt and Status Register,              Address offset:0x10 */
  __IO uint32_t IER;           /*!< CEC interrupt enable register,                  Address offset:0x14 */
} CEC_TypeDef;

/**
  * @brief CORDIC
  */
typedef struct
{
  __IO uint32_t CSR;           /*!< CORDIC Control and Status register,             Address offset: 0x00 */
  __IO uint32_t WDATA;         /*!< CORDIC argument register,                       Address offset: 0x04 */
  __IO uint32_t RDATA;         /*!< CORDIC result register,                         Address offset: 0x08 */
} CORDIC_TypeDef;

/**
  * @brief GFXTIM
  */
typedef struct
{
  __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
  __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
  __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
  __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
  __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
  __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
  uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
  __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
  uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
  __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
  __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
  __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
  __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
  __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
  __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
  uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
  __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
  __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
  __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
  uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
  __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
  uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
  __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
  __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
  uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
  __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
  __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
  __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
  __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
  uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
  __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
  __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
  __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
  uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
  __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
  __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
  __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
  __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
} GFXTIM_TypeDef;


/**
  * @brief CRC calculation unit
  */
typedef struct
{
  __IO uint32_t DR;            /*!< CRC Data register,                              Address offset: 0x00 */
  __IO uint32_t IDR;           /*!< CRC Independent data register,                  Address offset: 0x04 */
  __IO uint32_t CR;            /*!< CRC Control register,                           Address offset: 0x08 */
       uint32_t RESERVED1;     /*!< Reserved,                                                       0x0C */
  __IO uint32_t INIT;          /*!< Initial CRC value register,                     Address offset: 0x10 */
  __IO uint32_t POL;           /*!< CRC polynomial register,                        Address offset: 0x14 */
} CRC_TypeDef;

/**
  * @brief Clock Recovery System
  */
typedef struct
{
  __IO uint32_t CR;            /*!< CRS ccontrol register,                          Address offset: 0x00 */
  __IO uint32_t CFGR;          /*!< CRS configuration register,                     Address offset: 0x04 */
  __IO uint32_t ISR;           /*!< CRS interrupt and status register,              Address offset: 0x08 */
  __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,              Address offset: 0x0C */
} CRS_TypeDef;

/**
  * @brief Cryp Processor
  */
typedef struct
{
  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
  __IO uint32_t DIN;        /*!< CRYP data input register,                                 Address offset: 0x08 */
  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
} CRYP_TypeDef;

/**
  * @brief Debug MCU
  */
typedef struct
{
  __IO uint32_t IDCODE;        /*!< MCU device ID code,                             Address offset: 0x00 */
  __IO uint32_t CR;            /*!< Debug MCU configuration register,               Address offset: 0x04 */
  uint32_t RESERVED1[5];       /*!< Reserved,                                       Address offset: 0x08-0x18 */
  __IO uint32_t AHB5FZR;       /*!< Debug MCU AHB5FZR freeze register,              Address offset: 0x1C */
  uint32_t RESERVED2;          /*!< Reserved,                                       Address offset: 0x20 */
  __IO uint32_t AHB1FZR;       /*!< Debug MCU AHB1FZR freeze register,              Address offset: 0x24 */
  uint32_t RESERVED3[5];       /*!< Reserved,                                       Address offset: 0x28-0x38 */
  __IO uint32_t APB1FZR;       /*!< Debug MCU APB1FZR freeze register,              Address offset: 0x3C */
  uint32_t RESERVED4[3];       /*!< Reserved,                                       Address offset: 0x40-0x48 */
  __IO uint32_t APB2FZR;       /*!< Debug MCU APB2FZR freeze register,              Address offset: 0x4C */
  uint32_t RESERVED5;          /*!< Reserved,                                       Address offset: 0x50 */
  __IO uint32_t APB4FZR;       /*!< Debug MCU APB4FZR freeze register,              Address offset: 0x54 */
  uint32_t RESERVED6[41];      /*!< Reserved,                                       Address offset: 0x58-0xF8 */
  __IO uint32_t SR;            /*!< Debug MCU status register,                      Address offset: 0xFC */
  __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register,         Address offset: 0x100 */
  __IO uint32_t DBG_AUTH_DEV;  /*!< Debug MCU Authentication Device register,       Address offset: 0x104 */
  __IO uint32_t DBG_AUTH_ACK;  /*!< Debug MCU Authentication Ack register,          Address offset: 0x108 */
  uint32_t RESERVED7[945];     /*!< Reserved,                                       Address offset: 0x10C-0xFCC */
  __IO uint32_t PIDR4;         /*!< Debug MCU peripheral identity register 4,       Address offset: 0xFD0 */
  uint32_t RESERVED8[3];       /*!< Reserved,                                       Address offset: 0xFD4-0xFDC */
  __IO uint32_t PIDR0;         /*!< Debug MCU peripheral identity register 0,       Address offset: 0xFE0 */
  __IO uint32_t PIDR1;         /*!< Debug MCU peripheral identity register 1,       Address offset: 0xFE4 */
  __IO uint32_t PIDR2;         /*!< Debug MCU peripheral identity register 2,       Address offset: 0xFE8 */
  __IO uint32_t PIDR3;         /*!< Debug MCU peripheral identity register 3,       Address offset: 0xFEC */
  __IO uint32_t CIDR0;         /*!< Debug MCU component identity register 0,        Address offset: 0xFF0 */
  __IO uint32_t CIDR1;         /*!< Debug MCU component identity register 1,        Address offset: 0xFF4 */
  __IO uint32_t CIDR2;         /*!< Debug MCU component identity register 2,        Address offset: 0xFF8 */
  __IO uint32_t CIDR3;         /*!< Debug MCU component identity register 3,        Address offset: 0xFFC */
} DBGMCU_TypeDef;

/**
  * @brief DCMIPP
  */
typedef struct
{
  __IO uint32_t IPGR1;         /*!< IP-Plug global register 1                         Address offset: 0x00 */
  __IO uint32_t IPGR2;         /*!< IP-Plug global register 2                         Address offset: 0x04 */
  __IO uint32_t IPGR3;         /*!< IP-Plug global register 3                         Address offset: 0x08 */
  uint32_t RESERVED1[4];       /*!< Reserved,                                    Address offset: 0x0C-0x18 */
  __IO uint32_t IPGR8;         /*!< IP-Plug global register 8                         Address offset: 0x1C */
  __IO uint32_t IPC1R1;        /*!< IP-Plug client 1 register 1                       Address offset: 0x20 */
  __IO uint32_t IPC1R2;        /*!< IP-Plug client 1 register 2                       Address offset: 0x24 */
  __IO uint32_t IPC1R3;        /*!< IP-Plug client 1 register 3                       Address offset: 0x28 */
  __IO uint32_t RESERVED2[54]; /*!< Reserved,                                   Address offset: 0x2C-0x100 */
  __IO uint32_t PRCR;          /*!< Parallel interface control register              Address offset: 0x104 */
  __IO uint32_t PRESCR;        /*!< Parallel interface embedded sync code register   Address offset: 0x108 */
  __IO uint32_t PRESUR;        /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */
  __IO uint32_t RESERVED3[57]; /*!< Reserved,                                  Address offset: 0x110-0x1F0 */
  __IO uint32_t PRIER;         /*!< Parallel interface interrupt enable register     Address offset: 0x1F4 */
  __IO uint32_t PRSR;          /*!< Parallel interface status register               Address offset: 0x1F8 */
  __IO uint32_t PRFCR;         /*!< Parallel interface interrupt clear register      Address offset: 0x1FC */
  uint32_t RESERVED4;          /*!< Reserved,                                        Address offset: 0x200 */
  __IO uint32_t CMCR;          /*!< Common configuration register                    Address offset: 0x204 */
  __IO uint32_t CMFRCR;        /*!< Common frame counter register                    Address offset: 0x208 */
  __IO uint32_t RESERVED5[121]; /*!< Reserved,                                 Address offset: 0x20C-0x3EC */
  __IO uint32_t CMIER;         /*!< Common interrupt enable register                 Address offset: 0x3F0 */
  __IO uint32_t CMSR1;         /*!< Common status register 1                         Address offset: 0x3F4 */
  __IO uint32_t CMSR2;         /*!< Common status register 2                         Address offset: 0x3F8 */
  __IO uint32_t CMFCR;         /*!< Common interrupt clear register                  Address offset: 0x3FC */
  uint32_t RESERVED6;          /*!< Reserved,                                        Address offset: 0x400 */
  __IO uint32_t P0FSCR;        /*!< Pipe0 flow selection configuration register      Address offset: 0x404 */
  __IO uint32_t RESERVED7[62]; /*!< Reserved,                                  Address offset: 0x408-0x4FC */
  __IO uint32_t P0FCTCR;       /*!< Pipe0 flow control configuration register        Address offset: 0x500 */
  __IO uint32_t P0SCSTR;       /*!< Pipe0 stat/crop start register                   Address offset: 0x504 */
  __IO uint32_t P0SCSZR;       /*!< Pipe0 stat/crop size register                    Address offset: 0x508 */
  __IO uint32_t RESERVED8[41]; /*!< Reserved,                                  Address offset: 0x50C-0x5AC */
  __IO uint32_t P0DCCNTR;      /*!< Pipe0 dump counter register                      Address offset: 0x5B0 */
  __IO uint32_t P0DCLMTR;      /*!< Pipe0 dump limit register                        Address offset: 0x5B4 */
  __IO uint32_t RESERVED9[2];  /*!< Reserved,                                  Address offset: 0x5B8-0x5BC */
  __IO uint32_t P0PPCR;        /*!< Pipe0 pixel packer configuration register        Address offset: 0x5C0 */
  __IO uint32_t P0PPM0AR1;     /*!< Pipe0 pixel packer memory0 address register 1    Address offset: 0x5C4 */
  __IO uint32_t P0PPM0AR2;     /*!< Pipe0 pixel packer memory0 address register 2    Address offset: 0x5C8 */
  __IO uint32_t RESERVED10[10]; /*!< Reserved,                                 Address offset: 0x5CC-0x5F0 */
  __IO uint32_t P0IER;         /*!< Pipe0 interrupt enable register                  Address offset: 0x5F4 */
  __IO uint32_t P0SR;          /*!< Pipe0 status register                            Address offset: 0x5F8 */
  __IO uint32_t P0FCR;         /*!< Pipe0 interrupt clear register                   Address offset: 0x5FC */
  __IO uint32_t RESERVED11[64]; /*!< Reserved,                                 Address offset: 0x600-0x6FC */
  __IO uint32_t P0CFCTCR;      /*!< Pipe0 current flow control configuration register Address offset: 0x700 */
  __IO uint32_t P0CSCSTR;      /*!< Pipe0 current stat/crop start register           Address offset: 0x704 */
  __IO uint32_t P0CSCSZR;      /*!< Pipe0 current stat/crop size register            Address offset: 0x708 */
  __IO uint32_t RESERVED12[45]; /*!< Reserved,                                 Address offset: 0x70C-0x7BC */
  __IO uint32_t P0CPPCR;       /*!< Pipe0 current pixel packer configuration register      Address offset: 0x700 */
  __IO uint32_t P0CPPM0AR1;    /*!< Pipe0 current pixel packer memory0 address register 1  Address offset: 0x7C4 */
  __IO uint32_t P0CPPM0AR2;    /*!< Pipe0 current pixel packer memory0 address register 2  Address offset: 0x7C8 */
} DCMIPP_TypeDef;

/**
  * @ brief Delay Block
  */
typedef struct
{
  __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
  __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
} DLYB_TypeDef;

/**
  * @brief DMA Controller
  */
typedef struct
{
       uint32_t RESERVED1;     /*!< Reserved 1,                                      Address offset: 0x00 */
  __IO uint32_t PRIVCFGR;      /*!< DMA privileged configuration register,           Address offset: 0x04 */
  __IO uint32_t RCFGLOCKR;     /*!< DMA configuration lock register,                 Address offset: 0x08 */
  __IO uint32_t MISR;          /*!< DMA masked interrupt status register,            Address offset: 0x0C */
} DMA_TypeDef;

typedef struct
{
  __IO uint32_t CLBAR;         /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
       uint32_t RESERVED1[2];  /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
  __IO uint32_t CFCR;          /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
  __IO uint32_t CSR;           /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
  __IO uint32_t CCR;           /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
       uint32_t RESERVED2[10]; /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
  __IO uint32_t CTR1;          /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
  __IO uint32_t CTR2;          /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
  __IO uint32_t CBR1;          /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
  __IO uint32_t CSAR;          /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
  __IO uint32_t CDAR;          /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
  __IO uint32_t CTR3;          /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
  __IO uint32_t CBR2;          /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
       uint32_t RESERVED3[8];  /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8      */
  __IO uint32_t CLLR;          /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
} DMA_Channel_TypeDef;

/**
  * @brief DMA2D Controller
  */
typedef struct
{
  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
  uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
} DMA2D_TypeDef;

/**
  * @brief DTS
  */
typedef struct
{
  __IO uint32_t CFGR1;         /*!< DTS configuration register,                     Address offset: 0x00 */
  uint32_t RESERVED0;          /*!< Reserved,                                       Address offset: 0x04 */
  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                          Address offset: 0x08 */
  uint32_t RESERVED1;          /*!< Reserved,                                       Address offset: 0x0C */
  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                        Address offset: 0x10 */
  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,               Address offset: 0x14 */
  uint32_t RESERVED2;          /*!< Reserved,                                       Address offset: 0x18 */
  __IO uint32_t DR;            /*!< DTS data register,                              Address offset: 0x1C */
  __IO uint32_t SR;            /*!< DTS status register                             Address offset: 0x20 */
  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,                  Address offset: 0x24 */
  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,              Address offset: 0x28 */
  __IO uint32_t OR;            /*!< DTS option register 1,                          Address offset: 0x2C */
} DTS_TypeDef;

/**
  * @brief Ethernet MAC
  */
typedef struct
{
  __IO uint32_t MACCR;
  __IO uint32_t MACECR;
  __IO uint32_t MACPFR;
  __IO uint32_t MACWTR;
  __IO uint32_t MACHT0R;
  __IO uint32_t MACHT1R;
  uint32_t      RESERVED1[14];
  __IO uint32_t MACVTR;
  uint32_t      RESERVED2;
  __IO uint32_t MACVHTR;
  uint32_t      RESERVED3;
  __IO uint32_t MACVIR;
  __IO uint32_t MACIVIR;
  uint32_t      RESERVED4[2];
  __IO uint32_t MACTFCR;
  uint32_t      RESERVED5[7];
  __IO uint32_t MACRFCR;
  uint32_t      RESERVED6[7];
  __IO uint32_t MACISR;
  __IO uint32_t MACIER;
  __IO uint32_t MACRXTXSR;
  uint32_t      RESERVED7;
  __IO uint32_t MACPCSR;
  __IO uint32_t MACRWKPFR;
  uint32_t      RESERVED8[2];
  __IO uint32_t MACLCSR;
  __IO uint32_t MACLTCR;
  __IO uint32_t MACLETR;
  __IO uint32_t MAC1USTCR;
  uint32_t      RESERVED9[12];
  __IO uint32_t MACVR;
  __IO uint32_t MACDR;
  uint32_t      RESERVED10;
  __IO uint32_t MACHWF0R;
  __IO uint32_t MACHWF1R;
  __IO uint32_t MACHWF2R;
  uint32_t      RESERVED11[54];
  __IO uint32_t MACMDIOAR;
  __IO uint32_t MACMDIODR;
  uint32_t      RESERVED12[2];
  __IO uint32_t MACARPAR;
  uint32_t      RESERVED13[59];
  __IO uint32_t MACA0HR;
  __IO uint32_t MACA0LR;
  __IO uint32_t MACA1HR;
  __IO uint32_t MACA1LR;
  __IO uint32_t MACA2HR;
  __IO uint32_t MACA2LR;
  __IO uint32_t MACA3HR;
  __IO uint32_t MACA3LR;
  uint32_t      RESERVED14[248];
  __IO uint32_t MMCCR;
  __IO uint32_t MMCRIR;
  __IO uint32_t MMCTIR;
  __IO uint32_t MMCRIMR;
  __IO uint32_t MMCTIMR;
  uint32_t      RESERVED15[14];
  __IO uint32_t MMCTSCGPR;
  __IO uint32_t MMCTMCGPR;
  uint32_t      RESERVED16[5];
  __IO uint32_t MMCTPCGR;
  uint32_t      RESERVED17[10];
  __IO uint32_t MMCRCRCEPR;
  __IO uint32_t MMCRAEPR;
  uint32_t      RESERVED18[10];
  __IO uint32_t MMCRUPGR;
  uint32_t      RESERVED19[9];
  __IO uint32_t MMCTLPIMSTR;
  __IO uint32_t MMCTLPITCR;
  __IO uint32_t MMCRLPIMSTR;
  __IO uint32_t MMCRLPITCR;
  uint32_t      RESERVED20[65];
  __IO uint32_t MACL3L4C0R;
  __IO uint32_t MACL4A0R;
  uint32_t      RESERVED21[2];
  __IO uint32_t MACL3A0R0R;
  __IO uint32_t MACL3A1R0R;
  __IO uint32_t MACL3A2R0R;
  __IO uint32_t MACL3A3R0R;
  uint32_t      RESERVED22[4];
  __IO uint32_t MACL3L4C1R;
  __IO uint32_t MACL4A1R;
  uint32_t      RESERVED23[2];
  __IO uint32_t MACL3A0R1R;
  __IO uint32_t MACL3A1R1R;
  __IO uint32_t MACL3A2R1R;
  __IO uint32_t MACL3A3R1R;
  uint32_t      RESERVED24[108];
  __IO uint32_t MACTSCR;
  __IO uint32_t MACSSIR;
  __IO uint32_t MACSTSR;
  __IO uint32_t MACSTNR;
  __IO uint32_t MACSTSUR;
  __IO uint32_t MACSTNUR;
  __IO uint32_t MACTSAR;
  uint32_t      RESERVED25;
  __IO uint32_t MACTSSR;
  uint32_t      RESERVED26[3];
  __IO uint32_t MACTTSSNR;
  __IO uint32_t MACTTSSSR;
  uint32_t      RESERVED27[2];
  __IO uint32_t MACACR;
  uint32_t      RESERVED28;
  __IO uint32_t MACATSNR;
  __IO uint32_t MACATSSR;
  __IO uint32_t MACTSIACR;
  __IO uint32_t MACTSEACR;
  __IO uint32_t MACTSICNR;
  __IO uint32_t MACTSECNR;
  uint32_t      RESERVED29[4];
  __IO uint32_t MACPPSCR;
  uint32_t      RESERVED30[3];
  __IO uint32_t MACPPSTTSR;
  __IO uint32_t MACPPSTTNR;
  __IO uint32_t MACPPSIR;
  __IO uint32_t MACPPSWR;
  uint32_t      RESERVED31[12];
  __IO uint32_t MACPOCR;
  __IO uint32_t MACSPI0R;
  __IO uint32_t MACSPI1R;
  __IO uint32_t MACSPI2R;
  __IO uint32_t MACLMIR;
  uint32_t      RESERVED32[11];
  __IO uint32_t MTLOMR;
  uint32_t      RESERVED33[7];
  __IO uint32_t MTLISR;
  uint32_t      RESERVED34[55];
  __IO uint32_t MTLTQOMR;
  __IO uint32_t MTLTQUR;
  __IO uint32_t MTLTQDR;
  uint32_t      RESERVED35[8];
  __IO uint32_t MTLQICSR;
  __IO uint32_t MTLRQOMR;
  __IO uint32_t MTLRQMPOCR;
  __IO uint32_t MTLRQDR;
  uint32_t      RESERVED36[177];
  __IO uint32_t DMAMR;
  __IO uint32_t DMASBMR;
  __IO uint32_t DMAISR;
  __IO uint32_t DMADSR;
  uint32_t      RESERVED37[60];
  __IO uint32_t DMACCR;
  __IO uint32_t DMACTCR;
  __IO uint32_t DMACRCR;
  uint32_t      RESERVED38[2];
  __IO uint32_t DMACTDLAR;
  uint32_t      RESERVED39;
  __IO uint32_t DMACRDLAR;
  __IO uint32_t DMACTDTPR;
  uint32_t      RESERVED40;
  __IO uint32_t DMACRDTPR;
  __IO uint32_t DMACTDRLR;
  __IO uint32_t DMACRDRLR;
  __IO uint32_t DMACIER;
  __IO uint32_t DMACRIWTR;
__IO uint32_t DMACSFCSR;
  uint32_t      RESERVED41;
  __IO uint32_t DMACCATDR;
  uint32_t      RESERVED42;
  __IO uint32_t DMACCARDR;
  uint32_t      RESERVED43;
  __IO uint32_t DMACCATBR;
  uint32_t      RESERVED44;
  __IO uint32_t DMACCARBR;
  __IO uint32_t DMACSR;
uint32_t      RESERVED45[2];
__IO uint32_t DMACMFCR;
}ETH_TypeDef;

/**
  * @brief External Interrupt/Event Controller
  */
typedef struct
{
  __IO uint32_t RTSR1;         /*!< EXTI Rising trigger selection register 1,         Address offset: 0x00 */
  __IO uint32_t FTSR1;         /*!< EXTI Falling trigger selection register 1,        Address offset: 0x04 */
  __IO uint32_t SWIER1;        /*!< EXTI Software interrupt event register 1,         Address offset: 0x08 */
       uint32_t RESERVED1[5];  /*!< Reserved 1,                                  Address offset: 0x0C-0x1C */
  __IO uint32_t RTSR2;         /*!< EXTI Rising trigger selection register 2,         Address offset: 0x20 */
  __IO uint32_t FTSR2;         /*!< EXTI Falling trigger selection register 2,        Address offset: 0x24 */
  __IO uint32_t SWIER2;        /*!< EXTI Software interrupt event register 2,         Address offset: 0x28 */
       uint32_t RESERVED2[21]; /*!< Reserved 2,                                  Address offset: 0x2C-0x7C */
  __IO uint32_t IMR1;          /*!< EXTI Interrupt mask register 1,                   Address offset: 0x80 */
  __IO uint32_t EMR1;          /*!< EXTI Event mask register 1,                       Address offset: 0x84 */
  __IO uint32_t PR1;           /*!< EXTI Pending register 1,                          Address offset: 0x88 */
       uint32_t RESERVED3;     /*!< Reserved 3,                                       Address offset: 0x8C */
  __IO uint32_t IMR2;          /*!< EXTI Interrupt mask register 2,                   Address offset: 0x90 */
  __IO uint32_t EMR2;          /*!< EXTI Event mask register 2,                       Address offset: 0x94 */
  __IO uint32_t PR2;           /*!< EXTI Pending register 2,                          Address offset: 0x98 */
       uint32_t RESERVED4;     /*!< Reserved 4,                                       Address offset: 0x9C */
  __IO uint32_t IMR3;          /*!< EXTI Interrupt mask register 3,                   Address offset: 0xA0 */
  __IO uint32_t EMR3;          /*!< EXTI Event mask register 3,                       Address offset: 0xA4 */
} EXTI_TypeDef;

/**
  * @brief FD Controller Area Network
  */
typedef struct
{
  __IO uint32_t CREL;          /*!< FDCAN Core Release register,                      Address offset: 0x000 */
  __IO uint32_t ENDN;          /*!< FDCAN Endian register,                            Address offset: 0x004 */
       uint32_t RESERVED1;     /*!< Reserved,                                                         0x008 */
  __IO uint32_t DBTP;          /*!< FDCAN Data Bit Timing & Prescaler register,       Address offset: 0x00C */
  __IO uint32_t TEST;          /*!< FDCAN Test register,                              Address offset: 0x010 */
  __IO uint32_t RWD;           /*!< FDCAN RAM Watchdog register,                      Address offset: 0x014 */
  __IO uint32_t CCCR;          /*!< FDCAN CC Control register,                        Address offset: 0x018 */
  __IO uint32_t NBTP;          /*!< FDCAN Nominal Bit Timing & Prescaler register,    Address offset: 0x01C */
  __IO uint32_t TSCC;          /*!< FDCAN Timestamp Counter Configuration register,   Address offset: 0x020 */
  __IO uint32_t TSCV;          /*!< FDCAN Timestamp Counter Value register,           Address offset: 0x024 */
  __IO uint32_t TOCC;          /*!< FDCAN Timeout Counter Configuration register,     Address offset: 0x028 */
  __IO uint32_t TOCV;          /*!< FDCAN Timeout Counter Value register,             Address offset: 0x02C */
       uint32_t RESERVED2[4];  /*!< Reserved,                                                 0x030 - 0x03C */
  __IO uint32_t ECR;           /*!< FDCAN Error Counter register,                     Address offset: 0x040 */
  __IO uint32_t PSR;           /*!< FDCAN Protocol Status register,                   Address offset: 0x044 */
  __IO uint32_t TDCR;          /*!< FDCAN Transmitter Delay Compensation register,    Address offset: 0x048 */
       uint32_t RESERVED3;     /*!< Reserved,                                                         0x04C */
  __IO uint32_t IR;            /*!< FDCAN Interrupt register,                         Address offset: 0x050 */
  __IO uint32_t IE;            /*!< FDCAN Interrupt Enable register,                  Address offset: 0x054 */
  __IO uint32_t ILS;           /*!< FDCAN Interrupt Line Select register,             Address offset: 0x058 */
  __IO uint32_t ILE;           /*!< FDCAN Interrupt Line Enable register,             Address offset: 0x05C */
       uint32_t RESERVED4[8];  /*!< Reserved,                                                 0x060 - 0x07C */
  __IO uint32_t RXGFC;         /*!< FDCAN Global Filter Configuration register,       Address offset: 0x080 */
  __IO uint32_t XIDAM;         /*!< FDCAN Extended ID AND Mask register,              Address offset: 0x084 */
  __IO uint32_t HPMS;          /*!< FDCAN High Priority Message Status register,      Address offset: 0x088 */
       uint32_t RESERVED5;     /*!< Reserved,                                                         0x08C */
  __IO uint32_t RXF0S;         /*!< FDCAN Rx FIFO 0 Status register,                  Address offset: 0x090 */
  __IO uint32_t RXF0A;         /*!< FDCAN Rx FIFO 0 Acknowledge register,             Address offset: 0x094 */
  __IO uint32_t RXF1S;         /*!< FDCAN Rx FIFO 1 Status register,                  Address offset: 0x098 */
  __IO uint32_t RXF1A;         /*!< FDCAN Rx FIFO 1 Acknowledge register,             Address offset: 0x09C */
       uint32_t RESERVED6[8];  /*!< Reserved,                                                 0x0A0 - 0x0BC */
  __IO uint32_t TXBC;          /*!< FDCAN Tx Buffer Configuration register,           Address offset: 0x0C0 */
  __IO uint32_t TXFQS;         /*!< FDCAN Tx FIFO/Queue Status register,              Address offset: 0x0C4 */
  __IO uint32_t TXBRP;         /*!< FDCAN Tx Buffer Request Pending register,         Address offset: 0x0C8 */
  __IO uint32_t TXBAR;         /*!< FDCAN Tx Buffer Add Request register,             Address offset: 0x0CC */
  __IO uint32_t TXBCR;         /*!< FDCAN Tx Buffer Cancellation Request register,    Address offset: 0x0D0 */
  __IO uint32_t TXBTO;         /*!< FDCAN Tx Buffer Transmission Occurred register,   Address offset: 0x0D4 */
  __IO uint32_t TXBCF;         /*!< FDCAN Tx Buffer Cancellation Finished register,   Address offset: 0x0D8 */
  __IO uint32_t TXBTIE;        /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
  __IO uint32_t TXBCIE;        /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
  __IO uint32_t TXEFS;         /*!< FDCAN Tx Event FIFO Status register,              Address offset: 0x0E4 */
  __IO uint32_t TXEFA;         /*!< FDCAN Tx Event FIFO Acknowledge register,         Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;

/**
  * @brief FD Controller Area Network Configuration
  */
typedef struct
{
  __IO uint32_t CKDIV;         /*!< FDCAN clock divider register,                    Address offset: 0x100 + 0x000 */
       uint32_t RESERVED1[128];/*!< Reserved,                                        0x100 + 0x004 - 0x100 + 0x200 */
  __IO uint32_t OPTR;          /*!< FDCAN option register,                           Address offset: 0x100 + 0x204 */
       uint32_t RESERVED2[58]; /*!< Reserved,                                        0x100 + 0x208 - 0x100 + 0x2EC */
  __IO uint32_t HWCFG;         /*!< FDCAN hardware configuration register,           Address offset: 0x100 + 0x2F0 */
  __IO uint32_t VERR;          /*!< FDCAN IP version register,                       Address offset: 0x100 + 0x2F4 */
  __IO uint32_t IPIDR;         /*!< FDCAN IP ID register,                            Address offset: 0x100 + 0x2F8 */
  __IO uint32_t SIDR;          /*!< FDCAN size ID register,                          Address offset: 0x100 + 0x2FC */
} FDCAN_Config_TypeDef;

/**
  * @brief FLASH Registers
  */
typedef struct
{
  __IO uint32_t ACR;           /*!< FLASH access control register,                          Address offset: 0x000         */
  __IO uint32_t KEYR;          /*!< FLASH control key register,                             Address offset: 0x004         */
       uint32_t RESERVED1[2];  /*!< Reserved,                                               Address offset: 0x008 - 0x00C */
  __IO uint32_t CR;            /*!< FLASH control register,                                 Address offset: 0x010         */
  __IO uint32_t SR;            /*!< FLASH status register,                                  Address offset: 0x014         */
       uint32_t RESERVED2[2];  /*!< Reserved,                                               Address offset: 0x018 - 0x01C */
  __IO uint32_t IER;           /*!< FLASH interrupt enable register,                        Address offset: 0x020         */
  __IO uint32_t ISR;           /*!< FLASH interrupt status register,                        Address offset: 0x024         */
  __IO uint32_t ICR;           /*!< FLASH interrupt clear register,                         Address offset: 0x028         */
       uint32_t RESERVED3;     /*!< Reserved,                                               Address offset: 0x02C         */
  __IO uint32_t CRCCR;         /*!< FLASH CRC control register,                             Address offset: 0x030         */
  __IO uint32_t CRCSADDR;      /*!< FLASH CRC start address register,                       Address offset: 0x034         */
  __IO uint32_t CRCEADDR;      /*!< FLASH CRC end address register,                         Address offset: 0x038         */
  __IO uint32_t CRCDATAR;      /*!< FLASH CRC data register,                                Address offset: 0x03C         */
  __IO uint32_t ECCSFADDR;     /*!< FLASH ECC single fail address register,                 Address offset: 0x040         */
  __IO uint32_t ECCDFADDR;     /*!< FLASH ECC double fail address register,                 Address offset: 0x044         */
       uint32_t RESERVED4[46]; /*!< Reserved,                                               Address offset: 0x048 - 0x0FC */
  __IO uint32_t OPTKEYR;       /*!< FLASH options key register,                             Address offset: 0x100         */
  __IO uint32_t OPTCR;         /*!< FLASH options control register,                         Address offset: 0x104         */
  __IO uint32_t OPTISR;        /*!< FLASH options interrupt status register,                Address offset: 0x108         */
  __IO uint32_t OPTICR;        /*!< FLASH options interrupt clear register,                 Address offset: 0x10C         */
  __IO uint32_t OBKCR;         /*!< FLASH option byte key control register,                 Address offset: 0x110         */
       uint32_t RESERVED5;     /*!< Reserved,                                               Address offset: 0x114         */
  __IO uint32_t OBKDR[8];      /*!< FLASH option bytes key data register,                   Address offset: 0x118 - 0x134 */
       uint32_t RESERVED6[50]; /*!< Reserved,                                               Address offset: 0x138 - 0x1FC */
  __IO uint32_t NVSR;          /*!< FLASH non-volatile status register,                     Address offset: 0x200         */
  __IO uint32_t NVSRP;         /*!< FLASH security status register programming,             Address offset: 0x204         */
  __IO uint32_t ROTSR;         /*!< FLASH RoT status register,                              Address offset: 0x208         */
  __IO uint32_t ROTSRP;        /*!< FLASH RoT status register programming,                  Address offset: 0x20C         */
  __IO uint32_t OTPLSR;        /*!< FLASH OTP lock status register,                         Address offset: 0x210         */
  __IO uint32_t OTPLSRP;       /*!< FLASH OTP lock status programming register,             Address offset: 0x214         */
  __IO uint32_t WRPSR;         /*!< FLASH write protection status register,                 Address offset: 0x218         */
  __IO uint32_t WRPSRP;        /*!< FLASH write protection status register programming,     Address offset: 0x21C         */
       uint32_t RESERVED7[4];  /*!< Reserved,                                               Address offset: 0x220 - 0x22C */
  __IO uint32_t HDPSR;         /*!< FLASH hide protection status register,                  Address offset: 0x230         */
  __IO uint32_t HDPSRP;        /*!< FLASH hide protection status register programming,      Address offset: 0x234         */
       uint32_t RESERVED8[6];  /*!< Reserved,                                               Address offset: 0x238 - 0x24C */
  __IO uint32_t EPOCHSR;       /*!< FLASH epoch status register,                            Address offset: 0x250         */
  __IO uint32_t EPOCHSRP;      /*!< FLASH epoch status register programming,                Address offset: 0x254         */
       uint32_t RESERVED9[2];  /*!< Reserved,                                               Address offset: 0x258 - 0x25C */
  __IO uint32_t OBW1SR;        /*!< FLASH option byte word 1 status register,               Address offset: 0x260         */
  __IO uint32_t OBW1SRP;       /*!< FLASH option byte word 1 status register programming,   Address offset: 0x264         */
  __IO uint32_t OBW2SR;        /*!< FLASH option byte word 2 status register,               Address offset: 0x268         */
  __IO uint32_t OBW2SRP;       /*!< FLASH option byte word 2 status register programming,   Address offset: 0x26C         */
} FLASH_TypeDef;

/**
  * @brief Flexible Memory Controller Bank1
  */
typedef struct {
  __IO uint32_t BTCR[8];       /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FMC_Bank1_TypeDef;

/**
  * @brief Flexible Memory Controller Bank1 Extended
  */
typedef struct {
  __IO uint32_t BWTR[7];       /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;

/**
  * @brief Flexible Memory Controller Bank3
  */
typedef struct {
  __IO uint32_t PCR;           /*!< NAND Flash control register,                       Address offset: 0x80 */
  __IO uint32_t SR;            /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
  __IO uint32_t PMEM;          /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
  __IO uint32_t PATT;          /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
       uint32_t RESERVED0;     /*!< Reserved,                                          Address offset: 0x90 */
  __IO uint32_t ECCR;          /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
} FMC_Bank3_TypeDef;

/**
  * @brief Flexible Memory Controller Bank5 & 6
  */
typedef struct
{
  __IO uint32_t SDCR[2];       /*!< SDRAM Control registers ,     Address offset: 0x140 - 0x144 */
  __IO uint32_t SDTR[2];       /*!< SDRAM Timing registers ,      Address offset: 0x148 - 0x14C */
  __IO uint32_t SDCMR;         /*!< SDRAM Command Mode register,  Address offset: 0x150         */
  __IO uint32_t SDRTR;         /*!< SDRAM Refresh Timer register, Address offset: 0x154         */
  __IO uint32_t SDSR;          /*!< SDRAM Status register,        Address offset: 0x158         */
} FMC_Bank5_6_TypeDef;

/**
  * @brief General Purpose I/O
  */
typedef struct
{
  __IO uint32_t MODER;         /*!< GPIO port mode register,               Address offset: 0x00      */
  __IO uint32_t OTYPER;        /*!< GPIO port output type register,        Address offset: 0x04      */
  __IO uint32_t OSPEEDR;       /*!< GPIO port output speed register,       Address offset: 0x08      */
  __IO uint32_t PUPDR;         /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
  __IO uint32_t IDR;           /*!< GPIO port input data register,         Address offset: 0x10      */
  __IO uint32_t ODR;           /*!< GPIO port output data register,        Address offset: 0x14      */
  __IO uint32_t BSRR;          /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
  __IO uint32_t LCKR;          /*!< GPIO port configuration lock register, Address offset: 0x1C      */
  __IO uint32_t AFR[2];        /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
  __IO uint32_t BRR;           /*!< GPIO Bit Reset register,               Address offset: 0x28      */
} GPIO_TypeDef;

/**
  * @brief GFXMMU
  */
typedef struct
{
  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
       uint32_t RESERVED0;       /*!< Reserved0,                                         Address offset: 0x0C */
  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
  __IO uint32_t DAR;             /*!< GFXMMU default alpha register,                     Address offset: 0x14 */
       uint32_t RESERVED1[2];    /*!< Reserved1,                                 Address offset: 0x18 to 0x1C */
  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
       uint32_t RESERVED2[1012]; /*!< Reserved2,                                 Address offset: 0x30 to 0xFFC */
  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                      Address offset: 0x1000 to 0x2FFC
                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;

/**
  * @brief HASH
  */
typedef struct
{
  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
  __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
} HASH_TypeDef;

/**
  * @brief HASH_DIGEST
  */
typedef struct
{
  __IO uint32_t HR[16];            /*!< HASH digest registers,          Address offset: 0x310-0x34C */
} HASH_DIGEST_TypeDef;

/**
  * @brief Inter-integrated Circuit Interface
  */

typedef struct
{
  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
} I2C_TypeDef;

/**
  * @brief Improved Inter-integrated Circuit Interface
  */

typedef struct
{
  __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
  __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
  uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
  __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
  __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
  __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
  __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
  __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
  __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
  uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
  __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
  __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
  uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
  __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
  uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
  __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
  __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
  __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
  uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
  __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
  __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
  uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
  __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
  __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
  uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
  __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
  __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
  __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
  uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
  __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
  __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
  __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
  __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
  __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
  __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
} I3C_TypeDef;


/**
  * @brief IWDG
  */
typedef struct
{
  __IO uint32_t KR;            /*!< IWDG Key register,                  Address offset: 0x00 */
  __IO uint32_t PR;            /*!< IWDG Prescaler register,            Address offset: 0x04 */
  __IO uint32_t RLR;           /*!< IWDG Reload register,               Address offset: 0x08 */
  __IO uint32_t SR;            /*!< IWDG Status register,               Address offset: 0x0C */
  __IO uint32_t WINR;          /*!< IWDG Window register,               Address offset: 0x10 */
  __IO uint32_t EWCR;          /*!< IWDG Early Wakeup register,         Address offset: 0x14 */
} IWDG_TypeDef;

/**
  * @brief JPEG Codec
  */
typedef struct
{
  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 0x00 */
  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 0x04 */
  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 0x08 */
  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0x0C */
  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 0x10 */
  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 0x14 */
  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 0x18 */
  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 0x1C */
       uint32_t RESERVED0[4];    /* Reserved                                            Address offset: 0x20-0x2C */
  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 0x30 */
  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 0x34 */
  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 0x38 */
       uint32_t RESERVED1;       /* Reserved                                            Address offset: 0x3C */
  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 0x40 */
  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 0x44 */
       uint32_t RESERVED2[2];    /* Reserved                                            Address offset: 0x48-0x4C */
  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 0x50-0x8C */
  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 0x90-0xCC */
  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: 0xD0-0x10C */
  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 0x110-0x14C */
  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 0x150-0x18C */
  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 0x190-0x20C */
  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 0x210-0x35C */
  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 0x360-0x4F8 */
       uint32_t RESERVED3;       /* Reserved                                            Address offset: 0x4FC */
  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 0x500-0x65C */
  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 0x660-0x7BC */
  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 0x7C0-0x7DC */
  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 0x7E0-0x7FC */
} JPEG_TypeDef;

/**
  * @brief LPTIMER
  */
typedef struct
{
  __IO uint32_t ISR;           /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
  __IO uint32_t ICR;           /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
  __IO uint32_t DIER;          /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
  __IO uint32_t CFGR;          /*!< LPTIM Configuration register,           Address offset: 0x0C */
  __IO uint32_t CR;            /*!< LPTIM Control register,                 Address offset: 0x10 */
  __IO uint32_t CCR1;          /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
  __IO uint32_t ARR;           /*!< LPTIM Autoreload register,              Address offset: 0x18 */
  __IO uint32_t CNT;           /*!< LPTIM Counter register,                 Address offset: 0x1C */
  __IO uint32_t RESERVED0;     /*!< Reserved,                               Address offset: 0x20 */
  __IO uint32_t CFGR2;         /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
  __IO uint32_t RCR;           /*!< LPTIM Repetition register,              Address offset: 0x28 */
  __IO uint32_t CCMR1;         /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
  __IO uint32_t RESERVED1;     /*!< Reserved,                               Address offset: 0x30 */
  __IO uint32_t CCR2;          /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
} LPTIM_TypeDef;

/**
  * @brief Memory Cipher Engine (MCE)
  */
typedef struct
{
  __IO uint32_t REGCR;            /*!< MCE region configuration register,             Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */
  __IO uint32_t SADDR;            /*!< MCE region start address register,             Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */
  __IO uint32_t EADDR;            /*!< MCE region end address register,               Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */
  __IO uint32_t ATTR;             /*!< MCE region attribute register,                 Address offset: 0x04C + 0x10 * (x-1) (x = 1 to 4) */
} MCE_Region_TypeDef;

typedef struct
{
  __IO uint32_t CCCFGR;           /*!< MCE cipher context configuration register,     Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */
  __IO uint32_t CCNR0;            /*!< MCE cipher context nonce register 0,           Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */
  __IO uint32_t CCNR1;            /*!< MCE cipher context nonce register 1,           Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */
  __IO uint32_t CCKEYR0;          /*!< MCE cipher context key register 0,             Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */
  __IO uint32_t CCKEYR1;          /*!< MCE cipher context key register 1,             Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */
  __IO uint32_t CCKEYR2;          /*!< MCE cipher context key register 2,             Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */
  __IO uint32_t CCKEYR3;          /*!< MCE cipher context key register 3,             Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */
} MCE_Context_TypeDef;

typedef struct
{
  __IO uint32_t CR;               /*!< MCE configuration register,                           Address offset: 0x000       */
  __IO uint32_t SR;               /*!< MCE status register,                                  Address offset: 0x004       */
  __IO uint32_t IASR;             /*!< MCE illegal access status register,                   Address offset: 0x008       */
  __IO uint32_t IACR;             /*!< MCE illegal access clear register,                    Address offset: 0x00C       */
  __IO uint32_t IAIER;            /*!< MCE illegal access interrupt enable register,         Address offset: 0x010       */
  uint32_t RESERVED1[2];          /*!< Reserved,                                             Address offset: 0x014-0x018 */
  __IO uint32_t PRIVCFGR;         /*!< MCE privileged configuration register,                Address offset: 0x01C       */
  __IO uint32_t IAESR;            /*!< MCE illegal access error status register,             Address offset: 0x020       */
  __IO uint32_t IADDR;            /*!< MCE illegal address register,                         Address offset: 0x024       */
  uint32_t RESERVED2[118];        /*!< Reserved,                                             Address offset: 0x028-0x1FC */
  __IO uint32_t MKEYR0;           /*!< MCE master key register 0,                            Address offset: 0x200       */
  __IO uint32_t MKEYR1;           /*!< MCE master key register 1,                            Address offset: 0x204       */
  __IO uint32_t MKEYR2;           /*!< MCE master key register 2,                            Address offset: 0x208       */
  __IO uint32_t MKEYR3;           /*!< MCE master key register 3,                            Address offset: 0x20C       */
  uint32_t RESERVED3[4];          /*!< Reserved,                                             Address offset: 0x210-0x21C */
  __IO uint32_t FMKEYR0;          /*!< MCE fast master key register 0,                       Address offset: 0x220       */
  __IO uint32_t FMKEYR1;          /*!< MCE fast master key register 1,                       Address offset: 0x224       */
  __IO uint32_t FMKEYR2;          /*!< MCE fast master key register 2,                       Address offset: 0x228       */
  __IO uint32_t FMKEYR3;          /*!< MCE fast master key register 3,                       Address offset: 0x22C       */
} MCE_TypeDef;

/**
  * @brief MDIOS
  */

typedef struct
{
  __IO uint32_t CR;
  __IO uint32_t WRFR;
  __IO uint32_t CWRFR;
  __IO uint32_t RDFR;
  __IO uint32_t CRDFR;
  __IO uint32_t SR;
  __IO uint32_t CLRFR;
  uint32_t RESERVED[57];
  __IO uint32_t DINR0;
  __IO uint32_t DINR1;
  __IO uint32_t DINR2;
  __IO uint32_t DINR3;
  __IO uint32_t DINR4;
  __IO uint32_t DINR5;
  __IO uint32_t DINR6;
  __IO uint32_t DINR7;
  __IO uint32_t DINR8;
  __IO uint32_t DINR9;
  __IO uint32_t DINR10;
  __IO uint32_t DINR11;
  __IO uint32_t DINR12;
  __IO uint32_t DINR13;
  __IO uint32_t DINR14;
  __IO uint32_t DINR15;
  __IO uint32_t DINR16;
  __IO uint32_t DINR17;
  __IO uint32_t DINR18;
  __IO uint32_t DINR19;
  __IO uint32_t DINR20;
  __IO uint32_t DINR21;
  __IO uint32_t DINR22;
  __IO uint32_t DINR23;
  __IO uint32_t DINR24;
  __IO uint32_t DINR25;
  __IO uint32_t DINR26;
  __IO uint32_t DINR27;
  __IO uint32_t DINR28;
  __IO uint32_t DINR29;
  __IO uint32_t DINR30;
  __IO uint32_t DINR31;
  __IO uint32_t DOUTR0;
  __IO uint32_t DOUTR1;
  __IO uint32_t DOUTR2;
  __IO uint32_t DOUTR3;
  __IO uint32_t DOUTR4;
  __IO uint32_t DOUTR5;
  __IO uint32_t DOUTR6;
  __IO uint32_t DOUTR7;
  __IO uint32_t DOUTR8;
  __IO uint32_t DOUTR9;
  __IO uint32_t DOUTR10;
  __IO uint32_t DOUTR11;
  __IO uint32_t DOUTR12;
  __IO uint32_t DOUTR13;
  __IO uint32_t DOUTR14;
  __IO uint32_t DOUTR15;
  __IO uint32_t DOUTR16;
  __IO uint32_t DOUTR17;
  __IO uint32_t DOUTR18;
  __IO uint32_t DOUTR19;
  __IO uint32_t DOUTR20;
  __IO uint32_t DOUTR21;
  __IO uint32_t DOUTR22;
  __IO uint32_t DOUTR23;
  __IO uint32_t DOUTR24;
  __IO uint32_t DOUTR25;
  __IO uint32_t DOUTR26;
  __IO uint32_t DOUTR27;
  __IO uint32_t DOUTR28;
  __IO uint32_t DOUTR29;
  __IO uint32_t DOUTR30;
  __IO uint32_t DOUTR31;
} MDIOS_TypeDef;

/**
  * @brief ADF
  */
typedef struct
{
  __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
  __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
} MDF_TypeDef;

/**
  * @brief ADF filter
  */
typedef struct
{
  __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
  __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
  __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
  __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
  __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
  uint32_t      RESERVED0[4];   /*!< Reserved, 0x94-0xA0                                                  */
  __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
  uint32_t      RESERVED1[1];   /*!< Reserved, 0xA8                                                       */
  __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
  __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
  uint32_t      RESERVED2[1];   /*!< Reserved, 0xB4                                                       */
  __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
  __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
  __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
  __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
  uint32_t      RESERVED3[10];  /*!< Reserved, 0xC8-0xEC                                                  */
  __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
} MDF_Filter_TypeDef;

/**
  * @brief XSPI
  */
typedef struct
{
  __IO uint32_t CR;             /*!< XSPI Control Register,                                Address offset: 0x000         */
       uint32_t RESERVED1;      /*!< Reserved,                                             Address offset: 0x004         */
  __IO uint32_t DCR1;           /*!< XSPI Device Configuration Register 1,                 Address offset: 0x008         */
  __IO uint32_t DCR2;           /*!< XSPI Device Configuration Register 2,                 Address offset: 0x00C         */
  __IO uint32_t DCR3;           /*!< XSPI Device Configuration Register 3,                 Address offset: 0x010         */
  __IO uint32_t DCR4;           /*!< XSPI Device Configuration Register 4,                 Address offset: 0x014         */
       uint32_t RESERVED2[2];   /*!< Reserved,                                             Address offset: 0x018 - 0x01C */
  __IO uint32_t SR;             /*!< XSPI Status Register,                                 Address offset: 0x020         */
  __IO uint32_t FCR;            /*!< XSPI Flag Clear Register,                             Address offset: 0x024         */
       uint32_t RESERVED3[6];   /*!< Reserved,                                             Address offset: 0x028 - 0x03C */
  __IO uint32_t DLR;            /*!< XSPI Data Length Register,                            Address offset: 0x040         */
       uint32_t RESERVED4;      /*!< Reserved,                                             Address offset: 0x044         */
  __IO uint32_t AR;             /*!< XSPI Address Register,                                Address offset: 0x048         */
       uint32_t RESERVED5;      /*!< Reserved,                                             Address offset: 0x04C         */
  __IO uint32_t DR;             /*!< XSPI Data Register,                                   Address offset: 0x050         */
       uint32_t RESERVED6[11];  /*!< Reserved,                                             Address offset: 0x054 - 0x07C */
  __IO uint32_t PSMKR;          /*!< XSPI Polling Status Mask Register,                    Address offset: 0x080         */
       uint32_t RESERVED7;      /*!< Reserved,                                             Address offset: 0x084         */
  __IO uint32_t PSMAR;          /*!< XSPI Polling Status Match Register,                   Address offset: 0x088         */
       uint32_t RESERVED8;      /*!< Reserved,                                             Address offset: 0x08C         */
  __IO uint32_t PIR;            /*!< XSPI Polling Interval Register,                       Address offset: 0x090         */
       uint32_t RESERVED9[27];  /*!< Reserved,                                             Address offset: 0x094 - 0x0FC */
  __IO uint32_t CCR;            /*!< XSPI Communication Configuration Register,            Address offset: 0x100         */
       uint32_t RESERVED10;     /*!< Reserved,                                             Address offset: 0x104         */
  __IO uint32_t TCR;            /*!< XSPI Timing Configuration Register,                   Address offset: 0x108         */
       uint32_t RESERVED11;     /*!< Reserved,                                             Address offset: 0x10C         */
  __IO uint32_t IR;             /*!< XSPI Instruction Register,                            Address offset: 0x110         */
       uint32_t RESERVED12[3];  /*!< Reserved,                                             Address offset: 0x114 - 0x11C */
  __IO uint32_t ABR;            /*!< XSPI Alternate Bytes Register,                        Address offset: 0x120         */
       uint32_t RESERVED13[3];  /*!< Reserved,                                             Address offset: 0x124 - 0x12C */
  __IO uint32_t LPTR;           /*!< XSPI Low-Power Timeout Register,                      Address offset: 0x130         */
       uint32_t RESERVED14[3];  /*!< Reserved,                                             Address offset: 0x134 - 0x13C */
  __IO uint32_t WPCCR;          /*!< XSPI Wrap Communication Configuration Register,       Address offset: 0x140         */
       uint32_t RESERVED15;     /*!< Reserved,                                             Address offset: 0x144         */
  __IO uint32_t WPTCR;          /*!< XSPI Wrap Timing Configuration Register,              Address offset: 0x148         */
       uint32_t RESERVED16;     /*!< Reserved,                                             Address offset: 0x14C         */
  __IO uint32_t WPIR;           /*!< XSPI Wrap Instruction Register,                       Address offset: 0x150         */
       uint32_t RESERVED17[3];  /*!< Reserved,                                             Address offset: 0x154 - 0x15C */
  __IO uint32_t WPABR;          /*!< XSPI Wrap Alternate Bytes Register,                   Address offset: 0x160         */
       uint32_t RESERVED18[7];  /*!< Reserved,                                             Address offset: 0x164 - 0x17C */
  __IO uint32_t WCCR;           /*!< XSPI Write Communication Configuration Register,      Address offset: 0x180         */
       uint32_t RESERVED19;     /*!< Reserved,                                             Address offset: 0x184         */
  __IO uint32_t WTCR;           /*!< XSPI Write Timing Configuration Register,             Address offset: 0x188         */
       uint32_t RESERVED20;     /*!< Reserved,                                             Address offset: 0x18C         */
  __IO uint32_t WIR;            /*!< XSPI Write Instruction Register,                      Address offset: 0x190         */
       uint32_t RESERVED21[3];  /*!< Reserved,                                             Address offset: 0x194 - 0x19C */
  __IO uint32_t WABR;           /*!< XSPI Write Alternate Bytes Register,                  Address offset: 0x1A0         */
       uint32_t RESERVED22[23]; /*!< Reserved,                                             Address offset: 0x1A4 - 0x1FC */
  __IO uint32_t HLCR;           /*!< XSPI HyperBus Latency Configuration Register,         Address offset: 0x200         */
       uint32_t RESERVED23[3];  /*!< Reserved,                                             Address offset: 0x204 - 0x20C */
  __IO uint32_t CALFCR;         /*!< XSPI Full-Cycle Calibration Configuration Register,   Address offset: 0x210         */
       uint32_t RESERVED24;     /*!< Reserved,                                             Address offset: 0x214         */
  __IO uint32_t CALMR;          /*!< XSPI DLL Master Calibration Configuration Register,   Address offset: 0x218         */
       uint32_t RESERVED25;     /*!< Reserved,                                             Address offset: 0x21C         */
  __IO uint32_t CALSOR;         /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220         */
       uint32_t RESERVED26;     /*!< Reserved,                                             Address offset: 0x224         */
  __IO uint32_t CALSIR;         /*!< XSPI Slave Input Calibration Configuration Register,  Address offset: 0x228         */
} XSPI_TypeDef;

/**
  * @brief XSPI IO Manager
  */
typedef struct
{
  __IO uint32_t CR;     /*!< XSPIM IO Manager Control Register,                  Address offset: 0x00        */
} XSPIM_TypeDef;

/**
  * @brief Power Control
  */

typedef struct
{
  __IO uint32_t CR1;           /*!< PWR power control register 1,                 Address offset: 0x00 */
  __IO uint32_t SR1;           /*!< PWR power status register 1,                  Address offset: 0x04 */
  __IO uint32_t CSR1;          /*!< PWR power control status register 1,          Address offset: 0x08 */
  __IO uint32_t CSR2;          /*!< PWR power control status register 2,          Address offset: 0x0C */
  __IO uint32_t CSR3;          /*!< PWR power control status register 3,          Address offset: 0x10 */
  __IO uint32_t CSR4;          /*!< PWR power control status register 4,          Address offset: 0x14 */
  uint32_t      RESERVED0[2];  /*!< Reserved */
  __IO uint32_t WKUPCR;        /*!< PWR wakeup clear register,                    Address offset: 0x20 */
  __IO uint32_t WKUPFR;        /*!< PWR wakeup flag register,                     Address offset: 0x24 */
  __IO uint32_t WKUPEPR;       /*!< PWR wakeup enable and polarity register,      Address offset: 0x28 */
  __IO uint32_t UCPDR;         /*!< PWR USB Type-C and power delivery register,   Address offset: 0x2C */
  __IO uint32_t APCR;          /*!< PWR apply pull configuration register,        Address offset: 0x30 */
  __IO uint32_t PUCRN;         /*!< PWR port N pull-up control register,          Address offset: 0x34 */
  __IO uint32_t PDCRN;         /*!< PWR port N pull-down control register,        Address offset: 0x38 */
  __IO uint32_t PUCRO;         /*!< PWR port O pull-up control register,          Address offset: 0x3C */
  __IO uint32_t PDCRO;         /*!< PWR port O pull-down control register,        Address offset: 0x40 */
  __IO uint32_t PDCRP;         /*!< PWR port P pull-down control register,        Address offset: 0x44 */
  uint32_t      RESERVED2[2];  /*!< Reserved */
  __IO uint32_t PDR1;          /*!< PWR debug register 1,                         Address offset: 0x50 */
} PWR_TypeDef;

/**
  * @brief Public Key Accelerator (PKA)
  */

typedef struct
{
  __IO uint32_t CR;          /*!< PKA control register,                 Address offset: 0x00 */
  __IO uint32_t SR;          /*!< PKA status register,                  Address offset: 0x04 */
  __IO uint32_t CLRFR;       /*!< PKA clear flag register,              Address offset: 0x08 */
  uint32_t Reserved1[253];   /*!< Reserved,                             Address offset: 0x000C-0x03FC */
  __IO uint32_t RAM[1334];   /*!< PKA RAM                               Address offset: 0x0400-0x18D8 */
} PKA_TypeDef;

/**
  * @brief PSSI
  */
typedef struct
{
  __IO uint32_t CR;            /*!< PSSI control register,                 Address offset: 0x000 */
  __IO uint32_t SR;            /*!< PSSI status register,                  Address offset: 0x004 */
  __IO uint32_t RIS;           /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
  __IO uint32_t IER;           /*!< PSSI interrupt enable register,        Address offset: 0x00C */
  __IO uint32_t MIS;           /*!< PSSI masked interrupt status register, Address offset: 0x010 */
  __IO uint32_t ICR;           /*!< PSSI interrupt clear register,         Address offset: 0x014 */
  __IO uint32_t RESERVED1[4];  /*!< Reserved,                      Address offset: 0x018 - 0x024 */
  __IO uint32_t DR;            /*!< PSSI data register,                    Address offset: 0x028 */
} PSSI_TypeDef;

/**
  * @brief RAM_ECC_Specific_Registers
  */
typedef struct
{
  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
} RAMECC_MonitorTypeDef;

typedef struct
{
  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
} RAMECC_TypeDef;


/**
  * @brief Reset and Clock Control
  */

typedef struct
{
  __IO uint32_t CR;            /*!< RCC clock control register,                                              Address offset: 0x00 */
  __IO uint32_t HSICFGR;       /*!< HSI clock calibration register,                                          Address offset: 0x04 */
  __IO uint32_t CRRCR;         /*!< Clock recovery RC register,                                              Address offset: 0x08 */
  __IO uint32_t CSICFGR;       /*!< CSI clock calibration register,                                          Address offset: 0x0C */
  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                                        Address offset: 0x10 */
  uint32_t      RESERVED0;     /*!< Reserved,                                                                Address offset: 0x14 */
  __IO uint32_t CDCFGR;        /*!< RCC CPU domain configuration register,                                   Address offset: 0x18 */
  __IO uint32_t BMCFGR;        /*!< RCC Bus matrix configuration register,                                   Address offset: 0x1C */
  __IO uint32_t APBCFGR;       /*!< RCC APB clock configuration register,                                    Address offset: 0x20 */
  uint32_t      RESERVED1;     /*!< Reserved,                                                                Address offset: 0x24 */
  __IO uint32_t PLLCKSELR;     /*!< RCC PLLs clock source selection register,                                Address offset: 0x28 */
  __IO uint32_t PLLCFGR;       /*!< RCC PLLs configuration register,                                         Address offset: 0x2C */
  __IO uint32_t PLL1DIVR1;     /*!< RCC PLL1 dividers configuration register 1,                              Address offset: 0x30 */
  __IO uint32_t PLL1FRACR;     /*!< RCC PLL1 fractional divider configuration register,                      Address offset: 0x34 */
  __IO uint32_t PLL2DIVR1;     /*!< RCC PLL2 dividers configuration register 1,                              Address offset: 0x38 */
  __IO uint32_t PLL2FRACR;     /*!< RCC PLL2 fractional divider configuration register,                      Address offset: 0x3C */
  __IO uint32_t PLL3DIVR1;     /*!< RCC PLL3 dividers configuration register 1,                              Address offset: 0x40 */
  __IO uint32_t PLL3FRACR;     /*!< RCC PLL3 fractional divider configuration register,                      Address offset: 0x44 */
  uint32_t      RESERVED2;     /*!< Reserved,                                                                Address offset: 0x48 */
  __IO uint32_t CCIPR1;        /*!< RCC AHB peripherals kernel clock configuration register                  Address offset: 0x4C */
  __IO uint32_t CCIPR2;        /*!< RCC APB1 peripherals kernel clock configuration register                 Address offset: 0x50 */
  __IO uint32_t CCIPR3;        /*!< RCC APB2 peripherals kernel clock configuration register                 Address offset: 0x54 */
  __IO uint32_t CCIPR4;        /*!< RCC APB4/APB5 peripherals kernel clock configuration register            Address offset: 0x58 */
  uint32_t      RESERVED3;     /*!< Reserved,                                                                Address offset: 0x5C */
  __IO uint32_t CIER;          /*!< RCC clock interrupt enable register,                                     Address offset: 0x60 */
  __IO uint32_t CIFR;          /*!< RCC clock interrupt flag register,                                       Address offset: 0x64 */
  __IO uint32_t CICR;          /*!< RCC clock interrupt clear register,                                      Address offset: 0x68 */
  uint32_t      RESERVED4;     /*!< Reserved,                                                                Address offset: 0x6C */
  __IO uint32_t BDCR;          /*!< RCC backup domain control register,                                      Address offset: 0x70 */
  __IO uint32_t CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74 */
  uint32_t      RESERVED5;     /*!< Reserved,                                                                Address offset: 0x78 */
  __IO uint32_t AHB5RSTR;      /*!< RCC AHB5 peripheral reset register,                                      Address offset: 0x7C */
  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80 */
  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84 */
  __IO uint32_t AHB4RSTR;      /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88 */
  __IO uint32_t APB5RSTR;      /*!< RCC APB5 peripheral reset register,                                      Address offset: 0x8C */
  __IO uint32_t APB1RSTR1;     /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x90 */
  __IO uint32_t APB1RSTR2;     /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x94 */
  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98 */
  __IO uint32_t APB4RSTR;      /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C */
  uint32_t      RESERVED6;     /*!< Reserved,                                                                Address offset: 0xA0 */
  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0xA4 */
  uint32_t      RESERVED7[2];  /*!< Reserved,                                                                Address offset: 0xA8-0xAC */
  __IO uint32_t CKGDISR  ;     /*!< RCC AXI clocks gating disable register,                                  Address offset: 0xB0 */
  uint32_t      RESERVED8[3];  /*!< Reserved,                                                                Address offset: 0xB4-0xBC */
  __IO uint32_t PLL1DIVR2;     /*!< RCC PLL1 dividers configuration register 2,                              Address offset: 0xC0 */
  __IO uint32_t PLL2DIVR2;     /*!< RCC PLL2 dividers configuration register 2,                              Address offset: 0xC4 */
  __IO uint32_t PLL3DIVR2;     /*!< RCC PLL3 dividers configuration register 2,                              Address offset: 0xC8 */
  __IO uint32_t PLL1SSCGR;     /*!< RCC PLL1 spread spectrum clock generator register,                       Address offset: 0xCC */
  __IO uint32_t PLL2SSCGR;     /*!< RCC PLL2 spread spectrum clock generator register,                       Address offset: 0xD0 */
  __IO uint32_t PLL3SSCGR;     /*!< RCC PLL3 spread spectrum clock generator register,                       Address offset: 0xD4 */
  uint32_t      RESERVED9[10]; /*!< Reserved,                                                                Address offset: 0xD8-0xFC */
  __IO uint32_t CKPROTR;       /*!< RCC clock protection register,                                           Address offset: 0x100 */
  uint32_t      RESERVED10[11]; /*!< Reserved,                                                               Address offset: 0x104-0x12C */
  __IO uint32_t RSR;           /*!< RCC reset status register,                                               Address offset: 0x130 */
  __IO uint32_t AHB5ENR;       /*!< RCC AHB5 peripheral clocks enable register,                              Address offset: 0x134 */
  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x138 */
  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x13C */
  __IO uint32_t AHB4ENR;       /*!< RCC AHB4 peripheral clocks enable register,                              Address offset: 0x140 */
  __IO uint32_t APB5ENR;       /*!< RCC APB5 peripheral clocks enable register,                              Address offset: 0x144 */
  __IO uint32_t APB1ENR1;      /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x148 */
  __IO uint32_t APB1ENR2;      /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x14C */
  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x150 */
  __IO uint32_t APB4ENR;       /*!< RCC APB4 peripheral clocks enable register,                              Address offset: 0x154 */
  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x158 */
  __IO uint32_t AHB5LPENR;     /*!< RCC AHB5 peripheral sleep clocks enable register,                        Address offset: 0x15C */
  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral sleep clocks enable register,                        Address offset: 0x160 */
  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral sleep clocks enable register,                        Address offset: 0x164 */
  __IO uint32_t AHB4LPENR;     /*!< RCC AHB4 peripheral sleep clocks enable register,                        Address offset: 0x168 */
  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral sleep clocks enable register,                        Address offset: 0x16C */
  __IO uint32_t APB1LPENR1;    /*!< RCC APB1 peripheral sleep clocks enable register 1,                      Address offset: 0x170 */
  __IO uint32_t APB1LPENR2;    /*!< RCC APB1 peripheral sleep clocks enable register 2,                      Address offset: 0x174 */
  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral sleep clocks enable register,                        Address offset: 0x178 */
  __IO uint32_t APB4LPENR;     /*!< RCC APB4 peripheral sleep clocks enable register,                        Address offset: 0x17C */
  __IO uint32_t APB5LPENR;     /*!< RCC APB5 peripheral sleep clocks enable register,                        Address offset: 0x180 */
} RCC_TypeDef;

/**
  * @brief Random Number Generator
  */
typedef struct
{
  __IO uint32_t CR;      /*!< RNG control register, Address offset: 0x00 */
  __IO uint32_t SR;      /*!< RNG status register,  Address offset: 0x04 */
  __IO uint32_t DR;      /*!< RNG data register,    Address offset: 0x08 */
  uint32_t RESERVED;
  __IO uint32_t HTCR;    /*!< RNG health test configuration register, Address offset: 0x10 */
} RNG_TypeDef;

/*
* @brief RTC Specific device feature definitions
*/
#define RTC_BKP_NB         32U
#define RTC_TAMP_NB        8U

/**
  * @brief Real-Time Clock
  */
typedef struct
{
  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
  __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
  __IO uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x20 */
  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
  __IO uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x58 */
  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
       uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
  __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
  __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
} RTC_TypeDef;

/**
  * @brief SAES Processor
  */
typedef struct
{
  __IO uint32_t CR;              /*!< SAES control register,                      Address offset: 0x00 */
  __IO uint32_t SR;              /*!< SAES status register,                       Address offset: 0x04 */
  __IO uint32_t DINR;            /*!< SAES data input register,                   Address offset: 0x08 */
  __IO uint32_t DOUTR;           /*!< SAES data output register,                  Address offset: 0x0C */
  __IO uint32_t KEYR0;           /*!< SAES key register 0,                        Address offset: 0x10 */
  __IO uint32_t KEYR1;           /*!< SAES key register 1,                        Address offset: 0x14 */
  __IO uint32_t KEYR2;           /*!< SAES key register 2,                        Address offset: 0x18 */
  __IO uint32_t KEYR3;           /*!< SAES key register 3,                        Address offset: 0x1C */
  __IO uint32_t IVR0;            /*!< SAES initialization vector register 0,      Address offset: 0x20 */
  __IO uint32_t IVR1;            /*!< SAES initialization vector register 1,      Address offset: 0x24 */
  __IO uint32_t IVR2;            /*!< SAES initialization vector register 2,      Address offset: 0x28 */
  __IO uint32_t IVR3;            /*!< SAES initialization vector register 3,      Address offset: 0x2C */
  __IO uint32_t KEYR4;           /*!< SAES key register 4,                        Address offset: 0x30 */
  __IO uint32_t KEYR5;           /*!< SAES key register 5,                        Address offset: 0x34 */
  __IO uint32_t KEYR6;           /*!< SAES key register 6,                        Address offset: 0x38 */
  __IO uint32_t KEYR7;           /*!< SAES key register 7,                        Address offset: 0x3C */
  __IO uint32_t SUSP0R;          /*!< SAES Suspend register 0,                    Address offset: 0x40 */
  __IO uint32_t SUSP1R;          /*!< SAES Suspend register 1,                    Address offset: 0x44 */
  __IO uint32_t SUSP2R;          /*!< SAES Suspend register 2,                    Address offset: 0x48 */
  __IO uint32_t SUSP3R;          /*!< SAES Suspend register 3,                    Address offset: 0x4C */
  __IO uint32_t SUSP4R;          /*!< SAES Suspend register 4,                    Address offset: 0x50 */
  __IO uint32_t SUSP5R;          /*!< SAES Suspend register 5,                    Address offset: 0x54 */
  __IO uint32_t SUSP6R;          /*!< SAES Suspend register 6,                    Address offset: 0x58 */
  __IO uint32_t SUSP7R;          /*!< SAES Suspend register 7,                    Address offset: 0x5C */
       uint32_t RESERVED1[168];  /*!< Reserved,                                   Address offset: 0x60 -- 0x2FC */
  __IO uint32_t IER;             /*!< SAES Interrupt Enable Register,             Address offset: 0x300 */
  __IO uint32_t ISR;             /*!< SAES Interrupt Status Register,             Address offset: 0x304 */
  __IO uint32_t ICR;             /*!< SAES Interrupt Clear Register,              Address offset: 0x308 */
} SAES_TypeDef;

/**
  * @brief Serial Audio Interface
  */
typedef struct
{
  __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
  uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
  __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
  __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
} SAI_TypeDef;

typedef struct
{
  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
} SAI_Block_TypeDef;

/**
  * @brief System configuration, boot and security controller
  */
typedef struct
{
  __IO uint32_t BOOTSR;        /*!< SBS Boot Status register,                             Address offset: 0x00 */
  uint32_t      RESERVED1[3];  /*!< Reserved,                                             Address offset: 0x04-0x0C */
  __IO uint32_t HDPLCR;        /*!< SBS Hide Protection Control register,                 Address offset: 0x10 */
  __IO uint32_t HDPLSR;        /*!< SBS Hide Protection Status register,                  Address offset: 0x14 */
  uint32_t      RESERVED2[2];  /*!< Reserved,                                             Address offset: 0x18-0x1C */
  __IO uint32_t DBGCR;         /*!< SBS Debug Control register,                           Address offset: 0x20 */
  __IO uint32_t DBGLOCKR;      /*!< SBS Debug Lock register,                              Address offset: 0x24 */
  uint32_t      RESERVED3[3];  /*!< Reserved,                                             Address offset: 0x28-0x30 */
  __IO uint32_t RSSCMDR;       /*!< SBS RSS Command register,                             Address offset: 0x34 */
  uint32_t      RESERVED4[50]; /*!< Reserved,                                             Address offset: 0x38-0xFC */
  __IO uint32_t PMCR;          /*!< SBS Product Mode & Config register,                   Address offset: 0x100 */
  __IO uint32_t FPUIMR;        /*!< SBS FPU Interrupt Mask register,                      Address offset: 0x104 */
  __IO uint32_t MESR;          /*!< SBS Memory Erase Status register,                     Address offset: 0x108 */
  uint32_t      RESERVED5;     /*!< Reserved,                                             Address offset: 0x10C */
  __IO uint32_t CCCSR;         /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */
  __IO uint32_t CCVALR;        /*!< SBS IO Compensation Cell Value register,              Address offset: 0x114 */
  __IO uint32_t CCSWVALR;      /*!< SBS IO Compensation Cell Software Value register,     Address offset: 0x118 */
  uint32_t      RESERVED6;     /*!< Reserved,                                             Address offset: 0x11C */
  __IO uint32_t BKLOCKR;       /*!< SBS Break Lockup register,                            Address offset: 0x120 */
  uint32_t      RESERVED7[3];  /*!< Reserved,                                             Address offset: 0x124-0x12C */
  __IO uint32_t EXTICR[4];     /*!< SBS External Interrupt Configuration registers,       Address offset: 0x130-0x13C */
} SBS_TypeDef;

/**
  * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface
  */
typedef struct
{
  __IO uint32_t POWER;        /*!< SDMMC Power control register,                Address offset : 0x000         */
  __IO uint32_t CLKCR;        /*!< SDMMC Clock control register,                Address offset : 0x004         */
  __IO uint32_t ARG;          /*!< SDMMC Argument register,                     Address offset : 0x008         */
  __IO uint32_t CMD;          /*!< SDMMC Command register,                      Address offset : 0x00C         */
  __IO uint32_t RESPCMD;      /*!< SDMMC Command response register,             Address offset : 0x010         */
  __IO uint32_t RESP1;        /*!< SDMMC Response 1 register,                   Address offset : 0x014         */
  __IO uint32_t RESP2;        /*!< SDMMC Response 2 register,                   Address offset : 0x018         */
  __IO uint32_t RESP3;        /*!< SDMMC Response 3 register,                   Address offset : 0x01C         */
  __IO uint32_t RESP4;        /*!< SDMMC Response 4 register,                   Address offset : 0x020         */
  __IO uint32_t DTIMER;       /*!< SDMMC Data timer register,                   Address offset : 0x024         */
  __IO uint32_t DLEN;         /*!< SDMMC Data length register,                  Address offset : 0x028         */
  __IO uint32_t DCTRL;        /*!< SDMMC Data control register,                 Address offset : 0x02C         */
  __IO uint32_t DCOUNT;       /*!< SDMMC Data counter register,                 Address offset : 0x030         */
  __IO uint32_t STA;          /*!< SDMMC Status register,                       Address offset : 0x034         */
  __IO uint32_t ICR;          /*!< SDMMC Interrupt clear register,              Address offset : 0x038         */
  __IO uint32_t MASK;         /*!< SDMMC Mask register,                         Address offset : 0x03C         */
  __IO uint32_t ACKTIME;      /*!< SDMMC Acknowledgement timer register,        Address offset : 0x040         */
       uint32_t RESERVED0[3]; /*!< Reserved,                                    Address offset : 0x044 - 0x04C */
  __IO uint32_t IDMACTRL;     /*!< SDMMC IDMA control register,                 Address offset : 0x050         */
  __IO uint32_t IDMABSIZE;    /*!< SDMMC IDMA buffer size register,             Address offset : 0x054         */
  __IO uint32_t IDMABASER;    /*!< SDMMC IDMA buffer base address register,     Address offset : 0x058         */
       uint32_t RESERVED1[2]; /*!< Reserved,                                    Address offset : 0x05C - 0x060 */
  __IO uint32_t IDMALAR;      /*!< SDMMC IDMA linked list address register,     Address offset : 0x064         */
  __IO uint32_t IDMABAR;      /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068         */
       uint32_t RESERVED2[5]; /*!< Reserved,                                    Address offset : 0x06C - 0x07C */
  __IO uint32_t FIFO;         /*!< SDMMC data FIFO register,                    Address offset : 0x080         */
} SDMMC_TypeDef;

/**
  * @brief SPDIF-RX Interface
  */
typedef struct
{
  __IO uint32_t CR;          /*!< Control register,                   Address offset: 0x00 */
  __IO uint32_t IMR;         /*!< Interrupt mask register,            Address offset: 0x04 */
  __IO uint32_t SR;          /*!< Status register,                    Address offset: 0x08 */
  __IO uint32_t IFCR;        /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
  __IO uint32_t DR;          /*!< Data input register,                Address offset: 0x10 */
  __IO uint32_t CSR;         /*!< Channel Status register,            Address offset: 0x14 */
  __IO uint32_t DIR;         /*!< Debug Information register,         Address offset: 0x18 */
} SPDIFRX_TypeDef;

/**
  * @brief SPI
  */
typedef struct
{
  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                 Address offset: 0x00 */
  __IO uint32_t CR2;           /*!< SPI Control register 2,                     Address offset: 0x04 */
  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,               Address offset: 0x08 */
  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,               Address offset: 0x0C */
  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,          Address offset: 0x10 */
  __IO uint32_t SR;            /*!< SPI/I2S Status register,                    Address offset: 0x14 */
  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
  uint32_t      RESERVED0;     /*!< Reserved,                                   Address offset: 0x1C */
  __IO uint32_t TXDR;          /*!< SPI Transmit data register,                 Address offset: 0x20 */
  uint32_t      RESERVED1[3];  /*!< Reserved,                              Address offset: 0x24-0x2C */
  __IO uint32_t RXDR;          /*!< SPI/I2S data register,                      Address offset: 0x30 */
  uint32_t      RESERVED2[3];  /*!< Reserved,                              Address offset: 0x34-0x3C */
  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                Address offset: 0x40 */
  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,               Address offset: 0x44 */
  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                  Address offset: 0x48 */
  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                 Address offset: 0x4C */
  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                 Address offset: 0x50 */
} SPI_TypeDef;

/**
  * @brief Tamper and backup registers
  */
typedef struct
{
  __IO uint32_t CR1;           /*!< TAMP configuration register 1,                    Address offset: 0x00 */
  __IO uint32_t CR2;           /*!< TAMP configuration register 2,                    Address offset: 0x04 */
  __IO uint32_t CR3;           /*!< TAMP configuration register 3,                    Address offset: 0x08 */
  __IO uint32_t FLTCR;         /*!< TAMP filter control register,                     Address offset: 0x0C */
  __IO uint32_t ATCR1;         /*!< TAMP filter control register 1                    Address offset: 0x10 */
  __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                 Address offset: 0x14 */
  __IO uint32_t ATOR;          /*!< TAMP active tamper output register,               Address offset: 0x18 */
  __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,                   Address offset: 0x1C */
  __IO uint32_t CFGR;          /*!< TAMP configuration control register,              Address offset: 0x20 */
  __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,             Address offset: 0x24 */
       uint32_t RESERVED2;     /*!< Reserved,                                         Address offset: 0x28 */
  __IO uint32_t IER;           /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
  __IO uint32_t SR;            /*!< TAMP status register,                             Address offset: 0x30 */
  __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
  __IO uint32_t RESERVED3;     /*!< Reserved,                                         Address offset: 0x38 */
  __IO uint32_t SCR;           /*!< TAMP status clear register,                       Address offset: 0x3C */
  __IO uint32_t COUNT1R;       /*!< TAMP monotonic counter 1 register,                Address offset: 0x40 */
       uint32_t RESERVED4[4];  /*!< Reserved,                                         Address offset: 0x43 -- 0x50 */
  __IO uint32_t RPCFGR;        /*!< TAMP resources protection configuration register, Address offset: 0x54 */
       uint32_t RESERVED5[42]; /*!< Reserved,                                         Address offset: 0x58 -- 0xFC */
  __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                           Address offset: 0x100 */
  __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                           Address offset: 0x104 */
  __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                           Address offset: 0x108 */
  __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                           Address offset: 0x10C */
  __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                           Address offset: 0x110 */
  __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                           Address offset: 0x114 */
  __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                           Address offset: 0x118 */
  __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                           Address offset: 0x11C */
  __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                           Address offset: 0x120 */
  __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                           Address offset: 0x124 */
  __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                          Address offset: 0x128 */
  __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                          Address offset: 0x12C */
  __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                          Address offset: 0x130 */
  __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                          Address offset: 0x134 */
  __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                          Address offset: 0x138 */
  __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                          Address offset: 0x13C */
  __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                          Address offset: 0x140 */
  __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                          Address offset: 0x144 */
  __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                          Address offset: 0x148 */
  __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                          Address offset: 0x14C */
  __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                          Address offset: 0x150 */
  __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                          Address offset: 0x154 */
  __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                          Address offset: 0x158 */
  __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                          Address offset: 0x15C */
  __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                          Address offset: 0x160 */
  __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                          Address offset: 0x164 */
  __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                          Address offset: 0x168 */
  __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                          Address offset: 0x16C */
  __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                          Address offset: 0x170 */
  __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                          Address offset: 0x174 */
  __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                          Address offset: 0x178 */
  __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                          Address offset: 0x17C */
} TAMP_TypeDef;

/**
  * @brief TIM
  */
typedef struct
{
  __IO uint32_t CR1;            /*!< TIM control register 1,                   Address offset: 0x00  */
  __IO uint32_t CR2;            /*!< TIM control register 2,                   Address offset: 0x04  */
  __IO uint32_t SMCR;           /*!< TIM slave mode control register,          Address offset: 0x08  */
  __IO uint32_t DIER;           /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C  */
  __IO uint32_t SR;             /*!< TIM status register,                      Address offset: 0x10  */
  __IO uint32_t EGR;            /*!< TIM event generation register,            Address offset: 0x14  */
  __IO uint32_t CCMR1;          /*!< TIM capture/compare mode register 1,      Address offset: 0x18  */
  __IO uint32_t CCMR2;          /*!< TIM capture/compare mode register 2,      Address offset: 0x1C  */
  __IO uint32_t CCER;           /*!< TIM capture/compare enable register,      Address offset: 0x20  */
  __IO uint32_t CNT;            /*!< TIM counter register,                     Address offset: 0x24  */
  __IO uint32_t PSC;            /*!< TIM prescaler,                            Address offset: 0x28  */
  __IO uint32_t ARR;            /*!< TIM auto-reload register,                 Address offset: 0x2C  */
  __IO uint32_t RCR;            /*!< TIM repetition counter register,          Address offset: 0x30  */
  __IO uint32_t CCR1;           /*!< TIM capture/compare register 1,           Address offset: 0x34  */
  __IO uint32_t CCR2;           /*!< TIM capture/compare register 2,           Address offset: 0x38  */
  __IO uint32_t CCR3;           /*!< TIM capture/compare register 3,           Address offset: 0x3C  */
  __IO uint32_t CCR4;           /*!< TIM capture/compare register 4,           Address offset: 0x40  */
  __IO uint32_t BDTR;           /*!< TIM break and dead-time register,         Address offset: 0x44  */
  __IO uint32_t CCR5;           /*!< TIM capture/compare register 5,           Address offset: 0x48  */
  __IO uint32_t CCR6;           /*!< TIM capture/compare register 6,           Address offset: 0x4C  */
  __IO uint32_t CCMR3;          /*!< TIM capture/compare mode register 3,      Address offset: 0x50  */
  __IO uint32_t DTR2;           /*!< TIM deadtime register 2,                  Address offset: 0x54  */
  __IO uint32_t ECR;            /*!< TIM encoder control register,             Address offset: 0x58  */
  __IO uint32_t TISEL;          /*!< TIM Input Selection register,             Address offset: 0x5C  */
  __IO uint32_t AF1;            /*!< TIM alternate function option register 1, Address offset: 0x60  */
  __IO uint32_t AF2;            /*!< TIM alternate function option register 2, Address offset: 0x64  */
       uint32_t RESERVED0[221]; /*!< Reserved,                                 Address offset: 0x68  */
  __IO uint32_t DCR;            /*!< TIM DMA control register,                 Address offset: 0x3DC */
  __IO uint32_t DMAR;           /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
} TIM_TypeDef;


/**
  * @brief UCPD
  */
typedef struct
{
  __IO uint32_t CFG1;        /*!< UCPD configuration register 1,            Address offset: 0x00 */
  __IO uint32_t CFG2;        /*!< UCPD configuration register 2,            Address offset: 0x04 */
  __IO uint32_t CFG3;        /*!< UCPD configuration register 3,            Address offset: 0x08 */
  __IO uint32_t CR;          /*!< UCPD control register,                    Address offset: 0x0C */
  __IO uint32_t IMR;         /*!< UCPD interrupt mask register,             Address offset: 0x10 */
  __IO uint32_t SR;          /*!< UCPD status register,                     Address offset: 0x14 */
  __IO uint32_t ICR;         /*!< UCPD interrupt flag clear register        Address offset: 0x18 */
  __IO uint32_t TX_ORDSET;   /*!< UCPD Tx ordered set type register,        Address offset: 0x1C */
  __IO uint32_t TX_PAYSZ;    /*!< UCPD Tx payload size register,            Address offset: 0x20 */
  __IO uint32_t TXDR;        /*!< UCPD Tx data register,                    Address offset: 0x24 */
  __IO uint32_t RX_ORDSET;   /*!< UCPD Rx ordered set type register,        Address offset: 0x28 */
  __IO uint32_t RX_PAYSZ;    /*!< UCPD Rx payload size register,            Address offset: 0x2C */
  __IO uint32_t RXDR;        /*!< UCPD Rx data register,                    Address offset: 0x30 */
  __IO uint32_t RX_ORDEXT1;  /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
  __IO uint32_t RX_ORDEXT2;  /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;

/**
  * @brief USB_OTG_Core_register
  */
typedef struct
{
  __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
  __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
  __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
  __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
  __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
  __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
  __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
  __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
  __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
  __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
  __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
  __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
  __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
  __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
  __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
  __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
  __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
  __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
  __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
  __IO uint32_t  Reserved6;          /*!< Reserved,                                  Address offset: 050h */
  __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
  __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
  __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
  __IO uint32_t  Reserved43[39];     /*!< Reserved,                                  Address offset: 058h */
  __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
  __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
} USB_OTG_GlobalTypeDef;

/**
  * @brief USB_OTG_device_Registers
  */
typedef struct
{
  __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
  __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
  __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
  uint32_t Reserved0C;               /*!< Reserved,                     Address offset: 80Ch */
  __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
  __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
  __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
  __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
  uint32_t  Reserved20;              /*!< Reserved,                     Address offset: 820h */
  uint32_t Reserved9;                /*!< Reserved,                     Address offset: 824h */
  __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
  __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
  __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
  __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
  __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
  __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
  uint32_t Reserved40;               /*!< dedicated EP mask,            Address offset: 840h */
  __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
  uint32_t  Reserved44[15];          /*!< Reserved,                     Address offset: 844-87Ch */
  __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
} USB_OTG_DeviceTypeDef;


/**
  * @brief USB_OTG_IN_Endpoint-Specific_Register
  */
typedef struct
{
  __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
  __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
  __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
  __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
  __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
  __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;

/**
  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
  */
typedef struct
{
  __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
  __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
  __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
  __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
  __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
} USB_OTG_OUTEndpointTypeDef;

/**
  * @brief USB_OTG_Host_Mode_Register_Structures
  */
typedef struct
{
  __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
  uint32_t Reserved40C;               /*!< Reserved,                                 Address offset: 40Ch */
  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
} USB_OTG_HostTypeDef;

/**
  * @brief USB_OTG_Host_Channel_Specific_Registers
  */
typedef struct
{
  __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
  __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
  __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
  __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
  __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
  __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
  uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
} USB_OTG_HostChannelTypeDef;

/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
typedef struct
{
  __IO uint32_t CR1;         /*!< USART Control register 1,                    Address offset: 0x00 */
  __IO uint32_t CR2;         /*!< USART Control register 2,                    Address offset: 0x04 */
  __IO uint32_t CR3;         /*!< USART Control register 3,                    Address offset: 0x08 */
  __IO uint32_t BRR;         /*!< USART Baud rate register,                    Address offset: 0x0C */
  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,     Address offset: 0x10 */
  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,            Address offset: 0x14 */
  __IO uint32_t RQR;         /*!< USART Request register,                      Address offset: 0x18 */
  __IO uint32_t ISR;         /*!< USART Interrupt and status register,         Address offset: 0x1C */
  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,         Address offset: 0x20 */
  __IO uint32_t RDR;         /*!< USART Receive Data register,                 Address offset: 0x24 */
  __IO uint32_t TDR;         /*!< USART Transmit Data register,                Address offset: 0x28 */
  __IO uint32_t PRESC;       /*!< USART Prescaler register,                    Address offset: 0x2C */
} USART_TypeDef;

/**
  * @brief Window Watchdog
  */
typedef struct
{
  __IO uint32_t CR;          /*!< WWDG Control register,              Address offset: 0x00 */
  __IO uint32_t CFR;         /*!< WWDG Configuration register,        Address offset: 0x04 */
  __IO uint32_t SR;          /*!< WWDG Status register,               Address offset: 0x08 */
} WWDG_TypeDef;

/*@}*/ /* end of group STM32H7RSxx_peripherals */

/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */

/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr
  * @{
  */
#define ITCM_BASE                       0x00000000UL  /*!< ITCM base address */
#define FLASH_BASE                      0x08000000UL  /*!< User Flash address */
#define OTP_AREA_BASE                   0x08FFF000UL  /*!< OTP Area base address */
#define ENGI_BYTES_BASE                 0x52002800UL  /*!< Engi Bytes */
#define SYSTEM_FLASH_BASE               0x1FF00000UL  /*!< System Flash base address */
#define DTCM_BASE                       0x20000000UL  /*!< DTCM base address  */
#define SRAM1_AXI_BASE                  0x24000000UL  /*!< SRAM1 base address - accessible over AXI */
#define SRAM2_AXI_BASE                  0x24020000UL  /*!< SRAM2 base address - accessible over AXI */
#define SRAM3_AXI_BASE                  0x24040000UL  /*!< SRAM3 base address - accessible over AXI */
#define SRAM4_AXI_BASE                  0x24060000UL  /*!< SRAM4 base address - accessible over AXI */

#define GFXMMU_VIRTUAL_BUFFER0_BASE     0x25000000UL  /*!< GFXMMU virtual buffer 0 base address */
#define GFXMMU_VIRTUAL_BUFFER1_BASE     0x25400000UL  /*!< GFXMMU virtual buffer 1 base address */
#define GFXMMU_VIRTUAL_BUFFER2_BASE     0x25800000UL  /*!< GFXMMU virtual buffer 2 base address */
#define GFXMMU_VIRTUAL_BUFFER3_BASE     0x25C00000UL  /*!< GFXMMU virtual buffer 3 base address */

#define SRAM1_AHB_BASE                  0x30000000UL  /*!< SRAM1 base address */
#define SRAM2_AHB_BASE                  0x30004000UL  /*!< SRAM2 base address */
#define BKPSRAM_BASE                    0x38800000UL  /*!< Backup SRAM */

#define PERIPH_BASE                     0x40000000UL  /*!< AHB and APB Peripherals base address */
#define XSPI2_BASE                      0x70000000UL  /*!< XSPI2 base address */
#define XSPI1_BASE                      0x90000000UL  /*!< XSPI1 base address */

/*!< Internal memory size */
#define ITCM_SIZE                       0x00010000UL  /*!< 64 KB default, can be increased up to 192 KB */
#define DTCM_SIZE                       0x00010000UL  /*!< 64 KB default, can be increased up to 192 KB */
#define FLASH_SIZE                      0x00010000UL  /*!< 64 KB */
#define SRAM1_AXI_SIZE                  0x00020000UL  /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */
#define SRAM2_AXI_SIZE                  0x00020000UL  /*!< 128 KB */
#define SRAM3_AXI_SIZE                  0x00020000UL  /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */
#define SRAM4_AXI_SIZE                  0x00012000UL  /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */
#define SRAM_AHB_SIZE                   0x00004000UL  /*!< Both AHB SRAMs are 16 KB */
#define BKPSRAM_SIZE                    0x00001000UL  /*!< 4 KB */

/*!< OTP Area size */
#define OTP_SIZE               0x400U /* 1 KB */

/*!< Peripheral memory map */
#define APB1PERIPH_BASE                 PERIPH_BASE
#define AHB1PERIPH_BASE                 (PERIPH_BASE + 0x00020000UL)
#define APB2PERIPH_BASE                 (PERIPH_BASE + 0x02000000UL)
#define AHB2PERIPH_BASE                 (PERIPH_BASE + 0x08000000UL)
#define AHB3PERIPH_BASE                 (PERIPH_BASE + 0x08020000UL)
#define APB5PERIPH_BASE                 (PERIPH_BASE + 0x10000000UL)
#define AHB5PERIPH_BASE                 (PERIPH_BASE + 0x12000000UL)
#define APB4PERIPH_BASE                 (PERIPH_BASE + 0x18000000UL)
#define AHB4PERIPH_BASE                 (PERIPH_BASE + 0x18020000UL)

/*!< APB1 peripherals */
#define TIM2_BASE                       (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE                       (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE                       (APB1PERIPH_BASE + 0x0800UL)
#define TIM5_BASE                       (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE                       (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE                       (APB1PERIPH_BASE + 0x1400UL)
#define TIM12_BASE                      (APB1PERIPH_BASE + 0x1800UL)
#define TIM13_BASE                      (APB1PERIPH_BASE + 0x1C00UL)
#define TIM14_BASE                      (APB1PERIPH_BASE + 0x2000UL)
#define LPTIM1_BASE                     (APB1PERIPH_BASE + 0x2400UL)
#define WWDG_BASE                       (APB1PERIPH_BASE + 0x2C00UL)
#define SPI2_BASE                       (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE                       (APB1PERIPH_BASE + 0x3C00UL)
#define SPDIFRX_BASE                    (APB1PERIPH_BASE + 0x4000UL)
#define USART2_BASE                     (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE                     (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE                      (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE                      (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE                       (APB1PERIPH_BASE + 0x5400UL)
#define I3C1_BASE                       (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE                       (APB1PERIPH_BASE + 0x5800UL)
#define I2C3_BASE                       (APB1PERIPH_BASE + 0x5C00UL)
#define CEC_BASE                        (APB1PERIPH_BASE + 0x6C00UL)
#define UART7_BASE                      (APB1PERIPH_BASE + 0x7800UL)
#define UART8_BASE                      (APB1PERIPH_BASE + 0x7C00UL)
#define CRS_BASE                        (APB1PERIPH_BASE + 0x8400UL)
#define MDIOS_BASE                      (APB1PERIPH_BASE + 0x9400UL)
#define FDCAN1_BASE                     (APB1PERIPH_BASE + 0xA000UL)
#define FDCAN_CONFIG_BASE               (APB1PERIPH_BASE + 0xA100UL)  /*!< FDCAN configuration registers base address */
#define FDCAN2_BASE                     (APB1PERIPH_BASE + 0xA400UL)
#define SRAMCAN_BASE                    (APB1PERIPH_BASE + 0xAC00UL)
#define UCPD1_BASE                      (APB1PERIPH_BASE + 0xEC00UL)

/*!< APB2 peripherals */
#define TIM1_BASE                       (APB2PERIPH_BASE + 0x0000UL)
#define USART1_BASE                     (APB2PERIPH_BASE + 0x1000UL)
#define SPI1_BASE                       (APB2PERIPH_BASE + 0x3000UL)
#define SPI4_BASE                       (APB2PERIPH_BASE + 0x3400UL)
#define TIM15_BASE                      (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE                      (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE                      (APB2PERIPH_BASE + 0x4800UL)
#define TIM9_BASE                       (APB2PERIPH_BASE + 0x4C00UL)
#define SPI5_BASE                       (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE                       (APB2PERIPH_BASE + 0x5800UL)
#define SAI1_Block_A_BASE               (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE               (SAI1_BASE + 0x0024UL)
#define SAI2_BASE                       (APB2PERIPH_BASE + 0x5C00UL)
#define SAI2_Block_A_BASE               (SAI2_BASE + 0x0004UL)
#define SAI2_Block_B_BASE               (SAI2_BASE + 0x0024UL)

/*!< AHB1 peripherals */
#define GPDMA1_BASE                     (AHB1PERIPH_BASE + 0x1000UL)
#define GPDMA1_Channel0_BASE            (GPDMA1_BASE + 0x0050UL)
#define GPDMA1_Channel1_BASE            (GPDMA1_BASE + 0x00D0UL)
#define GPDMA1_Channel2_BASE            (GPDMA1_BASE + 0x0150UL)
#define GPDMA1_Channel3_BASE            (GPDMA1_BASE + 0x01D0UL)
#define GPDMA1_Channel4_BASE            (GPDMA1_BASE + 0x0250UL)
#define GPDMA1_Channel5_BASE            (GPDMA1_BASE + 0x02D0UL)
#define GPDMA1_Channel6_BASE            (GPDMA1_BASE + 0x0350UL)
#define GPDMA1_Channel7_BASE            (GPDMA1_BASE + 0x03D0UL)
#define GPDMA1_Channel8_BASE            (GPDMA1_BASE + 0x0450UL)
#define GPDMA1_Channel9_BASE            (GPDMA1_BASE + 0x04D0UL)
#define GPDMA1_Channel10_BASE           (GPDMA1_BASE + 0x0550UL)
#define GPDMA1_Channel11_BASE           (GPDMA1_BASE + 0x05D0UL)
#define GPDMA1_Channel12_BASE           (GPDMA1_BASE + 0x0650UL)
#define GPDMA1_Channel13_BASE           (GPDMA1_BASE + 0x06D0UL)
#define GPDMA1_Channel14_BASE           (GPDMA1_BASE + 0x0750UL)
#define GPDMA1_Channel15_BASE           (GPDMA1_BASE + 0x07D0UL)
#define ADC1_BASE                       (AHB1PERIPH_BASE + 0x2000UL)
#define ADC2_BASE                       (AHB1PERIPH_BASE + 0x2100UL)
#define ADC12_COMMON_BASE               (AHB1PERIPH_BASE + 0x2300UL)
#define ETH_BASE                        (AHB1PERIPH_BASE + 0x8000UL)
#define ETH_MAC_BASE                    (ETH_BASE)
#define ADF1_BASE                       (AHB1PERIPH_BASE + 0xF000UL)
#define ADF1_Filter0_BASE               (ADF1_BASE + 0x0080UL)
#define USB_OTG_HS_PERIPH_BASE          (AHB1PERIPH_BASE + 0x20000UL)
#define USB_OTG_FS_PERIPH_BASE          (AHB1PERIPH_BASE + 0x60000UL)

/*!< AHB2 peripherals */
#define PSSI_BASE                       (AHB2PERIPH_BASE + 0x0400UL)
#define SDMMC2_BASE                     (AHB2PERIPH_BASE + 0x2400UL)
#define DLYB_SDMMC2_BASE                (AHB2PERIPH_BASE + 0x2800UL)
#define CORDIC_BASE                     (AHB2PERIPH_BASE + 0x4400UL)

/*!< AHB3 peripherals */
#define RNG_BASE                        AHB3PERIPH_BASE
#define HASH_BASE                       (AHB3PERIPH_BASE + 0x0400UL)
#define HASH_DIGEST_BASE                (AHB3PERIPH_BASE + 0x0710UL)
#define CRYP_BASE                       (AHB3PERIPH_BASE + 0x0800UL)
#define SAES_BASE                       (AHB3PERIPH_BASE + 0x1000UL)
#define PKA_BASE                        (AHB3PERIPH_BASE + 0x2000UL)

/*!< APB5 peripherals */
#define DCMIPP_BASE                     (APB5PERIPH_BASE + 0x2000UL)
#define GFXTIM_BASE                     (APB5PERIPH_BASE + 0x4000UL)

/*!< AHB5 peripherals */
#define HPDMA1_BASE                     AHB5PERIPH_BASE
#define HPDMA1_Channel0_BASE            (HPDMA1_BASE + 0x0050UL)
#define HPDMA1_Channel1_BASE            (HPDMA1_BASE + 0x00D0UL)
#define HPDMA1_Channel2_BASE            (HPDMA1_BASE + 0x0150UL)
#define HPDMA1_Channel3_BASE            (HPDMA1_BASE + 0x01D0UL)
#define HPDMA1_Channel4_BASE            (HPDMA1_BASE + 0x0250UL)
#define HPDMA1_Channel5_BASE            (HPDMA1_BASE + 0x02D0UL)
#define HPDMA1_Channel6_BASE            (HPDMA1_BASE + 0x0350UL)
#define HPDMA1_Channel7_BASE            (HPDMA1_BASE + 0x03D0UL)
#define HPDMA1_Channel8_BASE            (HPDMA1_BASE + 0x0450UL)
#define HPDMA1_Channel9_BASE            (HPDMA1_BASE + 0x04D0UL)
#define HPDMA1_Channel10_BASE           (HPDMA1_BASE + 0x0550UL)
#define HPDMA1_Channel11_BASE           (HPDMA1_BASE + 0x05D0UL)
#define HPDMA1_Channel12_BASE           (HPDMA1_BASE + 0x0650UL)
#define HPDMA1_Channel13_BASE           (HPDMA1_BASE + 0x06D0UL)
#define HPDMA1_Channel14_BASE           (HPDMA1_BASE + 0x0750UL)
#define HPDMA1_Channel15_BASE           (HPDMA1_BASE + 0x07D0UL)
#define DMA2D_BASE                      (AHB5PERIPH_BASE + 0x1000UL)
#define FLASH_R_BASE                    (AHB5PERIPH_BASE + 0x2000UL)
#define JPEG_BASE                       (AHB5PERIPH_BASE + 0x3000UL)
#define FMC_R_BASE                      (AHB5PERIPH_BASE + 0x4000UL)
#define FMC_Bank1_R_BASE                (FMC_R_BASE + 0x0000UL)
#define FMC_Bank1E_R_BASE               (FMC_R_BASE + 0x0104UL)
#define FMC_Bank3_R_BASE                (FMC_R_BASE + 0x0080UL)
#define FMC_Bank5_6_R_BASE              (FMC_R_BASE + 0x0140UL)
#define XSPI1_R_BASE                    (AHB5PERIPH_BASE + 0x5000UL)
#define SDMMC1_BASE                     (AHB5PERIPH_BASE + 0x7000UL)
#define DLYB_SDMMC1_BASE                (AHB5PERIPH_BASE + 0x8000UL)
#define RAMECC1_BASE                    (AHB5PERIPH_BASE + 0x9000UL)
#define RAMECC1_Monitor0_BASE           (RAMECC1_BASE + 0x20UL)
#define RAMECC1_Monitor1_BASE           (RAMECC1_BASE + 0x40UL)
#define RAMECC1_Monitor2_BASE           (RAMECC1_BASE + 0x60UL)
#define RAMECC1_Monitor3_BASE           (RAMECC1_BASE + 0x80UL)
#define RAMECC1_Monitor4_BASE           (RAMECC1_BASE + 0xA0UL)
#define XSPI2_R_BASE                    (AHB5PERIPH_BASE + 0xA000UL)
#define XSPIM_BASE                      (AHB5PERIPH_BASE + 0xB400UL)
#define MCE1_BASE                       (AHB5PERIPH_BASE + 0xB800UL)
#define MCE1_REGION1_BASE               (MCE1_BASE + 0x040UL)
#define MCE1_REGION2_BASE               (MCE1_BASE + 0x050UL)
#define MCE1_REGION3_BASE               (MCE1_BASE + 0x060UL)
#define MCE1_REGION4_BASE               (MCE1_BASE + 0x070UL)
#define MCE1_CONTEXT1_BASE              (MCE1_BASE + 0x240UL)
#define MCE1_CONTEXT2_BASE              (MCE1_BASE + 0x270UL)
#define MCE2_BASE                       (AHB5PERIPH_BASE + 0xBC00UL)
#define MCE2_REGION1_BASE               (MCE2_BASE + 0x040UL)
#define MCE2_REGION2_BASE               (MCE2_BASE + 0x050UL)
#define MCE2_REGION3_BASE               (MCE2_BASE + 0x060UL)
#define MCE2_REGION4_BASE               (MCE2_BASE + 0x070UL)
#define MCE3_BASE                       (AHB5PERIPH_BASE + 0xC000UL)
#define MCE3_REGION1_BASE               (MCE3_BASE + 0x040UL)
#define MCE3_REGION2_BASE               (MCE3_BASE + 0x050UL)
#define MCE3_REGION3_BASE               (MCE3_BASE + 0x060UL)
#define MCE3_REGION4_BASE               (MCE3_BASE + 0x070UL)
#define GFXMMU_BASE                     (AHB5PERIPH_BASE + 0x010000UL)

/*!< APB4 peripherals */
#define EXTI_BASE                       APB4PERIPH_BASE
#define SBS_BASE                        (APB4PERIPH_BASE + 0x0400UL)
#define LPUART1_BASE                    (APB4PERIPH_BASE + 0x0C00UL)
#define SPI6_BASE                       (APB4PERIPH_BASE + 0x1400UL)
#define LPTIM2_BASE                     (APB4PERIPH_BASE + 0x2400UL)
#define LPTIM3_BASE                     (APB4PERIPH_BASE + 0x2800UL)
#define LPTIM4_BASE                     (APB4PERIPH_BASE + 0x2C00UL)
#define LPTIM5_BASE                     (APB4PERIPH_BASE + 0x3000UL)
#define VREFBUF_BASE                    (APB4PERIPH_BASE + 0x3C00UL)
#define RTC_BASE                        (APB4PERIPH_BASE + 0x4000UL)
#define TAMP_BASE                       (APB4PERIPH_BASE + 0x4400UL)
#define IWDG_BASE                       (APB4PERIPH_BASE + 0x4800UL)
#define DTS_BASE                        (APB4PERIPH_BASE + 0x6800UL)

/*!< AHB4 peripherals */
#define GPIOA_BASE                      AHB4PERIPH_BASE
#define GPIOB_BASE                      (AHB4PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE                      (AHB4PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE                      (AHB4PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE                      (AHB4PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE                      (AHB4PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE                      (AHB4PERIPH_BASE + 0x1800UL)
#define GPIOH_BASE                      (AHB4PERIPH_BASE + 0x1C00UL)
#define GPIOM_BASE                      (AHB4PERIPH_BASE + 0x3000UL)
#define GPION_BASE                      (AHB4PERIPH_BASE + 0x3400UL)
#define GPIOO_BASE                      (AHB4PERIPH_BASE + 0x3800UL)
#define GPIOP_BASE                      (AHB4PERIPH_BASE + 0x3C00UL)
#define RCC_BASE                        (AHB4PERIPH_BASE + 0x4400UL)
#define PWR_BASE                        (AHB4PERIPH_BASE + 0x4800UL)
#define CRC_BASE                        (AHB4PERIPH_BASE + 0x4C00UL)
#define RAMECC2_BASE                    (AHB4PERIPH_BASE + 0x7000UL)
#define RAMECC2_Monitor1_BASE           (RAMECC2_BASE + 0x40UL)

/*!< Debug MCU registers base address */
#define DBGMCU_BASE                     (0x5C001000UL)

/*!< AXIM registers base address */
#define AXIM_BASE                        (0xBFF00000UL)
#define AXIM_ASIB1_BASE                  (AXIM_BASE + 0x42000UL)
#define AXIM_ASIB2_BASE                  (AXIM_BASE + 0x43000UL)
#define AXIM_ASIB3_BASE                  (AXIM_BASE + 0x44000UL)
#define AXIM_ASIB4_BASE                  (AXIM_BASE + 0x45000UL)
#define AXIM_ASIB5_BASE                  (AXIM_BASE + 0x46000UL)
#define AXIM_ASIB6_BASE                  (AXIM_BASE + 0x47000UL)
#define AXIM_ASIB7_BASE                  (AXIM_BASE + 0x48000UL)
#define AXIM_ASIB8_BASE                  (AXIM_BASE + 0x49000UL)
#define AXIM_ASIB9_BASE                  (AXIM_BASE + 0x4A000UL)
#define AXIM_ASIB10_BASE                 (AXIM_BASE + 0x4B000UL)
#define AXIM_ASIB11_BASE                 (AXIM_BASE + 0x4C000UL)
#define AXIM_AMIB1_BASE                  (AXIM_BASE + 0x02000UL)
#define AXIM_AMIB2_BASE                  (AXIM_BASE + 0x03000UL)
#define AXIM_AMIB3_BASE                  (AXIM_BASE + 0x04000UL)
#define AXIM_AMIB4_BASE                  (AXIM_BASE + 0x05000UL)
#define AXIM_AMIB5_BASE                  (AXIM_BASE + 0x06000UL)
#define AXIM_AMIB6_BASE                  (AXIM_BASE + 0x07000UL)
#define AXIM_AMIB7_BASE                  (AXIM_BASE + 0x08000UL)
#define AXIM_AMIB8_BASE                  (AXIM_BASE + 0x09000UL)
#define AXIM_AMIB9_BASE                  (AXIM_BASE + 0x0A000UL)
#define AXIM_AMIB10_BASE                 (AXIM_BASE + 0x0B000UL)

/*!< Unique device ID register base address */
#define UID_BASE                        (0x08FFF800UL)

/*!< Flash size data register base address  */
#define FLASHSIZE_BASE                  (0x08FFF80CUL)

/*!< Package data register base address     */
#define PACKAGE_BASE                    (0x08FFF80CUL)

/* USB OTG registers base addresses */
#define USB_OTG_GLOBAL_BASE                  (0x0000UL)
#define USB_OTG_DEVICE_BASE                  (0x0800UL)
#define USB_OTG_IN_ENDPOINT_BASE             (0x0900UL)
#define USB_OTG_OUT_ENDPOINT_BASE            (0x0B00UL)
#define USB_OTG_EP_REG_SIZE                  (0x0020UL)
#define USB_OTG_HOST_BASE                    (0x0400UL)
#define USB_OTG_HOST_PORT_BASE               (0x0440UL)
#define USB_OTG_HOST_CHANNEL_BASE            (0x0500UL)
#define USB_OTG_HOST_CHANNEL_SIZE            (0x0020UL)
#define USB_OTG_PCGCCTL_BASE                 (0x0E00UL)
#define USB_OTG_FIFO_BASE                    (0x1000UL)
#define USB_OTG_FIFO_SIZE                    (0x1000UL)

/*!< Root Secure Service Library */
/************ RSSLIB system Flash region definition constants *************/
#define RSSLIB_SYS_FLASH_PFUNC_START   (0x1FF1FD4CUL)
#define RSSLIB_SYS_FLASH_PFUNC_END     (0x1FF1FD78UL)

/************ RSSLIB function return constants ********************************/
#define RSSLIB_ERROR   (0xF5F5F5F5UL)
#define RSSLIB_SUCCESS (0xEAEAEAEAUL)

/*!< RSSLIB  pointer function structure address definition */
#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL)
#define RSSLIB_PFUNC      ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)

/**
  * @brief  Prototype of RSSLIB Jump to HDP level2 Function
  * @detail This function increments HDP level up to HDP level 2
  *         Then it enables the MPU region corresponding the MPU index
  *         provided as input parameter. The Vector Table shall be located
  *         within this MPU region.
  *         Then it jumps to the reset handler present within the
  *         Vector table. The function does not return on successful execution.
  * @param  pointer on the vector table containing the reset handler the function
  *         jumps to.
  * @param  MPU region index containing the vector table
  *         jumps to.
  * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
  */
typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);

/**
  * @brief  Prototype of RSSLIB Jump to HDP level3 Function
  * @detail This function increments HDP level up to HDP level 3
  *         Then it enables the MPU region corresponding the MPU index
  *         provided as input parameter. The Vector Table shall be located
  *         within this MPU region.
  *         Then it jumps to the reset handler present within the
  *         Vector table. The function does not return on successful execution.
  * @param  pointer on the vector table containing the reset handler the function
  *         jumps to.
  * @param  MPU region index containing the vector table
  *         jumps to.
  * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
  */
typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);

/**
  * @brief Input parameter definition of RSSLIB_DataProvisioning
  */
typedef struct
{
  uint32_t *pSource;        /*!< Address of the Data to be provisioned, shall be in SRAM3 */
  uint32_t Destination;     /*!< OBKeys destination information where to provision Data */
  uint32_t Size;            /*!< Size in bytes of the Data to be provisioned*/
  uint32_t DoEncryption;    /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/
  uint32_t Crc;             /*!< CRC over full Data buffer and previous field in the structure*/
} RSSLIB_DataProvisioningConf_t;

/**
  * @brief  Prototype of RSSLIB Data Provisioning Function
  * @detail This function write Data within OBKeys sections.
  * @param  pointer on the structure defining Data to be provisioned and where to
  * provision them within OBKeys sections.
  * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
  */
typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig);

/**
  * @brief  Prototype of RSSLIB Set Secure OB Function
  * @detail This function configure a secure OB.
  * @param  OB address among following values:
  * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP)
  * @param  OB mask (example 0x000000FF for updating WRP OB).
  * @param  OB value
  * @param  OB Pos: bit position of OB value.
  * 			ObValue << ObPos must be aligned on ObMask.
  * @retval RSSLIB_RSS_ERROR on error, otherwise does not return.
  */
typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos);

/**
  * @brief  Prototype of RSSLIB Get RSS Status Function
  * @detail This function return RSS Status.
  * Calling GetRssStatus is only relevant after calling
  * SetSecOB or DataProvisioning.
  * @param  none.
  * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx.
  */
typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void);

/**
  * @brief  Prototype of RSSLIB Set Product State Function
  * @detail This function change Product State.
  * @param  Requested Product State among following values:
  * 0x17 : Provisioning
  * 0x72 : Closed
  * 0x5C : Locked
  * @retval RSSLIB_RSS_ERROR on error, otherwise does not return.
  */
typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState);

/**
  * @brief  Prototype of RSSLIB Get Product State Function
  * @detail This function return current Product State.
  * @param  none.
  * @retval RSSLIB_RSS_ERROR on error,
  * otherwise return product state among following values:
  * 0x39 : Open
  * 0x17 : Provisioning
  * 0x72 : Closed
  * 0x5C : Locked
  */
typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void);


/**
  * @brief RSSLib callable function pointer structure
  */
typedef struct
{
  __IM RSSLIB_SetSecOB_TypeDef SetSecOB;
  uint32_t RESERVED1[4];
  __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus;
  __IM RSSLIB_SetProductState_TypeDef SetProductState;
  __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning;
  __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2;
  __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3;
  __IM RSSLIB_GetProductState_TypeDef GetProductState;
} RSSLIB_pFunc_TypeDef;


/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup STM32H7RSxx_Peripheral_declaration
  * @{
  */

#define ADC1                   ((ADC_TypeDef *) ADC1_BASE)
#define ADC2                   ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON           ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADF1                   ((MDF_TypeDef *) ADF1_BASE)
#define ADF1_Filter0           ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE)
#define AXIM_AMIB_1            ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE )
#define AXIM_AMIB_2            ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE )
#define AXIM_AMIB_3            ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE )
#define AXIM_AMIB_4            ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE )
#define AXIM_AMIB_5            ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE )
#define AXIM_AMIB_6            ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE )
#define AXIM_AMIB_7            ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE )
#define AXIM_AMIB_8            ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE )
#define AXIM_AMIB_9            ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE )
#define AXIM_AMIB_10           ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE)
#define AXIM_ASIB_1            ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE )
#define AXIM_ASIB_2            ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE )
#define AXIM_ASIB_3            ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE )
#define AXIM_ASIB_4            ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE )
#define AXIM_ASIB_5            ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE )
#define AXIM_ASIB_6            ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE )
#define AXIM_ASIB_7            ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE )
#define AXIM_ASIB_8            ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE )
#define AXIM_ASIB_9            ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE )
#define AXIM_ASIB_10           ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE)
#define AXIM_ASIB_11           ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE)
#define CEC                    ((CEC_TypeDef *) CEC_BASE)
#define CORDIC                 ((CORDIC_TypeDef *) CORDIC_BASE)
#define CRC                    ((CRC_TypeDef *) CRC_BASE)
#define CRS                    ((CRS_TypeDef *) CRS_BASE)
#define CRYP                   ((CRYP_TypeDef *) CRYP_BASE)
#define DBGMCU                 ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define DCMIPP                 ((DCMIPP_TypeDef *) DCMIPP_BASE)
#define DLYB_SDMMC1            ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
#define DLYB_SDMMC2            ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
#define DMA2D                  ((DMA2D_TypeDef *) DMA2D_BASE)
#define DTS                    ((DTS_TypeDef *) DTS_BASE)
#define ETH                    ((ETH_TypeDef *)ETH_BASE)
#define EXTI                   ((EXTI_TypeDef *) EXTI_BASE)
#define FDCAN1                 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN2                 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define FDCAN_CONFIG           ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define FLASH                  ((FLASH_TypeDef *) FLASH_R_BASE)
#define FMC_Bank1_R            ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E_R           ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3_R            ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define FMC_Bank5_6_R          ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
#define GFXTIM                 ((GFXTIM_TypeDef *) GFXTIM_BASE)
#define GFXMMU                 ((GFXMMU_TypeDef *) GFXMMU_BASE)
#define GPDMA1                 ((DMA_TypeDef *) GPDMA1_BASE)
#define GPDMA1_Channel0        ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE)
#define GPDMA1_Channel1        ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE)
#define GPDMA1_Channel2        ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE)
#define GPDMA1_Channel3        ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE)
#define GPDMA1_Channel4        ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE)
#define GPDMA1_Channel5        ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE)
#define GPDMA1_Channel6        ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE)
#define GPDMA1_Channel7        ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE)
#define GPDMA1_Channel8        ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE)
#define GPDMA1_Channel9        ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE)
#define GPDMA1_Channel10       ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE)
#define GPDMA1_Channel11       ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE)
#define GPDMA1_Channel12       ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE)
#define GPDMA1_Channel13       ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE)
#define GPDMA1_Channel14       ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE)
#define GPDMA1_Channel15       ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE)
#define GPIOA                  ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB                  ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC                  ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD                  ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE                  ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF                  ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG                  ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH                  ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOM                  ((GPIO_TypeDef *) GPIOM_BASE)
#define GPION                  ((GPIO_TypeDef *) GPION_BASE)
#define GPIOO                  ((GPIO_TypeDef *) GPIOO_BASE)
#define GPIOP                  ((GPIO_TypeDef *) GPIOP_BASE)
#define HASH                   ((HASH_TypeDef *) HASH_BASE)
#define HASH_DIGEST            ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
#define HPDMA1                 ((DMA_TypeDef *) HPDMA1_BASE)
#define HPDMA1_Channel0        ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE)
#define HPDMA1_Channel1        ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE)
#define HPDMA1_Channel2        ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE)
#define HPDMA1_Channel3        ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE)
#define HPDMA1_Channel4        ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE)
#define HPDMA1_Channel5        ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE)
#define HPDMA1_Channel6        ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE)
#define HPDMA1_Channel7        ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE)
#define HPDMA1_Channel8        ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE)
#define HPDMA1_Channel9        ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE)
#define HPDMA1_Channel10       ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE)
#define HPDMA1_Channel11       ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE)
#define HPDMA1_Channel12       ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE)
#define HPDMA1_Channel13       ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE)
#define HPDMA1_Channel14       ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE)
#define HPDMA1_Channel15       ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE)
#define JPEG                   ((JPEG_TypeDef *) JPEG_BASE)
#define I2C1                   ((I2C_TypeDef *) I2C1_BASE)
#define I2C2                   ((I2C_TypeDef *) I2C2_BASE)
#define I2C3                   ((I2C_TypeDef *) I2C3_BASE)
#define I3C1                   ((I3C_TypeDef *) I3C1_BASE)
#define IWDG                   ((IWDG_TypeDef *) IWDG_BASE)
#define LPTIM1                 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPTIM2                 ((LPTIM_TypeDef *) LPTIM2_BASE)
#define LPTIM3                 ((LPTIM_TypeDef *) LPTIM3_BASE)
#define LPTIM4                 ((LPTIM_TypeDef *) LPTIM4_BASE)
#define LPTIM5                 ((LPTIM_TypeDef *) LPTIM5_BASE)
#define LPUART1                ((USART_TypeDef *) LPUART1_BASE)
#define MCE1                   ((MCE_TypeDef *) MCE1_BASE)
#define MCE1_REGION1           ((MCE_Region_TypeDef *) MCE1_REGION1_BASE)
#define MCE1_REGION2           ((MCE_Region_TypeDef *) MCE1_REGION2_BASE)
#define MCE1_REGION3           ((MCE_Region_TypeDef *) MCE1_REGION3_BASE)
#define MCE1_REGION4           ((MCE_Region_TypeDef *) MCE1_REGION4_BASE)
#define MCE1_CONTEXT1          ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE)
#define MCE1_CONTEXT2          ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE)
#define MCE2                   ((MCE_TypeDef *) MCE2_BASE)
#define MCE2_REGION1           ((MCE_Region_TypeDef *) MCE2_REGION1_BASE)
#define MCE2_REGION2           ((MCE_Region_TypeDef *) MCE2_REGION2_BASE)
#define MCE2_REGION3           ((MCE_Region_TypeDef *) MCE2_REGION3_BASE)
#define MCE2_REGION4           ((MCE_Region_TypeDef *) MCE2_REGION4_BASE)
#define MCE3                   ((MCE_TypeDef *) MCE3_BASE)
#define MCE3_REGION1           ((MCE_Region_TypeDef *) MCE3_REGION1_BASE)
#define MCE3_REGION2           ((MCE_Region_TypeDef *) MCE3_REGION2_BASE)
#define MCE3_REGION3           ((MCE_Region_TypeDef *) MCE3_REGION3_BASE)
#define MCE3_REGION4           ((MCE_Region_TypeDef *) MCE3_REGION4_BASE)
#define MDIOS                  ((MDIOS_TypeDef *) MDIOS_BASE)
#define PKA                    ((PKA_TypeDef *) PKA_BASE)
#define PSSI                   ((PSSI_TypeDef *) PSSI_BASE)
#define PWR                    ((PWR_TypeDef *) PWR_BASE)
#define RAMECC1                ((RAMECC_TypeDef *)RAMECC1_BASE)
#define RAMECC2                ((RAMECC_TypeDef *)RAMECC2_BASE)
#define RAMECC1_Monitor0       ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE)
#define RAMECC1_Monitor1       ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
#define RAMECC1_Monitor2       ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
#define RAMECC1_Monitor3       ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
#define RAMECC1_Monitor4       ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
#define RAMECC2_Monitor1       ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
#define RCC                    ((RCC_TypeDef *) RCC_BASE)
#define RNG                    ((RNG_TypeDef *) RNG_BASE)
#define RTC                    ((RTC_TypeDef *) RTC_BASE)
#define SAES                   ((SAES_TypeDef *) SAES_BASE)
#define SAI1                   ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A           ((SAI_Block_TypeDef *) SAI1_Block_A_BASE)
#define SAI1_Block_B           ((SAI_Block_TypeDef *) SAI1_Block_B_BASE)
#define SAI2                   ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A           ((SAI_Block_TypeDef *) SAI2_Block_A_BASE)
#define SAI2_Block_B           ((SAI_Block_TypeDef *) SAI2_Block_B_BASE)
#define SBS                    ((SBS_TypeDef *) SBS_BASE)
#define SDMMC1                 ((SDMMC_TypeDef *) SDMMC1_BASE)
#define SDMMC2                 ((SDMMC_TypeDef *) SDMMC2_BASE)
#define SPI1                   ((SPI_TypeDef *) SPI1_BASE)
#define SPI2                   ((SPI_TypeDef *) SPI2_BASE)
#define SPI3                   ((SPI_TypeDef *) SPI3_BASE)
#define SPI4                   ((SPI_TypeDef *) SPI4_BASE)
#define SPI5                   ((SPI_TypeDef *) SPI5_BASE)
#define SPI6                   ((SPI_TypeDef *) SPI6_BASE)
#define SPDIFRX                ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define TAMP                   ((TAMP_TypeDef *) TAMP_BASE)
#define TIM1                   ((TIM_TypeDef *) TIM1_BASE)
#define TIM2                   ((TIM_TypeDef *) TIM2_BASE)
#define TIM3                   ((TIM_TypeDef *) TIM3_BASE)
#define TIM4                   ((TIM_TypeDef *) TIM4_BASE)
#define TIM5                   ((TIM_TypeDef *) TIM5_BASE)
#define TIM6                   ((TIM_TypeDef *) TIM6_BASE)
#define TIM7                   ((TIM_TypeDef *) TIM7_BASE)
#define TIM9                   ((TIM_TypeDef *) TIM9_BASE)
#define TIM12                  ((TIM_TypeDef *) TIM12_BASE)
#define TIM13                  ((TIM_TypeDef *) TIM13_BASE)
#define TIM14                  ((TIM_TypeDef *) TIM14_BASE)
#define TIM15                  ((TIM_TypeDef *) TIM15_BASE)
#define TIM16                  ((TIM_TypeDef *) TIM16_BASE)
#define TIM17                  ((TIM_TypeDef *) TIM17_BASE)
#define USART1                 ((USART_TypeDef *) USART1_BASE)
#define USART2                 ((USART_TypeDef *) USART2_BASE)
#define USART3                 ((USART_TypeDef *) USART3_BASE)
#define UART4                  ((USART_TypeDef *) UART4_BASE)
#define UART5                  ((USART_TypeDef *) UART5_BASE)
#define UART7                  ((USART_TypeDef *) UART7_BASE)
#define UART8                  ((USART_TypeDef *) UART8_BASE)
#define UCPD1                  ((UCPD_TypeDef *) UCPD1_BASE)
#define USB_OTG_HS             ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
#define USB_OTG_FS             ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
#define WWDG                   ((WWDG_TypeDef *) WWDG_BASE)
#define XSPI1                  ((XSPI_TypeDef *) XSPI1_R_BASE)
#define XSPI2                  ((XSPI_TypeDef *) XSPI2_R_BASE)
#define XSPIM                  ((XSPIM_TypeDef *) XSPIM_BASE)
#define VREFBUF                ((VREFBUF_TypeDef *) VREFBUF_BASE)

/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */

/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants
  * @{
  */

/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition
  * @{
  */
#define LSI_STARTUP_TIME       130U /*!< LSI Maximum startup time in us */
/**
  * @}
  */

/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition
  * @{
  */
/******************************************************************************/
/*                         Peripheral Registers Bits Definition               */
/******************************************************************************/

/******************************************************************************/
/*                                                                            */
/*                        Analog to Digital Converter                         */
/*                                                                            */
/******************************************************************************/

/*
 * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
 */
#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */

/********************  Bit definition for ADC_ISR register  *******************/
#define ADC_ISR_ADRDY_Pos              (0U)
#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos              (1U)
#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos                (2U)
#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos                (3U)
#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos                (4U)
#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos               (5U)
#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos               (6U)
#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos               (7U)
#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos               (8U)
#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos               (9U)
#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos              (10U)
#define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */

/********************  Bit definition for ADC_IER register  *******************/
#define ADC_IER_ADRDYIE_Pos            (0U)
#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos            (1U)
#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos              (2U)
#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos              (3U)
#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos              (4U)
#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos             (5U)
#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos             (6U)
#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos             (7U)
#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos             (8U)
#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos             (9U)
#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos            (10U)
#define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */

/********************  Bit definition for ADC_CR register  ********************/
#define ADC_CR_ADEN_Pos                (0U)
#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
#define ADC_CR_ADDIS_Pos               (1U)
#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
#define ADC_CR_ADSTART_Pos             (2U)
#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos            (3U)
#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos               (4U)
#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos              (5U)
#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos            (28U)
#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos             (29U)
#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos            (30U)
#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos               (31U)
#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */

/********************  Bit definition for ADC_CFGR register  ******************/
#define ADC_CFGR_DMAEN_Pos             (0U)
#define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos            (1U)
#define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */

#define ADC_CFGR_ADFCFG_Pos            (2U)
#define ADC_CFGR_ADFCFG_Msk            (0x1UL << ADC_CFGR_ADFCFG_Pos)          /*!< 0x00000004 */
#define ADC_CFGR_ADFCFG                ADC_CFGR_ADFCFG_Msk                     /*!< ADC ADF transfer configuration */

#define ADC_CFGR_RES_Pos               (3U)
#define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
#define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
#define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */

#define ADC_CFGR_EXTSEL_Pos            (5U)
#define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */

#define ADC_CFGR_EXTEN_Pos             (10U)
#define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */

#define ADC_CFGR_OVRMOD_Pos            (12U)
#define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos              (13U)
#define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos            (14U)
#define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos             (15U)
#define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
#define ADC_CFGR_DISCEN_Pos            (16U)
#define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */

#define ADC_CFGR_DISCNUM_Pos           (17U)
#define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */

#define ADC_CFGR_JDISCEN_Pos           (20U)
#define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos               (21U)
#define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos           (22U)
#define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos            (23U)
#define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos           (24U)
#define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos             (25U)
#define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */

#define ADC_CFGR_AWD1CH_Pos            (26U)
#define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */

#define ADC_CFGR_JQDIS_Pos             (31U)
#define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */

/********************  Bit definition for ADC_CFGR2 register  *****************/
#define ADC_CFGR2_ROVSE_Pos            (0U)
#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos            (1U)
#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */

#define ADC_CFGR2_OVSR_Pos             (2U)
#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */

#define ADC_CFGR2_OVSS_Pos             (5U)
#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */

#define ADC_CFGR2_TROVS_Pos            (9U)
#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos            (10U)
#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */

#define ADC_CFGR2_SWTRIG_Pos           (25U)
#define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos             (26U)
#define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
#define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos          (27U)
#define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */

/********************  Bit definition for ADC_SMPR1 register  *****************/
#define ADC_SMPR1_SMP0_Pos             (0U)
#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */

#define ADC_SMPR1_SMP1_Pos             (3U)
#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */

#define ADC_SMPR1_SMP2_Pos             (6U)
#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */

#define ADC_SMPR1_SMP3_Pos             (9U)
#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */

#define ADC_SMPR1_SMP4_Pos             (12U)
#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */

#define ADC_SMPR1_SMP5_Pos             (15U)
#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */

#define ADC_SMPR1_SMP6_Pos             (18U)
#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */

#define ADC_SMPR1_SMP7_Pos             (21U)
#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */

#define ADC_SMPR1_SMP8_Pos             (24U)
#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */

#define ADC_SMPR1_SMP9_Pos             (27U)
#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */

#define ADC_SMPR1_SMPPLUS_Pos          (31U)
#define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */

/********************  Bit definition for ADC_SMPR2 register  *****************/
#define ADC_SMPR2_SMP10_Pos            (0U)
#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */

#define ADC_SMPR2_SMP11_Pos            (3U)
#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */

#define ADC_SMPR2_SMP12_Pos            (6U)
#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */

#define ADC_SMPR2_SMP13_Pos            (9U)
#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */

#define ADC_SMPR2_SMP14_Pos            (12U)
#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */

#define ADC_SMPR2_SMP15_Pos            (15U)
#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */

#define ADC_SMPR2_SMP16_Pos            (18U)
#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */

#define ADC_SMPR2_SMP17_Pos            (21U)
#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */

#define ADC_SMPR2_SMP18_Pos            (24U)
#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */

/********************  Bit definition for ADC_TR1 register  *******************/
#define ADC_TR1_LT1_Pos                (0U)
#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */

#define ADC_TR1_AWDFILT_Pos            (12U)
#define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
#define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
#define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */

#define ADC_TR1_HT1_Pos                (16U)
#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */

/********************  Bit definition for ADC_TR2 register  *******************/
#define ADC_TR2_LT2_Pos                (0U)
#define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */

#define ADC_TR2_HT2_Pos                (16U)
#define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */

/********************  Bit definition for ADC_TR3 register  *******************/
#define ADC_TR3_LT3_Pos                (0U)
#define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */

#define ADC_TR3_HT3_Pos                (16U)
#define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */

/********************  Bit definition for ADC_SQR1 register  ******************/
#define ADC_SQR1_L_Pos                 (0U)
#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */

#define ADC_SQR1_SQ1_Pos               (6U)
#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */

#define ADC_SQR1_SQ2_Pos               (12U)
#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */

#define ADC_SQR1_SQ3_Pos               (18U)
#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */

#define ADC_SQR1_SQ4_Pos               (24U)
#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */

/********************  Bit definition for ADC_SQR2 register  ******************/
#define ADC_SQR2_SQ5_Pos               (0U)
#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */

#define ADC_SQR2_SQ6_Pos               (6U)
#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */

#define ADC_SQR2_SQ7_Pos               (12U)
#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */

#define ADC_SQR2_SQ8_Pos               (18U)
#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */

#define ADC_SQR2_SQ9_Pos               (24U)
#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */

/********************  Bit definition for ADC_SQR3 register  ******************/
#define ADC_SQR3_SQ10_Pos              (0U)
#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */

#define ADC_SQR3_SQ11_Pos              (6U)
#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */

#define ADC_SQR3_SQ12_Pos              (12U)
#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */

#define ADC_SQR3_SQ13_Pos              (18U)
#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */

#define ADC_SQR3_SQ14_Pos              (24U)
#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */

/********************  Bit definition for ADC_SQR4 register  ******************/
#define ADC_SQR4_SQ15_Pos              (0U)
#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */

#define ADC_SQR4_SQ16_Pos              (6U)
#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */

/********************  Bit definition for ADC_DR register  ********************/
#define ADC_DR_RDATA_Pos               (0U)
#define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */

/********************  Bit definition for ADC_JSQR register  ******************/
#define ADC_JSQR_JL_Pos                (0U)
#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */

#define ADC_JSQR_JEXTSEL_Pos           (2U)
#define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */

#define ADC_JSQR_JEXTEN_Pos            (7U)
#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */

#define ADC_JSQR_JSQ1_Pos              (9U)
#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */

#define ADC_JSQR_JSQ2_Pos              (15U)
#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */

#define ADC_JSQR_JSQ3_Pos              (21U)
#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */

#define ADC_JSQR_JSQ4_Pos              (27U)
#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */

/********************  Bit definition for ADC_OFR1 register  ******************/
#define ADC_OFR1_OFFSET1_Pos           (0U)
#define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */

#define ADC_OFR1_OFFSETPOS_Pos         (24U)
#define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos             (25U)
#define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
#define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */

#define ADC_OFR1_OFFSET1_CH_Pos        (26U)
#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */

#define ADC_OFR1_OFFSET1_EN_Pos        (31U)
#define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */

/********************  Bit definition for ADC_OFR2 register  ******************/
#define ADC_OFR2_OFFSET2_Pos           (0U)
#define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */

#define ADC_OFR2_OFFSETPOS_Pos         (24U)
#define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos             (25U)
#define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
#define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */

#define ADC_OFR2_OFFSET2_CH_Pos        (26U)
#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */

#define ADC_OFR2_OFFSET2_EN_Pos        (31U)
#define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */

/********************  Bit definition for ADC_OFR3 register  ******************/
#define ADC_OFR3_OFFSET3_Pos           (0U)
#define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */

#define ADC_OFR3_OFFSETPOS_Pos         (24U)
#define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos             (25U)
#define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
#define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */

#define ADC_OFR3_OFFSET3_CH_Pos        (26U)
#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */

#define ADC_OFR3_OFFSET3_EN_Pos        (31U)
#define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */

/********************  Bit definition for ADC_OFR4 register  ******************/
#define ADC_OFR4_OFFSET4_Pos           (0U)
#define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */

#define ADC_OFR4_OFFSETPOS_Pos         (24U)
#define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos             (25U)
#define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
#define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */

#define ADC_OFR4_OFFSET4_CH_Pos        (26U)
#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */

#define ADC_OFR4_OFFSET4_EN_Pos        (31U)
#define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */

/********************  Bit definition for ADC_JDR1 register  ******************/
#define ADC_JDR1_JDATA_Pos             (0U)
#define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */

/********************  Bit definition for ADC_JDR2 register  ******************/
#define ADC_JDR2_JDATA_Pos             (0U)
#define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */

/********************  Bit definition for ADC_JDR3 register  ******************/
#define ADC_JDR3_JDATA_Pos             (0U)
#define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */

/********************  Bit definition for ADC_JDR4 register  ******************/
#define ADC_JDR4_JDATA_Pos             (0U)
#define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */

/********************  Bit definition for ADC_AWD2CR register  ****************/
#define ADC_AWD2CR_AWD2CH_Pos          (0U)
#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */

/********************  Bit definition for ADC_AWD3CR register  ****************/
#define ADC_AWD3CR_AWD3CH_Pos          (0U)
#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */

/********************  Bit definition for ADC_DIFSEL register  ****************/
#define ADC_DIFSEL_DIFSEL_Pos          (0U)
#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */

/********************  Bit definition for ADC_CALFACT register  ***************/
#define ADC_CALFACT_CALFACT_S_Pos      (0U)
#define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */

#define ADC_CALFACT_CALFACT_D_Pos      (16U)
#define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */

/********************  Bit definition for ADC_OR register  ***************/
#define ADC_OR_OP0_Pos                 (0U)
#define ADC_OR_OP0_Msk                 (0x1UL << ADC_OR_OP0_Pos)               /*!< 0x00000001 */
#define ADC_OR_OP0                     ADC_OR_OP0_Msk                          /*!< ADC internal path to VDDCORE */

/*************************  ADC Common registers  *****************************/
/********************  Bit definition for ADC_CSR register  *******************/
#define ADC_CSR_ADRDY_MST_Pos          (0U)
#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos          (1U)
#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos            (2U)
#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos            (3U)
#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos            (4U)
#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos           (5U)
#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos           (6U)
#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos           (7U)
#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos           (8U)
#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos           (9U)
#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos          (10U)
#define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */

#define ADC_CSR_ADRDY_SLV_Pos          (16U)
#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos          (17U)
#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos            (18U)
#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos            (19U)
#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos            (20U)
#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos           (21U)
#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos           (22U)
#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos           (23U)
#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos           (24U)
#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos           (25U)
#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos          (26U)
#define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */

/********************  Bit definition for ADC_CCR register  *******************/
#define ADC_CCR_DUAL_Pos               (0U)
#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */

#define ADC_CCR_DELAY_Pos              (8U)
#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */

#define ADC_CCR_DMACFG_Pos             (13U)
#define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */

#define ADC_CCR_MDMA_Pos               (14U)
#define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
#define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */

#define ADC_CCR_CKMODE_Pos             (16U)
#define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */

#define ADC_CCR_PRESC_Pos              (18U)
#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */

#define ADC_CCR_VREFEN_Pos             (22U)
#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */

#define ADC_CCR_TSEN_Pos               (23U)
#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */

#define ADC_CCR_VBATEN_Pos             (24U)
#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */

/********************  Bit definition for ADC_CDR register  *******************/
#define ADC_CDR_RDATA_MST_Pos          (0U)
#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */

#define ADC_CDR_RDATA_SLV_Pos          (16U)
#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */

/******************************************************************************/
/*                                                                            */
/*                                   AXIM                                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for AXIM_ASIB_FNMOD2 register  **********/
#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos   (0U)
#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk   (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos)    /*!< 0x00000001 */
#define AXIM_ASIB_FNMOD2_BYPASS_MERGE       AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk               /*!< Bypass Merge enable */

/*******************  Bit definition for AXIM_ASIB_READQOS register  ********/
#define AXIM_ASIB_READQOS_AR_QOS_Pos       (0U)
#define AXIM_ASIB_READQOS_AR_QOS_Msk       (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos)          /*!< 0x0000000F */
#define AXIM_ASIB_READQOS_AR_QOS           AXIM_ASIB_READQOS_AR_QOS_Msk                     /*!< Read channel QoS setting */

/*******************  Bit definition for AXIM_ASIB_WRITEQOS register  *******/
#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos       (0U)
#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk       (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos)        /*!< 0x0000000F */
#define AXIM_ASIB_WRITEQOS_AW_QOS           AXIM_ASIB_WRITEQOS_AW_QOS_Msk                   /*!< Write channel QoS setting */

/*******************  Bit definition for AXIM_ASIB_FNMOD register  **********/
#define AXIM_ASIB_FNMOD_READ_ISS_Pos        (0U)
#define AXIM_ASIB_FNMOD_READ_ISS_Msk        (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos)         /*!< 0x00000001 */
#define AXIM_ASIB_FNMOD_READ_ISS            AXIM_ASIB_FNMOD_READ_ISS_Msk                    /*!< Force read issuing capability to 1 */
#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos       (1U)
#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk       (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos)        /*!< 0x00000002 */
#define AXIM_ASIB_FNMOD_WRITE_ISS           AXIM_ASIB_FNMOD_WRITE_ISS_Msk                   /*!< Force write issuing capability to 1 */

/*******************  Bit definition for AXIM_AMIB_FNMODBMISS register  **********/
#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos   (0U)
#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk   (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos)     /*!< 0x00000001 */
#define AXIM_AMIB_FNMODBMISS_READ_ISS       AXIM_AMIB_FNMODBMISS_READ_ISS_Msk                /*!< Force read issuing capability to 1 */
#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos  (1U)
#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk  (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos)    /*!< 0x00000002 */
#define AXIM_AMIB_FNMODBMISS_WRITE_ISS      AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk               /*!< Force write issuing capability to 1 */

/*******************  Bit definition for AXIM_AMIB_FNMOD2 register  **********/
#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos   (0U)
#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk   (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos)    /*!< 0x00000001 */
#define AXIM_AMIB_FNMOD2_BYPASS_MERGE       AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk               /*!< Bypass Merge enable */

/*******************  Bit definition for AXIM_AMIB_FNMODLB register  **********/
#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos    (0U)
#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk    (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos)     /*!< 0x00000001 */
#define AXIM_AMIB_FNMODLB_LONG_BURST        AXIM_AMIB_FNMODLB_LONG_BURST_Msk                /*!< Long bursts can be generated */

/*******************  Bit definition for AXIM_AMIB_FNMOD register  **********/
#define AXIM_AMIB_FNMOD_READ_ISS_Pos        (0U)
#define AXIM_AMIB_FNMOD_READ_ISS_Msk        (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos)         /*!< 0x00000001 */
#define AXIM_AMIB_FNMOD_READ_ISS            AXIM_AMIB_FNMOD_READ_ISS_Msk                    /*!< Force read issuing capability to 1 */
#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos       (1U)
#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk       (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos)        /*!< 0x00000002 */
#define AXIM_AMIB_FNMOD_WRITE_ISS           AXIM_AMIB_FNMOD_WRITE_ISS_Msk                   /*!< Force write issuing capability to 1 */

/******************************************************************************/
/*                                                                            */
/*                                   VREFBUF                                  */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for VREFBUF_CSR register  ****************/
#define VREFBUF_CSR_ENVR_Pos        (0U)
#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos         (1U)
#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
#define VREFBUF_CSR_VRR_Pos         (3U)
#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
#define VREFBUF_CSR_VRS_Pos         (4U)
#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

/*******************  Bit definition for VREFBUF_CCR register  ****************/
#define VREFBUF_CCR_TRIM_Pos        (0U)
#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

/******************************************************************************/
/*                                                                            */
/*                          HDMI-CEC (CEC)                                    */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for CEC_CR register  *********************/
#define CEC_CR_CECEN_Pos         (0U)
#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
#define CEC_CR_TXSOM_Pos         (1U)
#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
#define CEC_CR_TXEOM_Pos         (2U)
#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

/*******************  Bit definition for CEC_CFGR register  *******************/
#define CEC_CFGR_SFT_Pos         (0U)
#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
#define CEC_CFGR_RXTOL_Pos       (3U)
#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
#define CEC_CFGR_BRESTP_Pos      (4U)
#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
#define CEC_CFGR_BREGEN_Pos      (5U)
#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
#define CEC_CFGR_LBPEGEN_Pos     (6U)
#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
#define CEC_CFGR_SFTOPT_Pos      (8U)
#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
#define CEC_CFGR_BRDNOGEN_Pos    (7U)
#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
#define CEC_CFGR_OAR_Pos         (16U)
#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
#define CEC_CFGR_LSTN_Pos        (31U)
#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

/*******************  Bit definition for CEC_TXDR register  *******************/
#define CEC_TXDR_TXD_Pos         (0U)
#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

/*******************  Bit definition for CEC_RXDR register  *******************/
#define CEC_RXDR_RXD_Pos         (0U)
#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

/*******************  Bit definition for CEC_ISR register  ********************/
#define CEC_ISR_RXBR_Pos         (0U)
#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
#define CEC_ISR_RXEND_Pos        (1U)
#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
#define CEC_ISR_RXOVR_Pos        (2U)
#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
#define CEC_ISR_BRE_Pos          (3U)
#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
#define CEC_ISR_SBPE_Pos         (4U)
#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
#define CEC_ISR_LBPE_Pos         (5U)
#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
#define CEC_ISR_RXACKE_Pos       (6U)
#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
#define CEC_ISR_ARBLST_Pos       (7U)
#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
#define CEC_ISR_TXBR_Pos         (8U)
#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
#define CEC_ISR_TXEND_Pos        (9U)
#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
#define CEC_ISR_TXUDR_Pos        (10U)
#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
#define CEC_ISR_TXERR_Pos        (11U)
#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
#define CEC_ISR_TXACKE_Pos       (12U)
#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

/*******************  Bit definition for CEC_IER register  ********************/
#define CEC_IER_RXBRIE_Pos       (0U)
#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
#define CEC_IER_RXENDIE_Pos      (1U)
#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
#define CEC_IER_RXOVRIE_Pos      (2U)
#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
#define CEC_IER_BREIE_Pos        (3U)
#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
#define CEC_IER_SBPEIE_Pos       (4U)
#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
#define CEC_IER_LBPEIE_Pos       (5U)
#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
#define CEC_IER_RXACKEIE_Pos     (6U)
#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
#define CEC_IER_ARBLSTIE_Pos     (7U)
#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
#define CEC_IER_TXBRIE_Pos       (8U)
#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
#define CEC_IER_TXENDIE_Pos      (9U)
#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
#define CEC_IER_TXUDRIE_Pos      (10U)
#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
#define CEC_IER_TXERRIE_Pos      (11U)
#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
#define CEC_IER_TXACKEIE_Pos     (12U)
#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */


/******************************************************************************/
/*                                                                            */
/*                          CORDIC calculation unit                           */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CORDIC_CSR register  *****************/
#define CORDIC_CSR_FUNC_Pos                 (0U)
#define CORDIC_CSR_FUNC_Msk                 (0xFUL << CORDIC_CSR_FUNC_Pos)          /*!< 0x0000000F */
#define CORDIC_CSR_FUNC                     CORDIC_CSR_FUNC_Msk                     /*!< Function */
#define CORDIC_CSR_FUNC_0                   (0x1UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1                   (0x2UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2                   (0x4UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3                   (0x8UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos            (4U)
#define CORDIC_CSR_PRECISION_Msk            (0xFUL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION                CORDIC_CSR_PRECISION_Msk                /*!< Precision */
#define CORDIC_CSR_PRECISION_0              (0x1UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1              (0x2UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2              (0x4UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3              (0x8UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos                (8U)
#define CORDIC_CSR_SCALE_Msk                (0x7UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000700 */
#define CORDIC_CSR_SCALE                    CORDIC_CSR_SCALE_Msk                    /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0                  (0x1UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1                  (0x2UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2                  (0x4UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos                  (16U)
#define CORDIC_CSR_IEN_Msk                  (0x1UL << CORDIC_CSR_IEN_Pos)           /*!< 0x00010000 */
#define CORDIC_CSR_IEN                      CORDIC_CSR_IEN_Msk                      /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos               (17U)
#define CORDIC_CSR_DMAREN_Msk               (0x1UL << CORDIC_CSR_DMAREN_Pos)        /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN                   CORDIC_CSR_DMAREN_Msk                   /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos               (18U)
#define CORDIC_CSR_DMAWEN_Msk               (0x1UL << CORDIC_CSR_DMAWEN_Pos)        /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN                   CORDIC_CSR_DMAWEN_Msk                   /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos                 (19U)
#define CORDIC_CSR_NRES_Msk                 (0x1UL << CORDIC_CSR_NRES_Pos)          /*!< 0x00080000 */
#define CORDIC_CSR_NRES                     CORDIC_CSR_NRES_Msk                     /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos                (20U)
#define CORDIC_CSR_NARGS_Msk                (0x1UL << CORDIC_CSR_NARGS_Pos)         /*!< 0x00100000 */
#define CORDIC_CSR_NARGS                    CORDIC_CSR_NARGS_Msk                    /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos              (21U)
#define CORDIC_CSR_RESSIZE_Msk              (0x1UL << CORDIC_CSR_RESSIZE_Pos)       /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE                  CORDIC_CSR_RESSIZE_Msk                  /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos              (22U)
#define CORDIC_CSR_ARGSIZE_Msk              (0x1UL << CORDIC_CSR_ARGSIZE_Pos)       /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE                  CORDIC_CSR_ARGSIZE_Msk                  /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos                 (31U)
#define CORDIC_CSR_RRDY_Msk                 (0x1UL << CORDIC_CSR_RRDY_Pos)          /*!< 0x80000000 */
#define CORDIC_CSR_RRDY                     CORDIC_CSR_RRDY_Msk                     /*!< Result Ready Flag */

/*******************  Bit definition for CORDIC_WDATA register  ***************/
#define CORDIC_WDATA_ARG_Pos                (0U)
#define CORDIC_WDATA_ARG_Msk                (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)  /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG                    CORDIC_WDATA_ARG_Msk                    /*!< Input Argument */

/*******************  Bit definition for CORDIC_RDATA register  ***************/
#define CORDIC_RDATA_RES_Pos                (0U)
#define CORDIC_RDATA_RES_Msk                (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)  /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES                    CORDIC_RDATA_RES_Msk                    /*!< Output Result */


/******************************************************************************/
/*                                                                            */
/*                          CRC calculation unit                              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_DR register  *********************/
#define CRC_DR_DR_Pos              (0U)
#define CRC_DR_DR_Msk              (0xFFFFFFFFUL << CRC_DR_DR_Pos)             /*!< 0xFFFFFFFF */
#define CRC_DR_DR                  CRC_DR_DR_Msk                               /*!< Data register bits */

/*******************  Bit definition for CRC_IDR register  ********************/
#define CRC_IDR_IDR_Pos            (0U)
#define CRC_IDR_IDR_Msk            (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)           /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR                CRC_IDR_IDR_Msk                             /*!< General-purpose 32-bits data register bits */

/********************  Bit definition for CRC_CR register  ********************/
#define CRC_CR_RESET_Pos           (0U)
#define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
#define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos        (3U)
#define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
#define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos          (5U)
#define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
#define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
#define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos         (7U)
#define CRC_CR_REV_OUT_Msk         (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
#define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */

/*******************  Bit definition for CRC_INIT register  *******************/
#define CRC_INIT_INIT_Pos          (0U)
#define CRC_INIT_INIT_Msk          (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)         /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT              CRC_INIT_INIT_Msk                           /*!< Initial CRC value bits */

/*******************  Bit definition for CRC_POL register  ********************/
#define CRC_POL_POL_Pos            (0U)
#define CRC_POL_POL_Msk            (0xFFFFFFFFUL << CRC_POL_POL_Pos)           /*!< 0xFFFFFFFF */
#define CRC_POL_POL                CRC_POL_POL_Msk                             /*!< Coefficients of the polynomial */


/******************************************************************************/
/*                                                                            */
/*                          CRS Clock Recovery System                         */
/******************************************************************************/
/*******************  Bit definition for CRS_CR register  *********************/
#define CRS_CR_SYNCOKIE_Pos        (0U)
#define CRS_CR_SYNCOKIE_Msk        (0x1UL << CRS_CR_SYNCOKIE_Pos)              /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE            CRS_CR_SYNCOKIE_Msk                         /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos      (1U)
#define CRS_CR_SYNCWARNIE_Msk      (0x1UL << CRS_CR_SYNCWARNIE_Pos)            /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE          CRS_CR_SYNCWARNIE_Msk                       /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos           (2U)
#define CRS_CR_ERRIE_Msk           (0x1UL << CRS_CR_ERRIE_Pos)                 /*!< 0x00000004 */
#define CRS_CR_ERRIE               CRS_CR_ERRIE_Msk                            /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos         (3U)
#define CRS_CR_ESYNCIE_Msk         (0x1UL << CRS_CR_ESYNCIE_Pos)               /*!< 0x00000008 */
#define CRS_CR_ESYNCIE             CRS_CR_ESYNCIE_Msk                          /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos             (5U)
#define CRS_CR_CEN_Msk             (0x1UL << CRS_CR_CEN_Pos)                   /*!< 0x00000020 */
#define CRS_CR_CEN                 CRS_CR_CEN_Msk                              /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos      (6U)
#define CRS_CR_AUTOTRIMEN_Msk      (0x1UL << CRS_CR_AUTOTRIMEN_Pos)            /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN          CRS_CR_AUTOTRIMEN_Msk                       /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos          (7U)
#define CRS_CR_SWSYNC_Msk          (0x1UL << CRS_CR_SWSYNC_Pos)                /*!< 0x00000080 */
#define CRS_CR_SWSYNC              CRS_CR_SWSYNC_Msk                           /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos            (8U)
#define CRS_CR_TRIM_Msk            (0x3FUL << CRS_CR_TRIM_Pos)                 /*!< 0x00003F00 */
#define CRS_CR_TRIM                CRS_CR_TRIM_Msk                             /*!< HSI48 oscillator smooth trimming */

/*******************  Bit definition for CRS_CFGR register  *********************/
#define CRS_CFGR_RELOAD_Pos        (0U)
#define CRS_CFGR_RELOAD_Msk        (0xFFFFUL << CRS_CFGR_RELOAD_Pos)           /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD            CRS_CFGR_RELOAD_Msk                         /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos         (16U)
#define CRS_CFGR_FELIM_Msk         (0xFFUL << CRS_CFGR_FELIM_Pos)              /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM             CRS_CFGR_FELIM_Msk                          /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos       (24U)
#define CRS_CFGR_SYNCDIV_Msk       (0x7UL << CRS_CFGR_SYNCDIV_Pos)             /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV           CRS_CFGR_SYNCDIV_Msk                        /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0         (0x1UL << CRS_CFGR_SYNCDIV_Pos)             /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1         (0x2UL << CRS_CFGR_SYNCDIV_Pos)             /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2         (0x4UL << CRS_CFGR_SYNCDIV_Pos)             /*!< 0x04000000 */

#define CRS_CFGR_SYNCSRC_Pos       (28U)
#define CRS_CFGR_SYNCSRC_Msk       (0x3UL << CRS_CFGR_SYNCSRC_Pos)             /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC           CRS_CFGR_SYNCSRC_Msk                        /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0         (0x1UL << CRS_CFGR_SYNCSRC_Pos)             /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1         (0x2UL << CRS_CFGR_SYNCSRC_Pos)             /*!< 0x20000000 */

#define CRS_CFGR_SYNCPOL_Pos       (31U)
#define CRS_CFGR_SYNCPOL_Msk       (0x1UL << CRS_CFGR_SYNCPOL_Pos)             /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL           CRS_CFGR_SYNCPOL_Msk                        /*!< SYNC polarity selection */

/*******************  Bit definition for CRS_ISR register  *********************/
#define CRS_ISR_SYNCOKF_Pos        (0U)
#define CRS_ISR_SYNCOKF_Msk        (0x1UL << CRS_ISR_SYNCOKF_Pos)              /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF            CRS_ISR_SYNCOKF_Msk                         /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos      (1U)
#define CRS_ISR_SYNCWARNF_Msk      (0x1UL << CRS_ISR_SYNCWARNF_Pos)            /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF          CRS_ISR_SYNCWARNF_Msk                       /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos           (2U)
#define CRS_ISR_ERRF_Msk           (0x1UL << CRS_ISR_ERRF_Pos)                 /*!< 0x00000004 */
#define CRS_ISR_ERRF               CRS_ISR_ERRF_Msk                            /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos         (3U)
#define CRS_ISR_ESYNCF_Msk         (0x1UL << CRS_ISR_ESYNCF_Pos)               /*!< 0x00000008 */
#define CRS_ISR_ESYNCF             CRS_ISR_ESYNCF_Msk                          /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos        (8U)
#define CRS_ISR_SYNCERR_Msk        (0x1UL << CRS_ISR_SYNCERR_Pos)              /*!< 0x00000100 */
#define CRS_ISR_SYNCERR            CRS_ISR_SYNCERR_Msk                         /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos       (9U)
#define CRS_ISR_SYNCMISS_Msk       (0x1UL << CRS_ISR_SYNCMISS_Pos)             /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS           CRS_ISR_SYNCMISS_Msk                        /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos        (10U)
#define CRS_ISR_TRIMOVF_Msk        (0x1UL << CRS_ISR_TRIMOVF_Pos)              /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF            CRS_ISR_TRIMOVF_Msk                         /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos          (15U)
#define CRS_ISR_FEDIR_Msk          (0x1UL << CRS_ISR_FEDIR_Pos)                /*!< 0x00008000 */
#define CRS_ISR_FEDIR              CRS_ISR_FEDIR_Msk                           /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos          (16U)
#define CRS_ISR_FECAP_Msk          (0xFFFFUL << CRS_ISR_FECAP_Pos)             /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP              CRS_ISR_FECAP_Msk                           /*!< Frequency error capture */

/*******************  Bit definition for CRS_ICR register  *********************/
#define CRS_ICR_SYNCOKC_Pos        (0U)
#define CRS_ICR_SYNCOKC_Msk        (0x1UL << CRS_ICR_SYNCOKC_Pos)              /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC            CRS_ICR_SYNCOKC_Msk                         /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos      (1U)
#define CRS_ICR_SYNCWARNC_Msk      (0x1UL << CRS_ICR_SYNCWARNC_Pos)            /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC          CRS_ICR_SYNCWARNC_Msk                       /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos           (2U)
#define CRS_ICR_ERRC_Msk           (0x1UL << CRS_ICR_ERRC_Pos)                 /*!< 0x00000004 */
#define CRS_ICR_ERRC               CRS_ICR_ERRC_Msk                            /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos         (3U)
#define CRS_ICR_ESYNCC_Msk         (0x1UL << CRS_ICR_ESYNCC_Pos)               /*!< 0x00000008 */
#define CRS_ICR_ESYNCC             CRS_ICR_ESYNCC_Msk                          /*!< Expected SYNC clear flag */


/******************************************************************************/
/*                                                                            */
/*                             CRYP Processor                                 */
/*                                                                            */
/******************************************************************************/
/******************* Bits definition for CRYP_CR register  ********************/
#define CRYP_CR_ALGODIR_Pos              (2U)
#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)           /*!< 0x00000004 */
#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk                      /*!< Algorithm direction (Encrypt/Decrypt) */

#define CRYP_CR_ALGOMODE_Pos             (3U)
#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080038 */
#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk                     /*!< Algorithm mode */
#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000008 */
#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000010 */
#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_3               (0x10000UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080000 */
#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)  /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)  /*!< 0x00000028 */
#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)  /*!< 0x00000030 */
#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)  /*!< 0x00000038 */
#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)  /*!< 0x00080000 */
#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

#define CRYP_CR_DATATYPE_Pos             (6U)
#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x000000C0 */
#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk                     /*!< Data Type selection */
#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000040 */
#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000080 */
#define CRYP_CR_KEYSIZE_Pos              (8U)
#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000300 */
#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk                      /*!< Key Size selection */
#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000100 */
#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000200 */
#define CRYP_CR_FFLUSH_Pos               (14U)
#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)            /*!< 0x00004000 */
#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk                       /*!< CRYP FIFO Flush */
#define CRYP_CR_CRYPEN_Pos               (15U)
#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)            /*!< 0x00008000 */
#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk                       /*!< CRYP processor enable */

#define CRYP_CR_GCM_CCMPH_Pos            (16U)
#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00030000 */
#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk                    /*!< GCM or CCM Phase selection */
#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00010000 */
#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00020000 */

#define CRYP_CR_NPBLB_Pos                (20U)
#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)             /*!< 0x00F00000 */
#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk                        /*!< Number of Padding Bytes in Last Block of payload */

#define CRYP_CR_KMOD_Pos                (24U)
#define CRYP_CR_KMOD_Msk                (0x3UL << CRYP_CR_KMOD_Pos)               /*!< 0x03000000 */
#define CRYP_CR_KMOD                    CRYP_CR_KMOD_Msk                          /*!< Key mode selection */
#define CRYP_CR_KMOD_0                  (0x1UL << CRYP_CR_KMOD_Pos)               /*!< 0x01000000 */
#define CRYP_CR_KMOD_1                  (0x2UL << CRYP_CR_KMOD_Pos)               /*!< 0x02000000 */

#define CRYP_CR_IPRST_Pos               (31U)
#define CRYP_CR_IPRST_Msk               (0x1UL << CRYP_CR_IPRST_Pos)              /*!< 0x80000000 */
#define CRYP_CR_IPRST                   CRYP_CR_IPRST_Msk                         /*!< CRYP peripheral software reset */

/****************** Bits definition for CRYP_SR register  *********************/
#define CRYP_SR_IFEM_Pos                 (0U)
#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)              /*!< 0x00000001 */
#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk                         /*!< Input FIFO empty flag */
#define CRYP_SR_IFNF_Pos                 (1U)
#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)              /*!< 0x00000002 */
#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk                         /*!< Input FIFO not full flag */
#define CRYP_SR_OFNE_Pos                 (2U)
#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)              /*!< 0x00000004 */
#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk                         /*!< Output FIFO not empty flag */
#define CRYP_SR_OFFU_Pos                 (3U)
#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)              /*!< 0x00000008 */
#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk                         /*!< Output FIFO full flag */
#define CRYP_SR_BUSY_Pos                 (4U)
#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)              /*!< 0x00000010 */
#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk                         /*!< Busy bit */
#define CRYP_SR_KERF_Pos                 (6U)
#define CRYP_SR_KERF_Msk                 (0x1UL << CRYP_SR_KERF_Pos)              /*!< 0x00000040 */
#define CRYP_SR_KERF                     CRYP_SR_KERF_Msk                         /*!< Key error flag */
#define CRYP_SR_KEYVALID_Pos             (7U)
#define CRYP_SR_KEYVALID_Msk             (0x1UL << CRYP_SR_KEYVALID_Pos)          /*!< 0x00000080 */
#define CRYP_SR_KEYVALID                 CRYP_SR_KEYVALID_Msk                     /*!< Key valid flag */

/*******************  Bit definition for CRYP_DIN register  *******************/
#define CRYP_DIN_DATAIN_Pos              (0U)
#define CRYP_DIN_DATAIN_Msk              (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos)    /*!< 0xFFFFFFFF */
#define CRYP_DIN_DATAIN                  CRYP_DIN_DATAIN_Msk                      /*!< CRYP Data Input */

/*******************  Bit definition for CRYP_DIN register  *******************/
#define CRYP_DOUT_DATAOUT_Pos            (0U)
#define CRYP_DOUT_DATAOUT_Msk            (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos)  /*!< 0xFFFFFFFF */
#define CRYP_DOUT_DATAOUT                CRYP_DOUT_DATAOUT_Msk                    /*!< CRYP Data Output */

/****************** Bits definition for CRYP_DMACR register  ******************/
#define CRYP_DMACR_DIEN_Pos              (0U)
#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)           /*!< 0x00000001 */
#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk                      /*!< DMA Input Enable */
#define CRYP_DMACR_DOEN_Pos              (1U)
#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)           /*!< 0x00000002 */
#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk                      /*!< DMA Output Enable */

/*****************  Bits definition for CRYP_IMSCR register  ******************/
#define CRYP_IMSCR_INIM_Pos              (0U)
#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)           /*!< 0x00000001 */
#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk                      /*!< Input FIFO service interrupt mask */
#define CRYP_IMSCR_OUTIM_Pos             (1U)
#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)          /*!< 0x00000002 */
#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk                     /*!< Output FIFO service interrupt mask */

/****************** Bits definition for CRYP_RISR register  *******************/
#define CRYP_RISR_INRIS_Pos              (0U)
#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)           /*!< 0x00000001 */
#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk                      /*!< Input FIFO service raw interrupt status */
#define CRYP_RISR_OUTRIS_Pos             (1U)
#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)          /*!< 0x00000002 */
#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk                     /*!< Output FIFO service raw interrupt mask */

/****************** Bits definition for CRYP_MISR register  *******************/
#define CRYP_MISR_INMIS_Pos              (0U)
#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)           /*!< 0x00000001 */
#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk                      /*!< Input FIFO service masked interrupt status */
#define CRYP_MISR_OUTMIS_Pos             (1U)
#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)          /*!< 0x00000002 */
#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk                     /*!< Output FIFO service masked interrupt status */

/*******************  Bit definition for CRYP_K0LR register  ******************/
#define CRYP_K0LR_K_Pos                  (0U)
#define CRYP_K0LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0LR_K_Pos)        /*!< 0xFFFFFFFF */
#define CRYP_K0LR_K                      CRYP_K0LR_K_Msk                          /*!< AES key bit x (x= 224 to 255) */

/*******************  Bit definition for CRYP_K0RR register  ******************/
#define CRYP_K0RR_K_Pos                  (0U)
#define CRYP_K0RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0RR_K_Pos)        /*!< 0xFFFFFFFF */
#define CRYP_K0RR_K                      CRYP_K0RR_K_Msk                          /*!< AES key bit x (x= 192 to 223) */

/*******************  Bit definition for CRYP_K1LR register  ******************/
#define CRYP_K1LR_Pos                    (0U)
#define CRYP_K1LR_Msk                    (0xFFFFFFFFUL << CRYP_K1LR_Pos)          /*!< 0xFFFFFFFF */
#define CRYP_K1LR                        CRYP_K1LR_Msk                            /*!< AES key bit x (x= 160 to 291) */

/*******************  Bit definition for CRYP_IV1RR register  ******************/
#define CRYP_K1RR_Pos                    (0U)
#define CRYP_K1RR_Msk                    (0xFFFFFFFFUL << CRYP_K1RR_Pos)          /*!< 0xFFFFFFFF */
#define CRYP_K1RR                        CRYP_K1RR_Msk                            /*!< AES key bit x (x= 128 to 159) */

/*******************  Bit definition for CRYP_K2LR register  ******************/
#define CRYP_K2LR_K_Pos                  (0U)
#define CRYP_K2LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2LR_K_Pos)        /*!< 0xFFFFFFFF */
#define CRYP_K2LR_K                      CRYP_K2LR_K_Msk                          /*!< AES key bit x (x= 96 to 127) */

/*******************  Bit definition for CRYP_K2RR register  ******************/
#define CRYP_K2RR_K_Pos                  (0U)
#define CRYP_K2RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2RR_K_Pos)        /*!< 0xFFFFFFFF */
#define CRYP_K2RR_K                      CRYP_K2RR_K_Msk                          /*!< AES key bit x (x= 64 to 95) */

/*******************  Bit definition for CRYP_K3LR register  ******************/
#define CRYP_K3LR_K_Pos                  (0U)
#define CRYP_K3LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3LR_K_Pos)        /*!< 0xFFFFFFFF */
#define CRYP_K3LR_K                      CRYP_K3LR_K_Msk                          /*!< AES key bit x (x= 32 to 63) */

/*******************  Bit definition for CRYP_K3RR register  ******************/
#define CRYP_K3RR_K_Pos                  (0U)
#define CRYP_K3RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3RR_K_Pos)        /*!< 0xFFFFFFFF */
#define CRYP_K3RR_K                      CRYP_K3RR_K_Msk                          /*!< AES key bit x (x= 0 to 31) */

/*******************  Bit definition for CRYP_IV0LR register  ******************/
#define CRYP_IV0LR_IV_Pos                (0U)
#define CRYP_IV0LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos)      /*!< 0xFFFFFFFF */
#define CRYP_IV0LR_IV                    CRYP_IV0LR_IV_Msk                        /*!< Initialization vector bit x (x= 0 to 31) */

/*******************  Bit definition for CRYP_IV0RR register  ******************/
#define CRYP_IV0RR_IV_Pos                (0U)
#define CRYP_IV0RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos)      /*!< 0xFFFFFFFF */
#define CRYP_IV0RR_IV                    CRYP_IV0RR_IV_Msk                        /*!< Initialization vector bit x (x= 32 to 63) */

/*******************  Bit definition for CRYP_IV1LR register  ******************/
#define CRYP_IV1LR_IV_Pos                (0U)
#define CRYP_IV1LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos)      /*!< 0xFFFFFFFF */
#define CRYP_IV1LR_IV                    CRYP_IV1LR_IV_Msk                        /*!< Initialization vector bit x (x= 64 to 95) */

/*******************  Bit definition for CRYP_IV1RR register  ******************/
#define CRYP_IV1RR_IV_Pos                (0U)
#define CRYP_IV1RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos)      /*!< 0xFFFFFFFF */
#define CRYP_IV1RR_IV                    CRYP_IV1RR_IV_Msk                        /*!< Initialization vector bit x (x= 96 to 127) */

/*******************  Bit definition for CRYP_CSGCMCCM0R register  ******************/
#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos          (0U)
#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM0R_CSGCMCCM0              CRYP_CSGCMCCM0R_CSGCMCCM0_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM1R register  ******************/
#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos          (0U)
#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM1R_CSGCMCCM1              CRYP_CSGCMCCM1R_CSGCMCCM1_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM2R register  ******************/
#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos          (0U)
#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM2R_CSGCMCCM2              CRYP_CSGCMCCM2R_CSGCMCCM2_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM3R register  ******************/
#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos          (0U)
#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM3R_CSGCMCCM3              CRYP_CSGCMCCM3R_CSGCMCCM3_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM4R register  ******************/
#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos          (0U)
#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM4R_CSGCMCCM4              CRYP_CSGCMCCM4R_CSGCMCCM4_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM5R register  ******************/
#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos          (0U)
#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM5R_CSGCMCCM5              CRYP_CSGCMCCM5R_CSGCMCCM5_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM6R register  ******************/
#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos          (0U)
#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM6R_CSGCMCCM6              CRYP_CSGCMCCM6R_CSGCMCCM6_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCMCCM7R register  ******************/
#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos          (0U)
#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM7R_CSGCMCCM7              CRYP_CSGCMCCM7R_CSGCMCCM7_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */

/*******************  Bit definition for CRYP_CSGCM0R register  ******************/
#define CRYP_CSGCM0R_CSGCM0_Pos          (0U)
#define CRYP_CSGCM0R_CSGCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM0R_CSGCM0              CRYP_CSGCM0R_CSGCM0_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM1R register  ******************/
#define CRYP_CSGCM1R_CSGCM1_Pos          (0U)
#define CRYP_CSGCM1R_CSGCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM1R_CSGCM1              CRYP_CSGCM1R_CSGCM1_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM2R register  ******************/
#define CRYP_CSGCM2R_CSGCM2_Pos          (0U)
#define CRYP_CSGCM2R_CSGCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM2R_CSGCM2              CRYP_CSGCM2R_CSGCM2_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM3R register  ******************/
#define CRYP_CSGCM3R_CSGCM3_Pos          (0U)
#define CRYP_CSGCM3R_CSGCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM3R_CSGCM3              CRYP_CSGCM3R_CSGCM3_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM4R register  ******************/
#define CRYP_CSGCM4R_CSGCM4_Pos          (0U)
#define CRYP_CSGCM4R_CSGCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM4R_CSGCM4              CRYP_CSGCM4R_CSGCM4_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM5R register  ******************/
#define CRYP_CSGCM5R_CSGCM5_Pos          (0U)
#define CRYP_CSGCM5R_CSGCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM5R_CSGCM5              CRYP_CSGCM5R_CSGCM5_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM6R register  ******************/
#define CRYP_CSGCM6R_CSGCM6_Pos          (0U)
#define CRYP_CSGCM6R_CSGCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM6R_CSGCM6              CRYP_CSGCM6R_CSGCM6_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */

/*******************  Bit definition for CRYP_CSGCM7R register  ******************/
#define CRYP_CSGCM7R_CSGCM7_Pos          (0U)
#define CRYP_CSGCM7R_CSGCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM7R_CSGCM7              CRYP_CSGCM7R_CSGCM7_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */


/*********************************************************************************/
/*                                                                               */
/*                                DBGMCU                                         */
/*                                                                               */
/*********************************************************************************/
/********************  Bit definition for DBGMCU_IDCODE register  ****************/
#define DBGMCU_IDCODE_DEV_ID_Pos             (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk             (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)                /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID                 DBGMCU_IDCODE_DEV_ID_Msk                             /*!< Device ID */
#define DBGMCU_IDCODE_REV_ID_Pos             (16U)
#define DBGMCU_IDCODE_REV_ID_Msk             (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)               /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID                 DBGMCU_IDCODE_REV_ID_Msk                             /*!< Revision */

/********************  Bit definition for DBGMCU_CR register  ********************/
#define DBGMCU_CR_DBG_SLEEP_Pos              (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk              (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)                   /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP                  DBGMCU_CR_DBG_SLEEP_Msk                              /*!< Debug in Sleep mode enable */
#define DBGMCU_CR_DBG_STOP_Pos               (1U)
#define DBGMCU_CR_DBG_STOP_Msk               (0x1UL << DBGMCU_CR_DBG_STOP_Pos)                    /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP                   DBGMCU_CR_DBG_STOP_Msk                               /*!< Debug in Stop mode enable */
#define DBGMCU_CR_DBG_STANDBY_Pos            (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk            (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)                 /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY                DBGMCU_CR_DBG_STANDBY_Msk                            /*!< Debug in Standby mode enable */
#define DBGMCU_CR_DCRT_Pos                   (16U)
#define DBGMCU_CR_DCRT_Msk                   (0x1UL << DBGMCU_CR_DCRT_Pos)                        /*!< 0x00010000 */
#define DBGMCU_CR_DCRT                       DBGMCU_CR_DCRT_Msk                                   /*!< Debug credentials reset type */
#define DBGMCU_CR_TRACECLKEN_Pos             (20U)
#define DBGMCU_CR_TRACECLKEN_Msk             (0x1UL << DBGMCU_CR_TRACECLKEN_Pos)                  /*!< 0x00100000 */
#define DBGMCU_CR_TRACECLKEN                 DBGMCU_CR_TRACECLKEN_Msk                             /*!< Trace port clock enable */
#define DBGMCU_CR_DBGCKEN_Pos                (21U)
#define DBGMCU_CR_DBGCKEN_Msk                (0x1UL << DBGMCU_CR_DBGCKEN_Pos )                    /*!< 0x00200000 */
#define DBGMCU_CR_DBGCKEN                    DBGMCU_CR_DBGCKEN_Msk                                /*!< Debug clock enable */
#define DBGMCU_CR_TRGOEN_Pos                 (28U)
#define DBGMCU_CR_TRGOEN_Msk                 (0x1UL << DBGMCU_CR_TRGOEN_Pos)                      /*!< 0x10000000 */
#define DBGMCU_CR_TRGOEN                     DBGMCU_CR_TRGOEN_Msk                                 /*!< External trigger output enable */

/********************  Bit definition for DBGMCU_AHB5FZR register  ***************/
#define DBGMCU_AHB5FZR_HPDMA_0_Pos           (0U)
#define DBGMCU_AHB5FZR_HPDMA_0_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_0_Pos)                /*!< 0x00000001 */
#define DBGMCU_AHB5FZR_HPDMA_0               DBGMCU_AHB5FZR_HPDMA_0_Msk                           /*!< HPDMA channel 0 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_1_Pos           (1U)
#define DBGMCU_AHB5FZR_HPDMA_1_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_1_Pos)                /*!< 0x00000002 */
#define DBGMCU_AHB5FZR_HPDMA_1               DBGMCU_AHB5FZR_HPDMA_1_Msk                           /*!< HPDMA channel 1 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_2_Pos           (2U)
#define DBGMCU_AHB5FZR_HPDMA_2_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_2_Pos)                /*!< 0x00000004 */
#define DBGMCU_AHB5FZR_HPDMA_2               DBGMCU_AHB5FZR_HPDMA_2_Msk                           /*!< HPDMA channel 2 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_3_Pos           (3U)
#define DBGMCU_AHB5FZR_HPDMA_3_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_3_Pos)                /*!< 0x00000008 */
#define DBGMCU_AHB5FZR_HPDMA_3               DBGMCU_AHB5FZR_HPDMA_3_Msk                           /*!< HPDMA channel 3 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_4_Pos           (4U)
#define DBGMCU_AHB5FZR_HPDMA_4_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_4_Pos)                /*!< 0x00000010 */
#define DBGMCU_AHB5FZR_HPDMA_4               DBGMCU_AHB5FZR_HPDMA_4_Msk                           /*!< HPDMA channel 4 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_5_Pos           (5U)
#define DBGMCU_AHB5FZR_HPDMA_5_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_5_Pos)                /*!< 0x00000020 */
#define DBGMCU_AHB5FZR_HPDMA_5               DBGMCU_AHB5FZR_HPDMA_5_Msk                           /*!< HPDMA channel 5 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_6_Pos           (6U)
#define DBGMCU_AHB5FZR_HPDMA_6_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_6_Pos)                /*!< 0x00000040 */
#define DBGMCU_AHB5FZR_HPDMA_6               DBGMCU_AHB5FZR_HPDMA_6_Msk                           /*!< HPDMA channel 6 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_7_Pos           (7U)
#define DBGMCU_AHB5FZR_HPDMA_7_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_7_Pos)                /*!< 0x00000080 */
#define DBGMCU_AHB5FZR_HPDMA_7               DBGMCU_AHB5FZR_HPDMA_7_Msk                           /*!< HPDMA channel 7 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_8_Pos           (8U)
#define DBGMCU_AHB5FZR_HPDMA_8_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_8_Pos)                /*!< 0x00000100 */
#define DBGMCU_AHB5FZR_HPDMA_8               DBGMCU_AHB5FZR_HPDMA_8_Msk                           /*!< HPDMA channel 8 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_9_Pos           (9U)
#define DBGMCU_AHB5FZR_HPDMA_9_Msk           (0x1UL << DBGMCU_AHB5FZR_HPDMA_9_Pos)                /*!< 0x00000200 */
#define DBGMCU_AHB5FZR_HPDMA_9               DBGMCU_AHB5FZR_HPDMA_9_Msk                           /*!< HPDMA channel 9 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_10_Pos          (10U)
#define DBGMCU_AHB5FZR_HPDMA_10_Msk          (0x1UL << DBGMCU_AHB5FZR_HPDMA_10_Pos)               /*!< 0x00000400 */
#define DBGMCU_AHB5FZR_HPDMA_10              DBGMCU_AHB5FZR_HPDMA_10_Msk                          /*!< HPDMA channel 10 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_11_Pos          (11U)
#define DBGMCU_AHB5FZR_HPDMA_11_Msk          (0x1UL << DBGMCU_AHB5FZR_HPDMA_11_Pos)               /*!< 0x00000800 */
#define DBGMCU_AHB5FZR_HPDMA_11              DBGMCU_AHB5FZR_HPDMA_11_Msk                          /*!< HPDMA channel 11 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_12_Pos          (12U)
#define DBGMCU_AHB5FZR_HPDMA_12_Msk          (0x1UL << DBGMCU_AHB5FZR_HPDMA_12_Pos)               /*!< 0x00001000 */
#define DBGMCU_AHB5FZR_HPDMA_12              DBGMCU_AHB5FZR_HPDMA_12_Msk                          /*!< HPDMA channel 12 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_13_Pos          (13U)
#define DBGMCU_AHB5FZR_HPDMA_13_Msk          (0x1UL << DBGMCU_AHB5FZR_HPDMA_13_Pos)               /*!< 0x00002000 */
#define DBGMCU_AHB5FZR_HPDMA_13              DBGMCU_AHB5FZR_HPDMA_13_Msk                          /*!< HPDMA channel 13 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_14_Pos          (14U)
#define DBGMCU_AHB5FZR_HPDMA_14_Msk          (0x1UL << DBGMCU_AHB5FZR_HPDMA_14_Pos)               /*!< 0x00004000 */
#define DBGMCU_AHB5FZR_HPDMA_14              DBGMCU_AHB5FZR_HPDMA_14_Msk                          /*!< HPDMA channel 14 stop in debug */
#define DBGMCU_AHB5FZR_HPDMA_15_Pos          (15U)
#define DBGMCU_AHB5FZR_HPDMA_15_Msk          (0x1UL << DBGMCU_AHB5FZR_HPDMA_15_Pos)               /*!< 0x00008000 */
#define DBGMCU_AHB5FZR_HPDMA_15              DBGMCU_AHB5FZR_HPDMA_15_Msk                          /*!< HPDMA channel 15 stop in debug */

/********************  Bit definition for DBGMCU_AHB1FZR register  ***************/
#define DBGMCU_AHB1FZR_GPDMA_0_Pos           (0U)
#define DBGMCU_AHB1FZR_GPDMA_0_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_0_Pos)                /*!< 0x00000001 */
#define DBGMCU_AHB1FZR_GPDMA_0               DBGMCU_AHB1FZR_GPDMA_0_Msk                           /*!< GPDMA channel 0 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_1_Pos           (1U)
#define DBGMCU_AHB1FZR_GPDMA_1_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_1_Pos)                /*!< 0x00000002 */
#define DBGMCU_AHB1FZR_GPDMA_1               DBGMCU_AHB1FZR_GPDMA_1_Msk                           /*!< GPDMA channel 1 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_2_Pos           (2U)
#define DBGMCU_AHB1FZR_GPDMA_2_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_2_Pos)                /*!< 0x00000004 */
#define DBGMCU_AHB1FZR_GPDMA_2               DBGMCU_AHB1FZR_GPDMA_2_Msk                           /*!< GPDMA channel 2 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_3_Pos           (3U)
#define DBGMCU_AHB1FZR_GPDMA_3_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_3_Pos)                /*!< 0x00000008 */
#define DBGMCU_AHB1FZR_GPDMA_3               DBGMCU_AHB1FZR_GPDMA_3_Msk                           /*!< GPDMA channel 3 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_4_Pos           (4U)
#define DBGMCU_AHB1FZR_GPDMA_4_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_4_Pos)                /*!< 0x00000010 */
#define DBGMCU_AHB1FZR_GPDMA_4               DBGMCU_AHB1FZR_GPDMA_4_Msk                           /*!< GPDMA channel 4 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_5_Pos           (5U)
#define DBGMCU_AHB1FZR_GPDMA_5_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_5_Pos)                /*!< 0x00000020 */
#define DBGMCU_AHB1FZR_GPDMA_5               DBGMCU_AHB1FZR_GPDMA_5_Msk                           /*!< GPDMA channel 5 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_6_Pos           (6U)
#define DBGMCU_AHB1FZR_GPDMA_6_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_6_Pos)                /*!< 0x00000040 */
#define DBGMCU_AHB1FZR_GPDMA_6               DBGMCU_AHB1FZR_GPDMA_6_Msk                           /*!< GPDMA channel 6 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_7_Pos           (7U)
#define DBGMCU_AHB1FZR_GPDMA_7_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_7_Pos)                /*!< 0x00000080 */
#define DBGMCU_AHB1FZR_GPDMA_7               DBGMCU_AHB1FZR_GPDMA_7_Msk                           /*!< GPDMA channel 7 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_8_Pos           (8U)
#define DBGMCU_AHB1FZR_GPDMA_8_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_8_Pos)                /*!< 0x00000100 */
#define DBGMCU_AHB1FZR_GPDMA_8               DBGMCU_AHB1FZR_GPDMA_8_Msk                           /*!< GPDMA channel 8 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_9_Pos           (9U)
#define DBGMCU_AHB1FZR_GPDMA_9_Msk           (0x1UL << DBGMCU_AHB1FZR_GPDMA_9_Pos)                /*!< 0x00000200 */
#define DBGMCU_AHB1FZR_GPDMA_9               DBGMCU_AHB1FZR_GPDMA_9_Msk                           /*!< GPDMA channel 9 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_10_Pos          (10U)
#define DBGMCU_AHB1FZR_GPDMA_10_Msk          (0x1UL << DBGMCU_AHB1FZR_GPDMA_10_Pos)               /*!< 0x00000400 */
#define DBGMCU_AHB1FZR_GPDMA_10              DBGMCU_AHB1FZR_GPDMA_10_Msk                          /*!< GPDMA channel 10 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_11_Pos          (11U)
#define DBGMCU_AHB1FZR_GPDMA_11_Msk          (0x1UL << DBGMCU_AHB1FZR_GPDMA_11_Pos)               /*!< 0x00000800 */
#define DBGMCU_AHB1FZR_GPDMA_11              DBGMCU_AHB1FZR_GPDMA_11_Msk                          /*!< GPDMA channel 11 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_12_Pos          (12U)
#define DBGMCU_AHB1FZR_GPDMA_12_Msk          (0x1UL << DBGMCU_AHB1FZR_GPDMA_12_Pos)               /*!< 0x00001000 */
#define DBGMCU_AHB1FZR_GPDMA_12              DBGMCU_AHB1FZR_GPDMA_12_Msk                          /*!< GPDMA channel 12 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_13_Pos          (13U)
#define DBGMCU_AHB1FZR_GPDMA_13_Msk          (0x1UL << DBGMCU_AHB1FZR_GPDMA_13_Pos)               /*!< 0x00002000 */
#define DBGMCU_AHB1FZR_GPDMA_13              DBGMCU_AHB1FZR_GPDMA_13_Msk                          /*!< GPDMA channel 13 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_14_Pos          (14U)
#define DBGMCU_AHB1FZR_GPDMA_14_Msk          (0x1UL << DBGMCU_AHB1FZR_GPDMA_14_Pos)               /*!< 0x00004000 */
#define DBGMCU_AHB1FZR_GPDMA_14              DBGMCU_AHB1FZR_GPDMA_14_Msk                          /*!< GPDMA channel 14 stop in debug */
#define DBGMCU_AHB1FZR_GPDMA_15_Pos          (15U)
#define DBGMCU_AHB1FZR_GPDMA_15_Msk          (0x1UL << DBGMCU_AHB1FZR_GPDMA_15_Pos)               /*!< 0x00008000 */
#define DBGMCU_AHB1FZR_GPDMA_15              DBGMCU_AHB1FZR_GPDMA_15_Msk                          /*!< GPDMA channel 15 stop in debug */

/********************  Bit definition for DBGMCU_APB1FZR register  ***************/
#define DBGMCU_APB1FZR_TIM2_Pos              (0U)
#define DBGMCU_APB1FZR_TIM2_Msk              (0x1UL << DBGMCU_APB1FZR_TIM2_Pos)                   /*!< 0x00000001 */
#define DBGMCU_APB1FZR_TIM2                  DBGMCU_APB1FZR_TIM2_Msk                              /*!< TIM2 stop in debug */
#define DBGMCU_APB1FZR_TIM3_Pos              (1U)
#define DBGMCU_APB1FZR_TIM3_Msk              (0x1UL << DBGMCU_APB1FZR_TIM3_Pos)                   /*!< 0x00000002 */
#define DBGMCU_APB1FZR_TIM3                  DBGMCU_APB1FZR_TIM3_Msk                              /*!< TIM3 stop in debug */
#define DBGMCU_APB1FZR_TIM4_Pos              (2U)
#define DBGMCU_APB1FZR_TIM4_Msk              (0x1UL << DBGMCU_APB1FZR_TIM4_Pos)                   /*!< 0x00000004 */
#define DBGMCU_APB1FZR_TIM4                  DBGMCU_APB1FZR_TIM4_Msk                              /*!< TIM4 stop in debug */
#define DBGMCU_APB1FZR_TIM5_Pos              (3U)
#define DBGMCU_APB1FZR_TIM5_Msk              (0x1UL << DBGMCU_APB1FZR_TIM5_Pos)                   /*!< 0x00000008 */
#define DBGMCU_APB1FZR_TIM5                  DBGMCU_APB1FZR_TIM5_Msk                              /*!< TIM5 stop in debug */
#define DBGMCU_APB1FZR_TIM6_Pos              (4U)
#define DBGMCU_APB1FZR_TIM6_Msk              (0x1UL << DBGMCU_APB1FZR_TIM6_Pos)                   /*!< 0x00000010 */
#define DBGMCU_APB1FZR_TIM6                  DBGMCU_APB1FZR_TIM6_Msk                              /*!< TIM6 stop in debug */
#define DBGMCU_APB1FZR_TIM7_Pos              (5U)
#define DBGMCU_APB1FZR_TIM7_Msk              (0x1UL << DBGMCU_APB1FZR_TIM7_Pos)                   /*!< 0x00000020 */
#define DBGMCU_APB1FZR_TIM7                  DBGMCU_APB1FZR_TIM7_Msk                              /*!< TIM7 stop in debug */
#define DBGMCU_APB1FZR_TIM12_Pos             (6U)
#define DBGMCU_APB1FZR_TIM12_Msk             (0x1UL << DBGMCU_APB1FZR_TIM12_Pos)                  /*!< 0x00000040 */
#define DBGMCU_APB1FZR_TIM12                 DBGMCU_APB1FZR_TIM12_Msk                             /*!< TIM12 stop in debug */
#define DBGMCU_APB1FZR_TIM13_Pos             (7U)
#define DBGMCU_APB1FZR_TIM13_Msk             (0x1UL << DBGMCU_APB1FZR_TIM13_Pos)                  /*!< 0x00000080 */
#define DBGMCU_APB1FZR_TIM13                 DBGMCU_APB1FZR_TIM13_Msk                             /*!< TIM13 stop in debug */
#define DBGMCU_APB1FZR_TIM14_Pos             (8U)
#define DBGMCU_APB1FZR_TIM14_Msk             (0x1UL << DBGMCU_APB1FZR_TIM14_Pos)                  /*!< 0x00000100 */
#define DBGMCU_APB1FZR_TIM14                 DBGMCU_APB1FZR_TIM14_Msk                             /*!< TIM14 stop in debug */
#define DBGMCU_APB1FZR_LPTIM1_Pos            (9U)
#define DBGMCU_APB1FZR_LPTIM1_Msk            (0x1UL << DBGMCU_APB1FZR_LPTIM1_Pos)                 /*!< 0x00000200 */
#define DBGMCU_APB1FZR_LPTIM1                DBGMCU_APB1FZR_LPTIM1_Msk                            /*!< LPTIM1 stop in debug */
#define DBGMCU_APB1FZR_WWDG_Pos              (11U)
#define DBGMCU_APB1FZR_WWDG_Msk              (0x1UL << DBGMCU_APB1FZR_WWDG_Pos)                   /*!< 0x00000800 */
#define DBGMCU_APB1FZR_WWDG                  DBGMCU_APB1FZR_WWDG_Msk                              /*!< WWDG stop in debug */
#define DBGMCU_APB1FZR_I2C1_Pos              (21U)
#define DBGMCU_APB1FZR_I2C1_Msk              (0x1UL << DBGMCU_APB1FZR_I2C1_Pos)                   /*!< 0x00200000 */
#define DBGMCU_APB1FZR_I2C1                  DBGMCU_APB1FZR_I2C1_Msk                              /*!< I2C1 SMBUS timeout stop in debug */
#define DBGMCU_APB1FZR_I2C2_Pos              (22U)
#define DBGMCU_APB1FZR_I2C2_Msk              (0x1UL << DBGMCU_APB1FZR_I2C2_Pos)                   /*!< 0x00400000 */
#define DBGMCU_APB1FZR_I2C2                  DBGMCU_APB1FZR_I2C2_Msk                              /*!< I2C2 SMBUS timeout stop in debug */
#define DBGMCU_APB1FZR_I2C3_Pos              (23U)
#define DBGMCU_APB1FZR_I2C3_Msk              (0x1UL << DBGMCU_APB1FZR_I2C3_Pos)                   /*!< 0x00800000 */
#define DBGMCU_APB1FZR_I2C3                  DBGMCU_APB1FZR_I2C3_Msk                              /*!< I2C3 SMBUS timeout stop in debug */

/********************  Bit definition for DBGMCU_APB2FZR register  ***************/
#define DBGMCU_APB2FZR_TIM1_Pos              (0U)
#define DBGMCU_APB2FZR_TIM1_Msk              (0x1UL << DBGMCU_APB2FZR_TIM1_Pos)                   /*!< 0x00000001 */
#define DBGMCU_APB2FZR_TIM1                  DBGMCU_APB2FZR_TIM1_Msk                              /*!< TIM1 stop in debug */
#define DBGMCU_APB2FZR_TIM15_Pos             (16U)
#define DBGMCU_APB2FZR_TIM15_Msk             (0x1UL << DBGMCU_APB2FZR_TIM15_Pos)                  /*!< 0x00010000 */
#define DBGMCU_APB2FZR_TIM15                 DBGMCU_APB2FZR_TIM15_Msk                             /*!< TIM15 stop in debug */
#define DBGMCU_APB2FZR_TIM16_Pos             (17U)
#define DBGMCU_APB2FZR_TIM16_Msk             (0x1UL << DBGMCU_APB2FZR_TIM16_Pos)                  /*!< 0x00020000 */
#define DBGMCU_APB2FZR_TIM16                 DBGMCU_APB2FZR_TIM16_Msk                             /*!< TIM16 stop in debug */
#define DBGMCU_APB2FZR_TIM17_Pos             (18U)
#define DBGMCU_APB2FZR_TIM17_Msk             (0x1UL << DBGMCU_APB2FZR_TIM17_Pos)                  /*!< 0x00040000 */
#define DBGMCU_APB2FZR_TIM17                 DBGMCU_APB2FZR_TIM17_Msk                             /*!< TIM17 stop in debug */
#define DBGMCU_APB2FZR_TIM9_Pos              (19U)
#define DBGMCU_APB2FZR_TIM9_Msk              (0x1UL << DBGMCU_APB2FZR_TIM9_Pos)                   /*!< 0x00080000 */
#define DBGMCU_APB2FZR_TIM9                  DBGMCU_APB2FZR_TIM9_Msk                              /*!< TIM9 stop in debug */

/********************  Bit definition for DBGMCU_APB4FZR register  ***************/
#define DBGMCU_APB4FZR_LPTIM2_Pos            (9U)
#define DBGMCU_APB4FZR_LPTIM2_Msk            (0x1UL << DBGMCU_APB4FZR_LPTIM2_Pos)                 /*!< 0x00000200 */
#define DBGMCU_APB4FZR_LPTIM2                DBGMCU_APB4FZR_LPTIM2_Msk                            /*!< LPTIM2 stop in debug */
#define DBGMCU_APB4FZR_LPTIM3_Pos            (10U)
#define DBGMCU_APB4FZR_LPTIM3_Msk            (0x1UL << DBGMCU_APB4FZR_LPTIM3_Pos)                 /*!< 0x00000400 */
#define DBGMCU_APB4FZR_LPTIM3                DBGMCU_APB4FZR_LPTIM3_Msk                            /*!< LPTIM3 stop in debug */
#define DBGMCU_APB4FZR_LPTIM4_Pos            (11U)
#define DBGMCU_APB4FZR_LPTIM4_Msk            (0x1UL << DBGMCU_APB4FZR_LPTIM4_Pos)                 /*!< 0x00000800 */
#define DBGMCU_APB4FZR_LPTIM4                DBGMCU_APB4FZR_LPTIM4_Msk                            /*!< LPTIM4 stop in debug */
#define DBGMCU_APB4FZR_LPTIM5_Pos            (12U)
#define DBGMCU_APB4FZR_LPTIM5_Msk            (0x1UL << DBGMCU_APB4FZR_LPTIM5_Pos)                 /*!< 0x00001000 */
#define DBGMCU_APB4FZR_LPTIM5                DBGMCU_APB4FZR_LPTIM5_Msk                            /*!< LPTIM5 stop in debug */
#define DBGMCU_APB4FZR_RTC_Pos               (16U)
#define DBGMCU_APB4FZR_RTC_Msk               (0x1UL << DBGMCU_APB4FZR_RTC_Pos)                    /*!< 0x00010000 */
#define DBGMCU_APB4FZR_RTC                   DBGMCU_APB4FZR_RTC_Msk                               /*!< RTC stop in debug */
#define DBGMCU_APB4FZR_IWDG_Pos              (18U)
#define DBGMCU_APB4FZR_IWDG_Msk              (0x1UL << DBGMCU_APB4FZR_IWDG_Pos)                   /*!< 0x00040000 */
#define DBGMCU_APB4FZR_IWDG                  DBGMCU_APB4FZR_IWDG_Msk                              /*!< Independent watchdog for stop in debug */

/******************  Bit definition for DBGMCU_SR register  ***********/
#define DBGMCU_SR_AP_PRESENT_Pos             (0U)
#define DBGMCU_SR_AP_PRESENT_Msk             (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos)               /*!< 0x0000FFFF */
#define DBGMCU_SR_AP_PRESENT                 DBGMCU_SR_AP_PRESENT_Msk
#define DBGMCU_SR_AP_ENABLED_Pos             (16U)
#define DBGMCU_SR_AP_ENABLED_Msk             (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos)               /*!< 0xFFFF0000 */
#define DBGMCU_SR_AP_ENABLED                 DBGMCU_SR_AP_ENABLED_Msk

/******************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ***********/
#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos     (0U)
#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk     (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos)   /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_AUTH_HOST_MESSAGE         DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk                     /*!< Debug host to device mailbox message */

/******************  Bit definition for DBGMCU_DBG_AUTH_DEVICE register  ************/
#define DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Pos   (0U)
#define DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Msk   (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Pos) /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_AUTH_DEVICE_MESSAGE       DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Msk                   /*!< Device to debug host mailbox message */

/******************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ************/
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos     (0U)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk     (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos)          /*!< 0x00000001 */
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK         DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk                     /*!< Host to device acknowledge */
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_Pos      (1U)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_Msk      (0x1UL << DBGMCU_DBG_AUTH_ACK_DEV_ACK_Pos)           /*!< 0x00000002 */
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK          DBGMCU_DBG_AUTH_ACK_DEV_ACK_Msk                      /*!< Device to host acknowledge */

/*********************  Bit definition for DBGMCU_PIDR4 register  ****************/
#define DBGMCU_PIDR4_JEP106CON_Pos           (0U)
#define DBGMCU_PIDR4_JEP106CON_Msk           (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)                /*!< 0x0000000F */
#define DBGMCU_PIDR4_JEP106CON               DBGMCU_PIDR4_JEP106CON_Msk                           /*!< JEP106 continuation code */
#define DBGMCU_PIDR4_SIZE_Pos                (4U)
#define DBGMCU_PIDR4_SIZE_Msk                (0xFUL << DBGMCU_PIDR4_SIZE_Pos)                     /*!< 0x000000F0 */
#define DBGMCU_PIDR4_SIZE                    DBGMCU_PIDR4_SIZE_Msk                                /*!< Register file size */

/*********************  Bit definition for DBGMCU_PIDR0 register  ****************/
#define DBGMCU_PIDR0_PARTNUM_Pos             (0U)
#define DBGMCU_PIDR0_PARTNUM_Msk             (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)                 /*!< 0x000000FF */
#define DBGMCU_PIDR0_PARTNUM                 DBGMCU_PIDR0_PARTNUM_Msk                             /*!< Part number field, bits [7:0] */

/*********************  Bit definition for DBGMCU_PIDR1 register  ****************/
#define DBGMCU_PIDR1_PARTNUM_Pos             (0U)
#define DBGMCU_PIDR1_PARTNUM_Msk             (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)                  /*!< 0x0000000F */
#define DBGMCU_PIDR1_PARTNUM                 DBGMCU_PIDR1_PARTNUM_Msk                             /*!< Part number field, bits [11:8] */
#define DBGMCU_PIDR1_JEP106ID_Pos            (4U)
#define DBGMCU_PIDR1_JEP106ID_Msk            (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)                 /*!< 0x000000F0 */
#define DBGMCU_PIDR1_JEP106ID                DBGMCU_PIDR1_JEP106ID_Msk                            /*!< JEP106 identity code field, bits [3:0] */

/*********************  Bit definition for DBGMCU_PIDR2 register  ****************/
#define DBGMCU_PIDR2_JEP106ID_Pos            (0U)
#define DBGMCU_PIDR2_JEP106ID_Msk            (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)                 /*!< 0x00000007 */
#define DBGMCU_PIDR2_JEP106ID                DBGMCU_PIDR2_JEP106ID_Msk                            /*!< JEP106 identity code field, bits [6:4] */
#define DBGMCU_PIDR2_JEDEC_Pos               (3U)
#define DBGMCU_PIDR2_JEDEC_Msk               (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)                    /*!< 0x00000008 */
#define DBGMCU_PIDR2_JEDEC                   DBGMCU_PIDR2_JEDEC_Msk                               /*!< JEDEC assigned value */
#define DBGMCU_PIDR2_REVISION_Pos            (4U)
#define DBGMCU_PIDR2_REVISION_Msk            (0xFUL << DBGMCU_PIDR2_REVISION_Pos)                 /*!< 0x000000F0 */
#define DBGMCU_PIDR2_REVISION                DBGMCU_PIDR2_REVISION_Msk                            /*!< Component revision number */

/*********************  Bit definition for DBGMCU_PIDR3 register  ****************/
#define DBGMCU_PIDR3_CMOD_Pos                (0U)
#define DBGMCU_PIDR3_CMOD_Msk                (0xFUL << DBGMCU_PIDR3_CMOD_Pos)                     /*!< 0x0000000F */
#define DBGMCU_PIDR3_CMOD                    DBGMCU_PIDR3_CMOD_Msk                                /*!< Customer modified */
#define DBGMCU_PIDR3_REVAND_Pos              (4U)
#define DBGMCU_PIDR3_REVAND_Msk              (0xFUL << DBGMCU_PIDR3_REVAND_Pos)                   /*!< 0x000000F0 */
#define DBGMCU_PIDR3_REVAND                  DBGMCU_PIDR3_REVAND_Msk                              /*!< Metal fix version */

/*********************  Bit definition for DBGMCU_CIDR0 register  ****************/
#define DBGMCU_CIDR0_PREAMBLE_Pos            (0U)
#define DBGMCU_CIDR0_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)                /*!< 0x000000FF */
#define DBGMCU_CIDR0_PREAMBLE                DBGMCU_CIDR0_PREAMBLE_Msk                            /*!< Component ID field, bits [7:0] */

/*********************  Bit definition for DBGMCU_CIDR1 register  ****************/
#define DBGMCU_CIDR1_PREAMBLE_Pos            (0U)
#define DBGMCU_CIDR1_PREAMBLE_Msk            (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)                 /*!< 0x0000000F */
#define DBGMCU_CIDR1_PREAMBLE                DBGMCU_CIDR1_PREAMBLE_Msk                            /*!< Component ID field, bits [11:8] */
#define DBGMCU_CIDR1_CLASS_Pos               (4U)
#define DBGMCU_CIDR1_CLASS_Msk               (0xFUL << DBGMCU_CIDR1_CLASS_Pos)                    /*!< 0x000000F0 */
#define DBGMCU_CIDR1_CLASS                   DBGMCU_CIDR1_CLASS_Msk                               /*!< Component ID field, bits [15:12] - component class */

/*********************  Bit definition for DBGMCU_CIDR2 register  ****************/
#define DBGMCU_CIDR2_PREAMBLE_Pos            (0U)
#define DBGMCU_CIDR2_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)                /*!< 0x000000FF */
#define DBGMCU_CIDR2_PREAMBLE                DBGMCU_CIDR2_PREAMBLE_Msk                            /*!< Component ID field, bits [23:16] */

/*********************  Bit definition for DBGMCU_CIDR3 register  ****************/
#define DBGMCU_CIDR3_PREAMBLE_Pos            (0U)
#define DBGMCU_CIDR3_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)                /*!< 0x000000FF */
#define DBGMCU_CIDR3_PREAMBLE                DBGMCU_CIDR3_PREAMBLE_Msk                            /*!< Component ID field, bits [31:24] */

/******************************************************************************/
/*                                                                            */
/*                                    DCMIPP                                  */
/*                                                                            */
/******************************************************************************/

#define DCMIPP_NUM_OF_PIPES 0x1U
/*******************  Bit definition for DCMIPP_IPGR1 register  ***************/
#define DCMIPP_IPGR1_MEMORYPAGE_Pos    (0U)
#define DCMIPP_IPGR1_MEMORYPAGE_Msk    (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos)  /*!< 0x00000007 */
#define DCMIPP_IPGR1_MEMORYPAGE        DCMIPP_IPGR1_MEMORYPAGE_Msk             /*!< MEMORYPAGE[2:0] */
#define DCMIPP_IPGR1_QOS_MODE_Pos      (24U)
#define DCMIPP_IPGR1_QOS_MODE_Msk      (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos)    /*!< 0x01000000 */
#define DCMIPP_IPGR1_QOS_MODE          DCMIPP_IPGR1_QOS_MODE_Msk               /*!< Quality Of Service */

/*******************  Bit definition for DCMIPP_IPGR2 register  ***************/
#define DCMIPP_IPGR2_PSTART_Pos        (0U)
#define DCMIPP_IPGR2_PSTART_Msk        (0x1UL << DCMIPP_IPGR2_PSTART_Pos)      /*!< 0x00000001 */
#define DCMIPP_IPGR2_PSTART            DCMIPP_IPGR2_PSTART_Msk                 /*!< request to lock the IP-Plug */

/*******************  Bit definition for DCMIPP_IPGR3 register  ***************/
#define DCMIPP_IPGR3_IDLE_Pos          (0U)
#define DCMIPP_IPGR3_IDLE_Msk          (0x1UL << DCMIPP_IPGR3_IDLE_Pos)        /*!< 0x00000001 */
#define DCMIPP_IPGR3_IDLE              DCMIPP_IPGR3_IDLE_Msk                   /*!< request to lock the IP-Plug */

/*******************  Bit definition for DCMIPP_IPGR8 register  ***************/
#define DCMIPP_IPGR8_DID_Pos           (0U)
#define DCMIPP_IPGR8_DID_Msk           (0x3FUL << DCMIPP_IPGR8_DID_Pos)        /*!< 0x0000003F */
#define DCMIPP_IPGR8_DID               DCMIPP_IPGR8_DID_Msk                    /*!< DID[5:0]: division identifier */
#define DCMIPP_IPGR8_REVID_Pos         (8U)
#define DCMIPP_IPGR8_REVID_Msk         (0x1FUL << DCMIPP_IPGR8_REVID_Pos)      /*!< 0x00001F00 */
#define DCMIPP_IPGR8_REVID             DCMIPP_IPGR8_REVID_Msk                  /*!< REVID[4:0]: revision identifier */
#define DCMIPP_IPGR8_ARCHIID_Pos       (16U)
#define DCMIPP_IPGR8_ARCHIID_Msk       (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos)    /*!< 0x001F0000 */
#define DCMIPP_IPGR8_ARCHIID           DCMIPP_IPGR8_ARCHIID_Msk                /*!< ARCHIID[4:0]: architecture identifier */
#define DCMIPP_IPGR8_IPID_Pos          (24U)
#define DCMIPP_IPGR8_IPID_Msk          (0xFFUL << DCMIPP_IPGR8_IPID_Pos)       /*!< 0xFF000000 */
#define DCMIPP_IPGR8_IPID              DCMIPP_IPGR8_IPID_Msk                   /*!< IPPID[7:0]: IP identifier */

/*******************  Bit definition for DCMIPP_IPC1R1 register  **************/
#define DCMIPP_IPC1R1_TRAFFIC_Pos      (0U)
#define DCMIPP_IPC1R1_TRAFFIC_Msk      (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos)    /*!< 0x00000007 */
#define DCMIPP_IPC1R1_TRAFFIC          DCMIPP_IPC1R1_TRAFFIC_Msk               /*!< TRAFFIC[2:0] */
#define DCMIPP_IPC1R1_OTR_Pos          (8U)
#define DCMIPP_IPC1R1_OTR_Msk          (0x3UL << DCMIPP_IPC1R1_OTR_Pos)        /*!< 0x00000300 */
#define DCMIPP_IPC1R1_OTR              DCMIPP_IPC1R1_OTR_Msk                   /*!< OTR[1:0]: max outstanding transactions */

/*******************  Bit definition for DCMIPP_IPC1R2 register  **************/
#define DCMIPP_IPC1R2_WLRU_Pos         (16U)
#define DCMIPP_IPC1R2_WLRU_Msk         (0xFUL << DCMIPP_IPC1R2_WLRU_Pos)       /*!< 0x000F0000 */
#define DCMIPP_IPC1R2_WLRU             DCMIPP_IPC1R2_WLRU_Msk                  /*!< WLRU[3:0]: ratio for WLRU[3:0] arbitration */

/*******************  Bit definition for DCMIPP_IPC1R3 register  **************/
#define DCMIPP_IPC1R3_DPREGSTART_Pos   (0U)
#define DCMIPP_IPC1R3_DPREGSTART_Msk   (0x1FUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x0000001F */
#define DCMIPP_IPC1R3_DPREGSTART       DCMIPP_IPC1R3_DPREGSTART_Msk            /*!< DPREGSTART[4:0]: start word */
#define DCMIPP_IPC1R3_DPREGEND_Pos     (16U)
#define DCMIPP_IPC1R3_DPREGEND_Msk     (0x1FUL << DCMIPP_IPC1R3_DPREGEND_Pos)  /*!< 0x001F0000 */
#define DCMIPP_IPC1R3_DPREGEND         DCMIPP_IPC1R3_DPREGEND_Msk              /*!< DPREGEND[4:0]: end word */

/*******************  Bit definition for DCMIPP_PRCR register  ****************/
#define DCMIPP_PRCR_ESS_Pos            (4U)
#define DCMIPP_PRCR_ESS_Msk            (0x1UL << DCMIPP_PRCR_ESS_Pos)          /*!< 0x00000010 */
#define DCMIPP_PRCR_ESS                DCMIPP_PRCR_ESS_Msk                     /*!< Embedded synchronization select */
#define DCMIPP_PRCR_PCKPOL_Pos         (5U)
#define DCMIPP_PRCR_PCKPOL_Msk         (0x1UL << DCMIPP_PRCR_PCKPOL_Pos)       /*!< 0x00000020 */
#define DCMIPP_PRCR_PCKPOL             DCMIPP_PRCR_PCKPOL_Msk                  /*!< Pixel clock polarity */
#define DCMIPP_PRCR_HSPOL_Pos          (6U)
#define DCMIPP_PRCR_HSPOL_Msk          (0x1UL << DCMIPP_PRCR_HSPOL_Pos)        /*!< 0x00000040 */
#define DCMIPP_PRCR_HSPOL              DCMIPP_PRCR_HSPOL_Msk                   /*!< Horizontal synchronization polarity */
#define DCMIPP_PRCR_VSPOL_Pos          (7U)
#define DCMIPP_PRCR_VSPOL_Msk          (0x1UL << DCMIPP_PRCR_VSPOL_Pos)        /*!< 0x00000080 */
#define DCMIPP_PRCR_VSPOL              DCMIPP_PRCR_VSPOL_Msk                   /*!< Vertical synchronization polarity */
#define DCMIPP_PRCR_EDM_Pos            (10U)
#define DCMIPP_PRCR_EDM_Msk            (0x7UL << DCMIPP_PRCR_EDM_Pos)          /*!< 0x00001C00 */
#define DCMIPP_PRCR_EDM                DCMIPP_PRCR_EDM_Msk                     /*!< EDM[2:0]: Extended data mode */
#define DCMIPP_PRCR_ENABLE_Pos         (14U)
#define DCMIPP_PRCR_ENABLE_Msk         (0x1UL << DCMIPP_PRCR_ENABLE_Pos)       /*!< 0x00004000 */
#define DCMIPP_PRCR_ENABLE             DCMIPP_PRCR_ENABLE_Msk                  /*!< Parallel Interface enable */
#define DCMIPP_PRCR_FORMAT_Pos         (16U)
#define DCMIPP_PRCR_FORMAT_Msk         (0xFFUL << DCMIPP_PRCR_FORMAT_Pos)      /*!< 0x00FF0000 */
#define DCMIPP_PRCR_FORMAT             DCMIPP_PRCR_FORMAT_Msk                  /*!< FORMAT[7:0] */
#define DCMIPP_PRCR_SWAPCYCLES_Pos     (25U)
#define DCMIPP_PRCR_SWAPCYCLES_Msk     (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos)   /*!< 0x02000000 */
#define DCMIPP_PRCR_SWAPCYCLES         DCMIPP_PRCR_SWAPCYCLES_Msk              /*!< swap data */
#define DCMIPP_PRCR_SWAPBITS_Pos       (26U)
#define DCMIPP_PRCR_SWAPBITS_Msk       (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos)     /*!< 0x04000000 */
#define DCMIPP_PRCR_SWAPBITS           DCMIPP_PRCR_SWAPBITS_Msk                /*!< swap lsb vs msb */

/*******************  Bit definition for DCMIPP_PRESCR register  **************/
#define DCMIPP_PRESCR_FSC_Pos          (0U)
#define DCMIPP_PRESCR_FSC_Msk          (0xFFUL << DCMIPP_PRESCR_FSC_Pos)       /*!< 0x000000FF */
#define DCMIPP_PRESCR_FSC              DCMIPP_PRESCR_FSC_Msk                   /*!< Frame start delimiter code */
#define DCMIPP_PRESCR_LSC_Pos          (8U)
#define DCMIPP_PRESCR_LSC_Msk          (0xFFUL << DCMIPP_PRESCR_LSC_Pos)       /*!< 0x0000FF00 */
#define DCMIPP_PRESCR_LSC              DCMIPP_PRESCR_LSC_Msk                   /*!< Line start delimiter code */
#define DCMIPP_PRESCR_LEC_Pos          (16U)
#define DCMIPP_PRESCR_LEC_Msk          (0xFFUL << DCMIPP_PRESCR_LEC_Pos)       /*!< 0x00FF0000 */
#define DCMIPP_PRESCR_LEC              DCMIPP_PRESCR_LEC_Msk                   /*!< Line end delimiter code */
#define DCMIPP_PRESCR_FEC_Pos          (24U)
#define DCMIPP_PRESCR_FEC_Msk          (0xFFUL << DCMIPP_PRESCR_FEC_Pos)       /*!< 0xFF000000 */
#define DCMIPP_PRESCR_FEC              DCMIPP_PRESCR_FEC_Msk                   /*!< Frame end delimiter code */

/*******************  Bit definition for DCMIPP_PRESUR register  **************/
#define DCMIPP_PRESUR_FSU_Pos          (0U)
#define DCMIPP_PRESUR_FSU_Msk          (0xFFUL << DCMIPP_PRESUR_FSU_Pos)       /*!< 0x000000FF */
#define DCMIPP_PRESUR_FSU              DCMIPP_PRESUR_FSU_Msk                   /*!< Frame start delimiter unmask */
#define DCMIPP_PRESUR_LSU_Pos          (8U)
#define DCMIPP_PRESUR_LSU_Msk          (0xFFUL << DCMIPP_PRESUR_LSU_Pos)       /*!< 0x0000FF00 */
#define DCMIPP_PRESUR_LSU              DCMIPP_PRESUR_LSU_Msk                   /*!< Line start delimiter unmask */
#define DCMIPP_PRESUR_LEU_Pos          (16U)
#define DCMIPP_PRESUR_LEU_Msk          (0xFFUL << DCMIPP_PRESUR_LEU_Pos)       /*!< 0x00FF0000 */
#define DCMIPP_PRESUR_LEU              DCMIPP_PRESUR_LEU_Msk                   /*!< Line end delimiter unmask */
#define DCMIPP_PRESUR_FEU_Pos          (24U)
#define DCMIPP_PRESUR_FEU_Msk          (0xFFUL << DCMIPP_PRESUR_FEU_Pos)       /*!< 0xFF000000 */
#define DCMIPP_PRESUR_FEU              DCMIPP_PRESUR_FEU_Msk                   /*!< Frame end delimiter unmask */

/*******************  Bit definition for DCMIPP_PRIER register  ***************/
#define DCMIPP_PRIER_ERRIE_Pos         (6U)
#define DCMIPP_PRIER_ERRIE_Msk         (0x1UL << DCMIPP_PRIER_ERRIE_Pos)       /*!< 0x00000040 */
#define DCMIPP_PRIER_ERRIE             DCMIPP_PRIER_ERRIE_Msk                  /*!< Synchronization error interrupt enable */

/*******************  Bit definition for DCMIPP_PRSR register  ****************/
#define DCMIPP_PRSR_ERRF_Pos           (6U)
#define DCMIPP_PRSR_ERRF_Msk           (0x1UL << DCMIPP_PRSR_ERRF_Pos)         /*!< 0x00000040 */
#define DCMIPP_PRSR_ERRF               DCMIPP_PRSR_ERRF_Msk                    /*!< Synchronization error raw interrupt status */
#define DCMIPP_PRSR_HSYNC_Pos          (16U)
#define DCMIPP_PRSR_HSYNC_Msk          (0x1UL << DCMIPP_PRSR_HSYNC_Pos)        /*!< 0x00010000 */
#define DCMIPP_PRSR_HSYNC              DCMIPP_PRSR_HSYNC_Msk                   /*!< HSYNC */
#define DCMIPP_PRSR_VSYNC_Pos          (17U)
#define DCMIPP_PRSR_VSYNC_Msk          (0x1UL << DCMIPP_PRSR_VSYNC_Pos)        /*!< 0x00020000 */
#define DCMIPP_PRSR_VSYNC              DCMIPP_PRSR_VSYNC_Msk                   /*!< VSYNC */

/*******************  Bit definition for DCMIPP_PRFCR register  ***************/
#define DCMIPP_PRFCR_CERRF_Pos         (6U)
#define DCMIPP_PRFCR_CERRF_Msk         (0x1UL << DCMIPP_PRFCR_CERRF_Pos)       /*!< 0x00000040 */
#define DCMIPP_PRFCR_CERRF             DCMIPP_PRFCR_CERRF_Msk                  /*!< Synchronization error interrupt status clear */

/*******************  Bit definition for DCMIPP_CMCR register  ****************/
#define DCMIPP_CMCR_CFC_Pos            (4U)
#define DCMIPP_CMCR_CFC_Msk            (0x1UL << DCMIPP_CMCR_CFC_Pos)          /*!< 0x00000010 */
#define DCMIPP_CMCR_CFC                DCMIPP_CMCR_CFC_Msk                     /*!< Clear frame counter */

/*******************  Bit definition for DCMIPP_CMFRCR register  **************/
#define DCMIPP_CMFRCR_FRMCNT_Pos       (0U)
#define DCMIPP_CMFRCR_FRMCNT_Msk       (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_CMFRCR_FRMCNT           DCMIPP_CMFRCR_FRMCNT_Msk                   /*!< FRMCNT[31:0]: frame counter */

/*******************  Bit definition for DCMIPP_CMIER register  ***************/
#define DCMIPP_CMIER_ATXERRIE_Pos      (5U)
#define DCMIPP_CMIER_ATXERRIE_Msk      (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos)    /*!< 0x00000020 */
#define DCMIPP_CMIER_ATXERRIE          DCMIPP_CMIER_ATXERRIE_Msk               /*!< AXI Transfer error interrupt enable for IP_Plug */
#define DCMIPP_CMIER_PRERRIE_Pos       (6U)
#define DCMIPP_CMIER_PRERRIE_Msk       (0x1UL << DCMIPP_CMIER_PRERRIE_Pos)     /*!< 0x00000040 */
#define DCMIPP_CMIER_PRERRIE           DCMIPP_CMIER_PRERRIE_Msk                /*!< limit interrupt enable for the Parallel Interface */
#define DCMIPP_CMIER_P0LINEIE_Pos      (8U)
#define DCMIPP_CMIER_P0LINEIE_Msk      (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos)    /*!< 0x0000100 */
#define DCMIPP_CMIER_P0LINEIE          DCMIPP_CMIER_P0LINEIE_Msk               /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0FRAMEIE_Pos     (9U)
#define DCMIPP_CMIER_P0FRAMEIE_Msk     (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos)   /*!< 0x0000200 */
#define DCMIPP_CMIER_P0FRAMEIE         DCMIPP_CMIER_P0FRAMEIE_Msk              /*!< Frame Capture complete interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0VSYNCIE_Pos     (10U)
#define DCMIPP_CMIER_P0VSYNCIE_Msk     (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos)   /*!< 0x0000400 */
#define DCMIPP_CMIER_P0VSYNCIE         DCMIPP_CMIER_P0VSYNCIE_Msk              /*!< Vertical sync interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0LIMITIE_Pos     (14U)
#define DCMIPP_CMIER_P0LIMITIE_Msk     (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos)   /*!< 0x0004000 */
#define DCMIPP_CMIER_P0LIMITIE         DCMIPP_CMIER_P0LIMITIE_Msk              /*!< limit interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0OVRIE_Pos       (15U)
#define DCMIPP_CMIER_P0OVRIE_Msk       (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos)     /*!< 0x0008000 */
#define DCMIPP_CMIER_P0OVRIE           DCMIPP_CMIER_P0OVRIE_Msk                /*!< Overrun interrupt enable for the Pipe0 */

/*******************  Bit definition for DCMIPP_CMSR1 register  ***************/
#define DCMIPP_CMSR1_PRHSYNC_Pos       (0U)
#define DCMIPP_CMSR1_PRHSYNC_Msk       (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos)     /*!< 0x00000001 */
#define DCMIPP_CMSR1_PRHSYNC           DCMIPP_CMSR1_PRHSYNC_Msk                /*!< state of the HSYNC pin */
#define DCMIPP_CMSR1_PRVSYNC_Pos       (1U)
#define DCMIPP_CMSR1_PRVSYNC_Msk       (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos)     /*!< 0x00000002 */
#define DCMIPP_CMSR1_PRVSYNC           DCMIPP_CMSR1_PRVSYNC_Msk                /*!< state of the VSYNC pin */
#define DCMIPP_CMSR1_P0CPTACT_Pos      (15U)
#define DCMIPP_CMSR1_P0CPTACT_Msk      (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos)    /*!< 0x00008000 */
#define DCMIPP_CMSR1_P0CPTACT          DCMIPP_CMSR1_P0CPTACT_Msk               /*!< active frame capture for the Pipe0 */

/*******************  Bit definition for DCMIPP_CMSR2 register  ***************/
#define DCMIPP_CMSR2_ATXERRF_Pos       (5U)
#define DCMIPP_CMSR2_ATXERRF_Msk       (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos)     /*!< 0x00000020 */
#define DCMIPP_CMSR2_ATXERRF           DCMIPP_CMSR2_ATXERRF_Msk                /*!< AXI transfer error interrupt status flag for the IPPLUG */
#define DCMIPP_CMSR2_PRERRF_Pos        (6U)
#define DCMIPP_CMSR2_PRERRF_Msk        (0x1UL << DCMIPP_CMSR2_PRERRF_Pos)      /*!< 0x00000040 */
#define DCMIPP_CMSR2_PRERRF            DCMIPP_CMSR2_PRERRF_Msk                 /*!< Synchronization error raw interrupt status flag for the Parallel Interface */
#define DCMIPP_CMSR2_P0LINEF_Pos       (8U)
#define DCMIPP_CMSR2_P0LINEF_Msk       (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos)      /*!< 0x00000100 */
#define DCMIPP_CMSR2_P0LINEF           DCMIPP_CMSR2_P0LINEF_Msk                /*!< multi-Line Capture completed raw interrupt status flag for the Pipe0 */
#define DCMIPP_CMSR2_P0FRAMEF_Pos      (9U)
#define DCMIPP_CMSR2_P0FRAMEF_Msk      (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos)    /*!< 0x00000200 */
#define DCMIPP_CMSR2_P0FRAMEF          DCMIPP_CMSR2_P0FRAMEF_Msk               /*!< Frame Capture completed raw interrupt status flag for the Pipe0 */
#define DCMIPP_CMSR2_P0VSYNCF_Pos      (10U)
#define DCMIPP_CMSR2_P0VSYNCF_Msk      (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos)    /*!< 0x00000400 */
#define DCMIPP_CMSR2_P0VSYNCF          DCMIPP_CMSR2_P0VSYNCF_Msk               /*!< VSYNC raw interrupt status flag for the Pipe0 */
#define DCMIPP_CMSR2_P0LIMITF_Pos      (14U)
#define DCMIPP_CMSR2_P0LIMITF_Msk      (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos)    /*!< 0x00004000 */
#define DCMIPP_CMSR2_P0LIMITF          DCMIPP_CMSR2_P0LIMITF_Msk               /*!< Limit raw interrupt status flag for the Pipe0 */
#define DCMIPP_CMSR2_P0OVRF_Pos        (15U)
#define DCMIPP_CMSR2_P0OVRF_Msk        (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos)      /*!< 0x00008000 */
#define DCMIPP_CMSR2_P0OVRF            DCMIPP_CMSR2_P0OVRF_Msk                 /*!< Overrun raw interrupt status flag for the Pipe0 */

/*******************  Bit definition for DCMIPP_CMFCR register  ***************/
#define DCMIPP_CMFCR_CATXERRF_Pos      (5U)
#define DCMIPP_CMFCR_CATXERRF_Msk      (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos)    /*!< 0x00000020 */
#define DCMIPP_CMFCR_CATXERRF          DCMIPP_CMFCR_CATXERRF_Msk               /*!< AXI transfer error interrupt status clear for the IPPLUG */
#define DCMIPP_CMFCR_CPRERRF_Pos       (6U)
#define DCMIPP_CMFCR_CPRERRF_Msk       (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos)     /*!< 0x00000040 */
#define DCMIPP_CMFCR_CPRERRF           DCMIPP_CMFCR_CPRERRF_Msk                /*!< Synchronization error raw interrupt status clear for the Parallel Interface */
#define DCMIPP_CMFCR_CP0LINEF_Pos      (8U)
#define DCMIPP_CMFCR_CP0LINEF_Msk      (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos)    /*!< 0x00000100 */
#define DCMIPP_CMFCR_CP0LINEF          DCMIPP_CMFCR_CP0LINEF_Msk               /*!< multi-Line Capture completed raw interrupt status clear for the Pipe0 */
#define DCMIPP_CMFCR_CP0FRAMEF_Pos     (9U)
#define DCMIPP_CMFCR_CP0FRAMEF_Msk     (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos)   /*!< 0x00000200 */
#define DCMIPP_CMFCR_CP0FRAMEF         DCMIPP_CMFCR_CP0FRAMEF_Msk              /*!< Frame Capture completed raw interrupt status clear for the Pipe0 */
#define DCMIPP_CMFCR_CP0VSYNCF_Pos     (10U)
#define DCMIPP_CMFCR_CP0VSYNCF_Msk     (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos)   /*!< 0x00000400 */
#define DCMIPP_CMFCR_CP0VSYNCF         DCMIPP_CMFCR_CP0VSYNCF_Msk              /*!< VSYNC raw interrupt status clear for the Pipe0 */
#define DCMIPP_CMFCR_CP0LIMITF_Pos     (14U)
#define DCMIPP_CMFCR_CP0LIMITF_Msk     (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos)   /*!< 0x00004000 */
#define DCMIPP_CMFCR_CP0LIMITF         DCMIPP_CMFCR_CP0LIMITF_Msk              /*!< Limit raw interrupt status clear for the Pipe0 */
#define DCMIPP_CMFCR_CP0OVRF_Pos       (15U)
#define DCMIPP_CMFCR_CP0OVRF_Msk       (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos)     /*!< 0x00008000 */
#define DCMIPP_CMFCR_CP0OVRF           DCMIPP_CMFCR_CP0OVRF_Msk                /*!< Overrun raw interrupt status clear for the Pipe0 */

/*******************  Bit definition for DCMIPP_P0FSCR register  **************/
#define DCMIPP_P0FSCR_PIPEN_Pos        (31U)
#define DCMIPP_P0FSCR_PIPEN_Msk        (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos)      /*!< 0x80000000 */
#define DCMIPP_P0FSCR_PIPEN            DCMIPP_P0FSCR_PIPEN_Msk                 /*!< activation of this Pipe */

/*******************  Bit definition for DCMIPP_P0FCTCR register  *************/
#define DCMIPP_P0FCTCR_FRATE_Pos       (0U)
#define DCMIPP_P0FCTCR_FRATE_Msk       (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos)     /*!< 0x00000003 */
#define DCMIPP_P0FCTCR_FRATE           DCMIPP_P0FCTCR_FRATE_Msk                /*!< FRATE[1:0]: Frame capture rate control */
#define DCMIPP_P0FCTCR_CPTMODE_Pos     (2U)
#define DCMIPP_P0FCTCR_CPTMODE_Msk     (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos)   /*!< 0x00000004 */
#define DCMIPP_P0FCTCR_CPTMODE         DCMIPP_P0FCTCR_CPTMODE_Msk              /*!< Capture mode */
#define DCMIPP_P0FCTCR_CPTREQ_Pos      (3U)
#define DCMIPP_P0FCTCR_CPTREQ_Msk      (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos)    /*!< 0x00000008 */
#define DCMIPP_P0FCTCR_CPTREQ          DCMIPP_P0FCTCR_CPTREQ_Msk               /*!< Capture requested */

/*******************  Bit definition for DCMIPP_P0SCSTR register  *************/
#define DCMIPP_P0SCSTR_HSTART_Pos      (0U)
#define DCMIPP_P0SCSTR_HSTART_Msk      (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos)  /*!< 0x00000FFF */
#define DCMIPP_P0SCSTR_HSTART          DCMIPP_P0SCSTR_HSTART_Msk               /*!< HSTART[11:0]: horizontal start */
#define DCMIPP_P0SCSTR_VSTART_Pos      (16U)
#define DCMIPP_P0SCSTR_VSTART_Msk      (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos)  /*!< 0x0FFF0000 */
#define DCMIPP_P0SCSTR_VSTART          DCMIPP_P0SCSTR_VSTART_Msk               /*!< VSTART[11:0]: vertical start */

/*******************  Bit definition for DCMIPP_P0SCSZR register  *************/
#define DCMIPP_P0SCSZR_HSIZE_Pos       (0U)
#define DCMIPP_P0SCSZR_HSIZE_Msk       (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos)   /*!< 0x00000FFF */
#define DCMIPP_P0SCSZR_HSIZE           DCMIPP_P0SCSZR_HSIZE_Msk                /*!< HSTART[11:0]: horizontal size */
#define DCMIPP_P0SCSZR_VSIZE_Pos       (16U)
#define DCMIPP_P0SCSZR_VSIZE_Msk       (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos)   /*!< 0x0FFF0000 */
#define DCMIPP_P0SCSZR_VSIZE           DCMIPP_P0SCSZR_VSIZE_Msk                /*!< VSTART[11:0]: vertical size */
#define DCMIPP_P0SCSZR_POSNEG_Pos      (30U)
#define DCMIPP_P0SCSZR_POSNEG_Msk      (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos)    /*!< 0x40000000 */
#define DCMIPP_P0SCSZR_POSNEG          DCMIPP_P0SCSZR_POSNEG_Msk               /*!< Negative area */
#define DCMIPP_P0SCSZR_ENABLE_Pos      (31U)
#define DCMIPP_P0SCSZR_ENABLE_Msk      (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos)    /*!< 0x80000000 */
#define DCMIPP_P0SCSZR_ENABLE          DCMIPP_P0SCSZR_ENABLE_Msk               /*!< Enable */

/*******************  Bit definition for DCMIPP_P0DCCNTR register  ************/
#define DCMIPP_P0DCCNTR_CNT_Pos        (0U)
#define DCMIPP_P0DCCNTR_CNT_Msk        (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */
#define DCMIPP_P0DCCNTR_CNT            DCMIPP_P0DCCNTR_CNT_Msk                  /*!< CNT[25:0]: number of data dumped during the frame */

/*******************  Bit definition for DCMIPP_P0DCLMTR register  ************/
#define DCMIPP_P0DCLMTR_LIMIT_Pos      (0U)
#define DCMIPP_P0DCLMTR_LIMIT_Msk      (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */
#define DCMIPP_P0DCLMTR_LIMIT          DCMIPP_P0DCLMTR_LIMIT_Msk                 /*!< LIMIT[23:0]: maximum number of data dumped during the frame */
#define DCMIPP_P0DCLMTR_ENABLE_Pos     (31U)
#define DCMIPP_P0DCLMTR_ENABLE_Msk     (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos)   /*!< 0x80000000 */
#define DCMIPP_P0DCLMTR_ENABLE         DCMIPP_P0DCLMTR_ENABLE_Msk              /*!< Enable */

/*******************  Bit definition for DCMIPP_P0PPCR register  **************/
#define DCMIPP_P0PPCR_PAD_Pos          (5U)
#define DCMIPP_P0PPCR_PAD_Msk          (0x1UL << DCMIPP_P0PPCR_PAD_Pos)        /*!< 0x00000020 */
#define DCMIPP_P0PPCR_PAD              DCMIPP_P0PPCR_PAD_Msk                   /*!< PAD mode */
#define DCMIPP_P0PPCR_BSM_Pos          (7U)
#define DCMIPP_P0PPCR_BSM_Msk          (0x3UL << DCMIPP_P0PPCR_BSM_Pos)        /*!< 0x00000180 */
#define DCMIPP_P0PPCR_BSM              DCMIPP_P0PPCR_BSM_Msk                   /*!< Byte Select mode */
#define DCMIPP_P0PPCR_OEBS_Pos         (9U)
#define DCMIPP_P0PPCR_OEBS_Msk         (0x1UL << DCMIPP_P0PPCR_OEBS_Pos)       /*!< 0x00000200 */
#define DCMIPP_P0PPCR_OEBS             DCMIPP_P0PPCR_OEBS_Msk                  /*!< Odd/Even Byte Select */
#define DCMIPP_P0PPCR_LSM_Pos          (10U)
#define DCMIPP_P0PPCR_LSM_Msk          (0x1UL << DCMIPP_P0PPCR_LSM_Pos)        /*!< 0x00000400 */
#define DCMIPP_P0PPCR_LSM              DCMIPP_P0PPCR_LSM_Msk                   /*!< Line Select mode */
#define DCMIPP_P0PPCR_OELS_Pos         (11U)
#define DCMIPP_P0PPCR_OELS_Msk         (0x1UL << DCMIPP_P0PPCR_OELS_Pos)       /*!< 0x00000800 */
#define DCMIPP_P0PPCR_OELS             DCMIPP_P0PPCR_OELS_Msk                  /*!< Odd/Even Line Select */
#define DCMIPP_P0PPCR_LINEMULT_Pos     (13U)
#define DCMIPP_P0PPCR_LINEMULT_Msk     (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< 0x0000E000 */
#define DCMIPP_P0PPCR_LINEMULT         DCMIPP_P0PPCR_LINEMULT_Msk              /*!< LINEMULT[2:0] */
#define DCMIPP_P0PPCR_DBM_Pos          (16U)
#define DCMIPP_P0PPCR_DBM_Msk          (0x1UL << DCMIPP_P0PPCR_DBM_Pos)        /*!< 0x00010000 */
#define DCMIPP_P0PPCR_DBM              DCMIPP_P0PPCR_DBM_Msk                   /*!< Double buffer mode */

/*******************  Bit definition for DCMIPP_P0PPM0AR1 register  ***********/
#define DCMIPP_P0PPM0AR1_MOA_Pos       (0U)
#define DCMIPP_P0PPM0AR1_MOA_Msk       (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_MOA_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0PPM0AR1_MOA           DCMIPP_P0PPM0AR1_MOA_Msk                   /*!< Memory 0 address register 1 */

/*******************  Bit definition for DCMIPP_P0PPM0AR2 register  ***********/
#define DCMIPP_P0PPM0AR2_MOA_Pos       (0U)
#define DCMIPP_P0PPM0AR2_MOA_Msk       (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_MOA_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0PPM0AR2_MOA           DCMIPP_P0PPM0AR2_MOA_Msk                   /*!< Memory 0 address register 2 */

/*******************  Bit definition for DCMIPP_P0IER register  ***************/
#define DCMIPP_P0IER_LINEIE_Pos        (0U)
#define DCMIPP_P0IER_LINEIE_Msk        (0x1UL << DCMIPP_P0IER_LINEIE_Pos)      /*!< 0x00000001 */
#define DCMIPP_P0IER_LINEIE            DCMIPP_P0IER_LINEIE_Msk                 /*!< multi-Line Capture completed interrupt enable */
#define DCMIPP_P0IER_FRAMEIE_Pos       (1U)
#define DCMIPP_P0IER_FRAMEIE_Msk       (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos)     /*!< 0x00000002 */
#define DCMIPP_P0IER_FRAMEIE           DCMIPP_P0IER_FRAMEIE_Msk                /*!< Frame Capture completed interrupt enable */
#define DCMIPP_P0IER_VSYNCIE_Pos       (2U)
#define DCMIPP_P0IER_VSYNCIE_Msk       (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos)     /*!< 0x00000004 */
#define DCMIPP_P0IER_VSYNCIE           DCMIPP_P0IER_VSYNCIE_Msk                /*!< VSYNC interrupt enable */
#define DCMIPP_P0IER_LIMITIE_Pos       (6U)
#define DCMIPP_P0IER_LIMITIE_Msk       (0x1UL << DCMIPP_P0IER_LIMITIE_Pos)     /*!< 0x00000040 */
#define DCMIPP_P0IER_LIMITIE           DCMIPP_P0IER_LIMITIE_Msk                /*!< Limit interrupt enable */
#define DCMIPP_P0IER_OVRIE_Pos         (7U)
#define DCMIPP_P0IER_OVRIE_Msk         (0x1UL << DCMIPP_P0IER_OVRIE_Pos)       /*!< 0x00000080 */
#define DCMIPP_P0IER_OVRIE             DCMIPP_P0IER_OVRIE_Msk                  /*!< Overrun interrupt enable */

/*******************  Bit definition for DCMIPP_P0SR register  ****************/
#define DCMIPP_P0SR_LINEF_Pos          (0U)
#define DCMIPP_P0SR_LINEF_Msk          (0x1UL << DCMIPP_P0SR_LINEF_Pos)        /*!< 0x00000001 */
#define DCMIPP_P0SR_LINEF              DCMIPP_P0SR_LINEF_Msk                   /*!< multi-Line Capture completed interrupt status */
#define DCMIPP_P0SR_FRAMEF_Pos         (1U)
#define DCMIPP_P0SR_FRAMEF_Msk         (0x1UL << DCMIPP_P0SR_FRAMEF_Pos)       /*!< 0x00000002 */
#define DCMIPP_P0SR_FRAMEF             DCMIPP_P0SR_FRAMEF_Msk                  /*!< Frame Capture completed interrupt status */
#define DCMIPP_P0SR_VSYNCF_Pos         (2U)
#define DCMIPP_P0SR_VSYNCF_Msk         (0x1UL << DCMIPP_P0SR_VSYNCF_Pos)       /*!< 0x00000004 */
#define DCMIPP_P0SR_VSYNCF             DCMIPP_P0SR_VSYNCF_Msk                  /*!< VSYNC interrupt status */
#define DCMIPP_P0SR_LIMITF_Pos         (6U)
#define DCMIPP_P0SR_LIMITF_Msk         (0x1UL << DCMIPP_P0SR_LIMITF_Pos)       /*!< 0x00000040 */
#define DCMIPP_P0SR_LIMITF             DCMIPP_P0SR_LIMITF_Msk                  /*!< Limit interrupt status */
#define DCMIPP_P0SR_OVRF_Pos           (7U)
#define DCMIPP_P0SR_OVRF_Msk           (0x1UL << DCMIPP_P0SR_OVRF_Pos)         /*!< 0x00000080 */
#define DCMIPP_P0SR_OVRF               DCMIPP_P0SR_OVRF_Msk                    /*!< Overrun interrupt status */
#define DCMIPP_P0SR_LSTLINE_Pos        (16U)
#define DCMIPP_P0SR_LSTLINE_Msk        (0x1UL << DCMIPP_P0SR_LSTLINE_Pos)      /*!< 0x00010000 */
#define DCMIPP_P0SR_LSTLINE            DCMIPP_P0SR_LSTLINE_Msk                 /*!< Last Line Lsb bit */
#define DCMIPP_P0SR_CPTACT_Pos         (23U)
#define DCMIPP_P0SR_CPTACT_Msk         (0x1UL << DCMIPP_P0SR_CPTACT_Pos)       /*!< 0x00800000 */
#define DCMIPP_P0SR_CPTACT             DCMIPP_P0SR_CPTACT_Msk                  /*!< Capture immediate status */

/*******************  Bit definition for DCMIPP_P0FCR register  ***************/
#define DCMIPP_P0FCR_CLINEF_Pos        (0U)
#define DCMIPP_P0FCR_CLINEF_Msk        (0x1UL << DCMIPP_P0FCR_CLINEF_Pos)      /*!< 0x00000001 */
#define DCMIPP_P0FCR_CLINEF            DCMIPP_P0FCR_CLINEF_Msk                 /*!< multi-Line Capture completed interrupt status clear */
#define DCMIPP_P0FCR_CFRAMEF_Pos       (1U)
#define DCMIPP_P0FCR_CFRAMEF_Msk       (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos)     /*!< 0x00000002 */
#define DCMIPP_P0FCR_CFRAMEF           DCMIPP_P0FCR_CFRAMEF_Msk                /*!< Frame Capture completed interrupt status clear */
#define DCMIPP_P0FCR_CVSYNCF_Pos       (2U)
#define DCMIPP_P0FCR_CVSYNCF_Msk       (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos)     /*!< 0x00000004 */
#define DCMIPP_P0FCR_CVSYNCF           DCMIPP_P0FCR_CVSYNCF_Msk                /*!< VSYNC interrupt status clear */
#define DCMIPP_P0FCR_CLIMITF_Pos       (6U)
#define DCMIPP_P0FCR_CLIMITF_Msk       (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos)     /*!< 0x00000040 */
#define DCMIPP_P0FCR_CLIMITF           DCMIPP_P0FCR_CLIMITF_Msk                /*!< Limit interrupt status clear */
#define DCMIPP_P0FCR_COVRF_Pos         (7U)
#define DCMIPP_P0FCR_COVRF_Msk         (0x1UL << DCMIPP_P0FCR_COVRF_Pos)       /*!< 0x00000080 */
#define DCMIPP_P0FCR_COVRF             DCMIPP_P0FCR_COVRF_Msk                  /*!< Overrun interrupt status clear */

/*******************  Bit definition for DCMIPP_P0CFCTCR register  ************/
#define DCMIPP_P0CFCTCR_FRATE_Pos      (0U)
#define DCMIPP_P0CFCTCR_FRATE_Msk      (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos)    /*!< 0x00000003 */
#define DCMIPP_P0CFCTCR_FRATE          DCMIPP_P0CFCTCR_FRATE_Msk               /*!< FRATE[1:0]: Frame capture rate control */
#define DCMIPP_P0CFCTCR_CPTMODE_Pos    (2U)
#define DCMIPP_P0CFCTCR_CPTMODE_Msk    (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos)  /*!< 0x00000004 */
#define DCMIPP_P0CFCTCR_CPTMODE        DCMIPP_P0CFCTCR_CPTMODE_Msk             /*!< Capture mode */
#define DCMIPP_P0CFCTCR_CPTREQ_Pos     (3U)
#define DCMIPP_P0CFCTCR_CPTREQ_Msk     (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos)   /*!< 0x00000008 */
#define DCMIPP_P0CFCTCR_CPTREQ         DCMIPP_P0CFCTCR_CPTREQ_Msk              /*!< Capture requested */

/*******************  Bit definition for DCMIPP_P0CSCSTR register  ************/
#define DCMIPP_P0CSCSTR_HSTART_Pos     (0U)
#define DCMIPP_P0CSCSTR_HSTART_Msk     (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P0CSCSTR_HSTART         DCMIPP_P0CSCSTR_HSTART_Msk              /*!< HSTART[11:0]: horizontal start */
#define DCMIPP_P0CSCSTR_VSTART_Pos     (16U)
#define DCMIPP_P0CSCSTR_VSTART_Msk     (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P0CSCSTR_VSTART         DCMIPP_P0CSCSTR_VSTART_Msk              /*!< VSTART[11:0]: vertical start */

/*******************  Bit definition for DCMIPP_P0CSCSZR register  ************/
#define DCMIPP_P0CSCSZR_HSIZE_Pos      (0U)
#define DCMIPP_P0CSCSZR_HSIZE_Msk      (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos)  /*!< 0x00000FFF */
#define DCMIPP_P0CSCSZR_HSIZE          DCMIPP_P0CSCSZR_HSIZE_Msk               /*!< HSTART[11:0]: horizontal size */
#define DCMIPP_P0CSCSZR_VSIZE_Pos      (16U)
#define DCMIPP_P0CSCSZR_VSIZE_Msk      (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos)  /*!< 0x0FFF0000 */
#define DCMIPP_P0CSCSZR_VSIZE          DCMIPP_P0CSCSZR_VSIZE_Msk               /*!< VSTART[11:0]: vertical size */
#define DCMIPP_P0CSCSZR_POSNEG_Pos     (30U)
#define DCMIPP_P0CSCSZR_POSNEG_Msk     (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos)   /*!< 0x40000000 */
#define DCMIPP_P0CSCSZR_POSNEG         DCMIPP_P0CSCSZR_POSNEG_Msk              /*!< Negative area */
#define DCMIPP_P0CSCSZR_ENABLE_Pos     (31U)
#define DCMIPP_P0CSCSZR_ENABLE_Msk     (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos)   /*!< 0x80000000 */
#define DCMIPP_P0CSCSZR_ENABLE         DCMIPP_P0CSCSZR_ENABLE_Msk              /*!< Enable */

/*******************  Bit definition for DCMIPP_P0CPPCR register  *************/
#define DCMIPP_P0CPPCR_PAD_Pos         (5U)
#define DCMIPP_P0CPPCR_PAD_Msk         (0x1UL << DCMIPP_P0CPPCR_PAD_Pos)       /*!< 0x00000020 */
#define DCMIPP_P0CPPCR_PAD             DCMIPP_P0CPPCR_PAD_Msk                  /*!< PAD mode */
#define DCMIPP_P0CPPCR_BSM_Pos         (7U)
#define DCMIPP_P0CPPCR_BSM_Msk         (0x3UL << DCMIPP_P0CPPCR_BSM_Pos)       /*!< 0x00000180 */
#define DCMIPP_P0CPPCR_BSM             DCMIPP_P0CPPCR_BSM_Msk                  /*!< Byte Select mode */
#define DCMIPP_P0CPPCR_OEBS_Pos        (9U)
#define DCMIPP_P0CPPCR_OEBS_Msk        (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos)      /*!< 0x00000200 */
#define DCMIPP_P0CPPCR_OEBS            DCMIPP_P0CPPCR_OEBS_Msk                 /*!< Odd/Even Byte Select */
#define DCMIPP_P0CPPCR_LSM_Pos         (10U)
#define DCMIPP_P0CPPCR_LSM_Msk         (0x1UL << DCMIPP_P0CPPCR_LSM_Pos)       /*!< 0x00000400 */
#define DCMIPP_P0CPPCR_LSM             DCMIPP_P0CPPCR_LSM_Msk                  /*!< Line Select mode */
#define DCMIPP_P0CPPCR_OELS_Pos        (11U)
#define DCMIPP_P0CPPCR_OELS_Msk        (0x1UL << DCMIPP_P0CPPCR_OELS_Pos)      /*!< 0x00000800 */
#define DCMIPP_P0CPPCR_OELS            DCMIPP_P0CPPCR_OELS_Msk                 /*!< Odd/Even Line Select */
#define DCMIPP_P0CPPCR_LINEMULT_Pos    (13U)
#define DCMIPP_P0CPPCR_LINEMULT_Msk    (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos)  /*!< 0x0000E000 */
#define DCMIPP_P0CPPCR_LINEMULT        DCMIPP_P0CPPCR_LINEMULT_Msk             /*!< LINEMULT[2:0] */
#define DCMIPP_P0CPPCR_DBM_Pos         (16U)
#define DCMIPP_P0CPPCR_DBM_Msk         (0x1UL << DCMIPP_P0CPPCR_DBM_Pos)       /*!< 0x00010000 */
#define DCMIPP_P0CPPCR_DBM             DCMIPP_P0CPPCR_DBM_Msk                  /*!< Double buffer mode */

/*******************  Bit definition for DCMIPP_P0CPPM0AR1 register  **********/
#define DCMIPP_P0CPPM0AR1_MOA_Pos     (0U)
#define DCMIPP_P0CPPM0AR1_MOA_Msk     (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_MOA_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0CPPM0AR1_MOA         DCMIPP_P0CPPM0AR1_MOA_Msk                   /*!< Memory 0 address register 1 */

/*******************  Bit definition for DCMIPP_P0CPPM0AR2 register  **********/
#define DCMIPP_P0CPPM0AR2_MOA_Pos     (0U)
#define DCMIPP_P0CPPM0AR2_MOA_Msk     (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR2_MOA_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0CPPM0AR2_MOA         DCMIPP_P0CPPM0AR2_MOA_Msk                   /*!< Memory 0 address register 2 */


/******************************************************************************/
/*                                                                            */
/*                        Delay Block Interface (DLYB)                        */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for DLYB_CR register  ********************/
#define DLYB_CR_DEN_Pos                     (0U)
#define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
#define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
#define DLYB_CR_SEN_Pos                     (1U)
#define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
#define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */

/*******************  Bit definition for DLYB_CFGR register  ********************/
#define DLYB_CFGR_SEL_Pos                   (0U)
#define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
#define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
#define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
#define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
#define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
#define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */

#define DLYB_CFGR_UNIT_Pos                  (8U)
#define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
#define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
#define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
#define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
#define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
#define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
#define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
#define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
#define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */

#define DLYB_CFGR_LNG_Pos                   (16U)
#define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
#define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
#define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
#define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
#define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
#define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
#define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
#define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
#define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
#define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
#define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
#define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
#define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
#define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */

#define DLYB_CFGR_LNGF_Pos                  (31U)
#define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
#define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */


/******************************************************************************/
/*                                                                            */
/*                           DMA Controller (DMA)                             */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for DMA_PRIVCFGR register  ****************/
#define DMA_PRIVCFGR_PRIV0_Pos              (0U)
#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0 */
#define DMA_PRIVCFGR_PRIV1_Pos              (1U)
#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1 */
#define DMA_PRIVCFGR_PRIV2_Pos              (2U)
#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2 */
#define DMA_PRIVCFGR_PRIV3_Pos              (3U)
#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3 */
#define DMA_PRIVCFGR_PRIV4_Pos              (4U)
#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4 */
#define DMA_PRIVCFGR_PRIV5_Pos              (5U)
#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5 */
#define DMA_PRIVCFGR_PRIV6_Pos              (6U)
#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6 */
#define DMA_PRIVCFGR_PRIV7_Pos              (7U)
#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7 */
#define DMA_PRIVCFGR_PRIV8_Pos              (8U)
#define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
#define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8 */
#define DMA_PRIVCFGR_PRIV9_Pos              (9U)
#define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
#define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9 */
#define DMA_PRIVCFGR_PRIV10_Pos             (10U)
#define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
#define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
#define DMA_PRIVCFGR_PRIV11_Pos             (11U)
#define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
#define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
#define DMA_PRIVCFGR_PRIV12_Pos             (12U)
#define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
#define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
#define DMA_PRIVCFGR_PRIV13_Pos             (13U)
#define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
#define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
#define DMA_PRIVCFGR_PRIV14_Pos             (14U)
#define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
#define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
#define DMA_PRIVCFGR_PRIV15_Pos             (15U)
#define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
#define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */

/*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
#define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
#define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
#define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
#define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
#define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
#define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
#define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
#define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
#define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
#define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
#define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
#define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
#define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
#define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
#define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
#define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
#define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
#define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
#define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
#define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
#define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
#define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
#define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
#define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
#define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
#define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
#define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
#define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
#define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
#define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
#define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
#define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */

/*******************  Bit definition for DMA_MISR register  ****************/
#define DMA_MISR_MIS0_Pos                   (0U)
#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Channel 0 */
#define DMA_MISR_MIS1_Pos                   (1U)
#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Channel 1 */
#define DMA_MISR_MIS2_Pos                   (2U)
#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Channel 2 */
#define DMA_MISR_MIS3_Pos                   (3U)
#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Channel 3 */
#define DMA_MISR_MIS4_Pos                   (4U)
#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Channel 4 */
#define DMA_MISR_MIS5_Pos                   (5U)
#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Channel 5 */
#define DMA_MISR_MIS6_Pos                   (6U)
#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Channel 6 */
#define DMA_MISR_MIS7_Pos                   (7U)
#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Channel 7 */
#define DMA_MISR_MIS8_Pos                   (8U)
#define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
#define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Channel 8 */
#define DMA_MISR_MIS9_Pos                   (9U)
#define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
#define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Channel 9 */
#define DMA_MISR_MIS10_Pos                  (10U)
#define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
#define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Channel 10 */
#define DMA_MISR_MIS11_Pos                  (11U)
#define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
#define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Channel 11 */
#define DMA_MISR_MIS12_Pos                  (12U)
#define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
#define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Channel 12 */
#define DMA_MISR_MIS13_Pos                  (13U)
#define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
#define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Channel 13 */
#define DMA_MISR_MIS14_Pos                  (14U)
#define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
#define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Channel 14 */
#define DMA_MISR_MIS15_Pos                  (15U)
#define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
#define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Channel 15 */

/*******************  Bit definition for DMA_CLBAR register  ****************/
#define DMA_CLBAR_LBA_Pos                   (16U)
#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */

/*******************  Bit definition for DMA_CFCR register  *******************/
#define DMA_CFCR_TCF_Pos                    (8U)
#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear */
#define DMA_CFCR_HTF_Pos                    (9U)
#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear */
#define DMA_CFCR_DTEF_Pos                   (10U)
#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear */
#define DMA_CFCR_ULEF_Pos                   (11U)
#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
#define DMA_CFCR_USEF_Pos                   (12U)
#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear */
#define DMA_CFCR_SUSPF_Pos                  (13U)
#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear */
#define DMA_CFCR_TOF_Pos                    (14U)
#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun clear flag */

/*******************  Bit definition for DMA_CSR register  *******************/
#define DMA_CSR_IDLEF_Pos                   (0U)
#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
#define DMA_CSR_TCF_Pos                     (8U)
#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
#define DMA_CSR_HTF_Pos                     (9U)
#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
#define DMA_CSR_DTEF_Pos                    (10U)
#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
#define DMA_CSR_ULEF_Pos                    (11U)
#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
#define DMA_CSR_USEF_Pos                    (12U)
#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
#define DMA_CSR_SUSPF_Pos                   (13U)
#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag */
#define DMA_CSR_TOF_Pos                     (14U)
#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */
#define DMA_CSR_FIFOL_Pos                   (16U)
#define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
#define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes */

/*******************  Bit definition for DMA_CCR register  ********************/
#define DMA_CCR_EN_Pos                      (0U)
#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
#define DMA_CCR_RESET_Pos                   (1U)
#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset */
#define DMA_CCR_SUSP_Pos                    (2U)
#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
#define DMA_CCR_TCIE_Pos                    (8U)
#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos                    (9U)
#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable */
#define DMA_CCR_DTEIE_Pos                   (10U)
#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable */
#define DMA_CCR_ULEIE_Pos                   (11U)
#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
#define DMA_CCR_USEIE_Pos                   (12U)
#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable */
#define DMA_CCR_SUSPIE_Pos                  (13U)
#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable */
#define DMA_CCR_TOIE_Pos                    (14U)
#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable */
#define DMA_CCR_LSM_Pos                     (16U)
#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
#define DMA_CCR_LAP_Pos                     (17U)
#define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
#define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port */
#define DMA_CCR_PRIO_Pos                    (22U)
#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level */
#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */

/*******************  Bit definition for DMA_CTR1 register  *******************/
#define DMA_CTR1_SDW_LOG2_Pos               (0U)
#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst */
#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
#define DMA_CTR1_SINC_Pos                   (3U)
#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
#define DMA_CTR1_SBL_1_Pos                  (4U)
#define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
#define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1 */
#define DMA_CTR1_PAM_Pos                    (11U)
#define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
#define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
#define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
#define DMA_CTR1_SBX_Pos                    (13U)
#define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
#define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
#define DMA_CTR1_SAP_Pos                    (14U)
#define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
#define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port */
#define DMA_CTR1_DDW_LOG2_Pos               (16U)
#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst */
#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
#define DMA_CTR1_DINC_Pos                   (19U)
#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst */
#define DMA_CTR1_DBL_1_Pos                  (20U)
#define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
#define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1 */
#define DMA_CTR1_DBX_Pos                    (26U)
#define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
#define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange */
#define DMA_CTR1_DHX_Pos                    (27U)
#define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
#define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange */
#define DMA_CTR1_DWX_Pos                    (28U)
#define DMA_CTR1_DWX_Msk                    (0x1UL << DMA_CTR1_DWX_Pos)             /*!< 0x10000000 */
#define DMA_CTR1_DWX                        DMA_CTR1_DWX_Msk                        /*!< Destination word-word exchange */
#define DMA_CTR1_DAP_Pos                    (30U)
#define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
#define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port */

/******************  Bit definition for DMA_CTR2 register  *******************/
#define DMA_CTR2_REQSEL_Pos                 (0U)
#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
#define DMA_CTR2_SWREQ_Pos                  (9U)
#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
#define DMA_CTR2_DREQ_Pos                   (10U)
#define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
#define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request */
#define DMA_CTR2_BREQ_Pos                   (11U)
#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
#define DMA_CTR2_PFREQ_Pos                  (12U)
#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
#define DMA_CTR2_TRIGM_Pos                  (14U)
#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
#define DMA_CTR2_TRIGSEL_Pos                (16U)
#define DMA_CTR2_TRIGSEL_Msk                (0x3FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x003F0000 */
#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection */
#define DMA_CTR2_TRIGPOL_Pos                (24U)
#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity */
#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
#define DMA_CTR2_TCEM_Pos                   (30U)
#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode */
#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */

/******************  Bit definition for DMA_CBR1 register  *******************/
#define DMA_CBR1_BNDT_Pos                   (0U)
#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
#define DMA_CBR1_BRC_Pos                    (16U)
#define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
#define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter */
#define DMA_CBR1_SDEC_Pos                   (28U)
#define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
#define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement */
#define DMA_CBR1_DDEC_Pos                   (29U)
#define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
#define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement */
#define DMA_CBR1_BRSDEC_Pos                 (30U)
#define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
#define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement */
#define DMA_CBR1_BRDDEC_Pos                 (31U)
#define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
#define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement */

/******************  Bit definition for DMA_CSAR register  ********************/
#define DMA_CSAR_SA_Pos                     (0U)
#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */

/******************  Bit definition for DMA_CDAR register  *******************/
#define DMA_CDAR_DA_Pos                     (0U)
#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */

/******************  Bit definition for DMA_CTR3 register  *******************/
#define DMA_CTR3_SAO_Pos                    (0U)
#define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
#define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment */
#define DMA_CTR3_DAO_Pos                    (16U)
#define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
#define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */

/******************  Bit definition for DMA_CBR2 register  *******************/
#define DMA_CBR2_BRSAO_Pos                  (0U)
#define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
#define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset */
#define DMA_CBR2_BRDAO_Pos                  (16U)
#define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
#define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */

/******************  Bit definition for DMA_CLLR register  *******************/
#define DMA_CLLR_LA_Pos                     (2U)
#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
#define DMA_CLLR_ULL_Pos                    (16U)
#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory */
#define DMA_CLLR_UB2_Pos                    (25U)
#define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
#define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory */
#define DMA_CLLR_UT3_Pos                    (26U)
#define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
#define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM */
#define DMA_CLLR_UDA_Pos                    (27U)
#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM */
#define DMA_CLLR_USA_Pos                    (28U)
#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM */
#define DMA_CLLR_UB1_Pos                    (29U)
#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM */
#define DMA_CLLR_UT2_Pos                    (30U)
#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM */
#define DMA_CLLR_UT1_Pos                    (31U)
#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM */


/******************************************************************************/
/*                                                                            */
/*                          DMA2D Controller (DMA2D)                          */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for DMA2D_CR register  ******************/
#define DMA2D_CR_START_Pos         (0U)
#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
#define DMA2D_CR_SUSP_Pos          (1U)
#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
#define DMA2D_CR_ABORT_Pos         (2U)
#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
#define DMA2D_CR_LOM_Pos           (6U)
#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode */
#define DMA2D_CR_TEIE_Pos          (8U)
#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
#define DMA2D_CR_TCIE_Pos          (9U)
#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
#define DMA2D_CR_TWIE_Pos          (10U)
#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
#define DMA2D_CR_CAEIE_Pos         (11U)
#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
#define DMA2D_CR_CTCIE_Pos         (12U)
#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
#define DMA2D_CR_CEIE_Pos          (13U)
#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
#define DMA2D_CR_MODE_Pos          (16U)
#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0] */
#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                /*!< 0x00010000 */
#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                /*!< 0x00020000 */
#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                /*!< 0x00040000 */

/********************  Bit definition for DMA2D_ISR register  *****************/
#define DMA2D_ISR_TEIF_Pos         (0U)
#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
#define DMA2D_ISR_TCIF_Pos         (1U)
#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
#define DMA2D_ISR_TWIF_Pos         (2U)
#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_ISR_CAEIF_Pos        (3U)
#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_ISR_CTCIF_Pos        (4U)
#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_ISR_CEIF_Pos         (5U)
#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */

/********************  Bit definition for DMA2D_IFCR register  ****************/
#define DMA2D_IFCR_CTEIF_Pos       (0U)
#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFCR_CTCIF_Pos       (1U)
#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CTWIF_Pos       (2U)
#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFCR_CAECIF_Pos      (3U)
#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFCR_CCTCIF_Pos      (4U)
#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CCEIF_Pos       (5U)
#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */

/********************  Bit definition for DMA2D_FGMAR register  ***************/
#define DMA2D_FGMAR_MA_Pos         (0U)
#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */

/********************  Bit definition for DMA2D_FGOR register  ****************/
#define DMA2D_FGOR_LO_Pos          (0U)
#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

/********************  Bit definition for DMA2D_BGMAR register  ***************/
#define DMA2D_BGMAR_MA_Pos         (0U)
#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */

/********************  Bit definition for DMA2D_BGOR register  ****************/
#define DMA2D_BGOR_LO_Pos          (0U)
#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

/********************  Bit definition for DMA2D_FGPFCCR register  *************/
#define DMA2D_FGPFCCR_CM_Pos       (0U)
#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000001 */
#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000002 */
#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000004 */
#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000008 */
#define DMA2D_FGPFCCR_CCM_Pos      (4U)
#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
#define DMA2D_FGPFCCR_START_Pos    (5U)
#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
#define DMA2D_FGPFCCR_CS_Pos       (8U)
#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
#define DMA2D_FGPFCCR_AM_Pos       (16U)
#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00010000 */
#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00020000 */
#define DMA2D_FGPFCCR_CSS_Pos      (18U)
#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /*!< Chroma Sub-Sampling */
#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00040000 */
#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00080000 */
#define DMA2D_FGPFCCR_AI_Pos       (20U)
#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
#define DMA2D_FGPFCCR_RBS_Pos      (21U)
#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

/********************  Bit definition for DMA2D_FGCOLR register  **************/
#define DMA2D_FGCOLR_BLUE_Pos      (0U)
#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
#define DMA2D_FGCOLR_GREEN_Pos     (8U)
#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
#define DMA2D_FGCOLR_RED_Pos       (16U)
#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */

/********************  Bit definition for DMA2D_BGPFCCR register  *************/
#define DMA2D_BGPFCCR_CM_Pos       (0U)
#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000001 */
#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000002 */
#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000004 */
#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000008 */
#define DMA2D_BGPFCCR_CCM_Pos      (4U)
#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
#define DMA2D_BGPFCCR_START_Pos    (5U)
#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
#define DMA2D_BGPFCCR_CS_Pos       (8U)
#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
#define DMA2D_BGPFCCR_AM_Pos       (16U)
#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00010000 */
#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00020000 */
#define DMA2D_BGPFCCR_AI_Pos       (20U)
#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
#define DMA2D_BGPFCCR_RBS_Pos      (21U)
#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */

/********************  Bit definition for DMA2D_BGCOLR register  **************/
#define DMA2D_BGCOLR_BLUE_Pos      (0U)
#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
#define DMA2D_BGCOLR_GREEN_Pos     (8U)
#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
#define DMA2D_BGCOLR_RED_Pos       (16U)
#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */

/********************  Bit definition for DMA2D_FGCMAR register  **************/
#define DMA2D_FGCMAR_MA_Pos        (0U)
#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */

/********************  Bit definition for DMA2D_BGCMAR register  **************/
#define DMA2D_BGCMAR_MA_Pos        (0U)
#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */

/********************  Bit definition for DMA2D_OPFCCR register  **************/
#define DMA2D_OPFCCR_CM_Pos        (0U)
#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
#define DMA2D_OPFCCR_SB_Pos        (8U)
#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
#define DMA2D_OPFCCR_AI_Pos        (20U)
#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
#define DMA2D_OPFCCR_RBS_Pos       (21U)
#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */

/********************  Bit definition for DMA2D_OCOLR register  ***************/
/*!<Mode_ARGB8888/RGB888 */
#define DMA2D_OCOLR_BLUE_1         (0x000000FFUL)                              /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_1        (0x0000FF00UL)                              /*!< Green Value  */
#define DMA2D_OCOLR_RED_1          (0x00FF0000UL)                              /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_1        (0xFF000000UL)                              /*!< Alpha Channel Value */

/*!<Mode_RGB565 */
#define DMA2D_OCOLR_BLUE_2         (0x0000001FUL)                              /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_2        (0x000007E0UL)                              /*!< Green Value  */
#define DMA2D_OCOLR_RED_2          (0x0000F800UL)                              /*!< Red Value */

/*!<Mode_ARGB1555 */
#define DMA2D_OCOLR_BLUE_3         (0x0000001FUL)                              /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_3        (0x000003E0UL)                              /*!< Green Value  */
#define DMA2D_OCOLR_RED_3          (0x00007C00UL)                              /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_3        (0x00008000UL)                              /*!< Alpha Channel Value */

/*!<Mode_ARGB4444 */
#define DMA2D_OCOLR_BLUE_4         (0x0000000FUL)                              /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_4        (0x000000F0UL)                              /*!< Green Value  */
#define DMA2D_OCOLR_RED_4          (0x00000F00UL)                              /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_4        (0x0000F000UL)                              /*!< Alpha Channel Value */

/********************  Bit definition for DMA2D_OMAR register  ****************/
#define DMA2D_OMAR_MA_Pos          (0U)
#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */

/********************  Bit definition for DMA2D_OOR register  *****************/
#define DMA2D_OOR_LO_Pos           (0U)
#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */

/********************  Bit definition for DMA2D_NLR register  *****************/
#define DMA2D_NLR_NL_Pos           (0U)
#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
#define DMA2D_NLR_PL_Pos           (16U)
#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

/********************  Bit definition for DMA2D_LWR register  *****************/
#define DMA2D_LWR_LW_Pos           (0U)
#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

/********************  Bit definition for DMA2D_AMTCR register  ***************/
#define DMA2D_AMTCR_EN_Pos         (0U)
#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
#define DMA2D_AMTCR_DT_Pos         (8U)
#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

/********************  Bit definition for DMA2D_FGCLUT register  **************/

/********************  Bit definition for DMA2D_BGCLUT register  **************/


/******************************************************************************/
/*                                                                            */
/*                    Digital Temperature Sensor (DTS)                        */
/*                                                                            */
/******************************************************************************/

/******************  Bit definition for DTS_CFGR1 register  *******************/
#define DTS_CFGR1_TS1_EN_Pos               (0U)
#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */
#define DTS_CFGR1_TS1_START_Pos            (4U)
#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */
#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)
#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)
#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */
#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)
#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */
#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)
#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */
#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)
#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

/******************  Bit definition for DTS_T0VALR1 register  *****************/
#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)
#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */
#define DTS_T0VALR1_TS1_T0_Pos             (16U)
#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

/******************  Bit definition for DTS_RAMPVALR register  ****************/
#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)
#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

/******************  Bit definition for DTS_ITR1 register      ****************/
#define DTS_ITR1_TS1_LITTHD_Pos            (0U)
#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */
#define DTS_ITR1_TS1_HITTHD_Pos            (16U)
#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

/******************  Bit definition for DTS_DR register        ****************/
#define DTS_DR_TS1_MFREQ_Pos               (0U)
#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

/******************  Bit definition for DTS_SR register        ****************/
#define DTS_SR_TS1_ITEF_Pos                (0U)
#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */
#define DTS_SR_TS1_ITLF_Pos                (1U)
#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */
#define DTS_SR_TS1_ITHF_Pos                (2U)
#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */
#define DTS_SR_TS1_AITEF_Pos               (4U)
#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */
#define DTS_SR_TS1_AITLF_Pos               (5U)
#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */
#define DTS_SR_TS1_AITHF_Pos               (6U)
#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */
#define DTS_SR_TS1_RDY_Pos                 (15U)
#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

/******************  Bit definition for DTS_ITENR register      ***************/
#define DTS_ITENR_TS1_ITEEN_Pos            (0U)
#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */
#define DTS_ITENR_TS1_ITLEN_Pos            (1U)
#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */
#define DTS_ITENR_TS1_ITHEN_Pos            (2U)
#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */
#define DTS_ITENR_TS1_AITEEN_Pos           (4U)
#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */
#define DTS_ITENR_TS1_AITLEN_Pos           (5U)
#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */
#define DTS_ITENR_TS1_AITHEN_Pos           (6U)
#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

/******************  Bit definition for DTS_ICIFR register      ***************/
#define DTS_ICIFR_TS1_CITEF_Pos            (0U)
#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */
#define DTS_ICIFR_TS1_CITLF_Pos            (1U)
#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */
#define DTS_ICIFR_TS1_CITHF_Pos            (2U)
#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */
#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)
#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)
#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */
#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)
#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */


/******************************************************************************/
/*                                                                            */
/*                Ethernet MAC Registers bits definitions                     */
/*                                                                            */
/******************************************************************************/
/* Bit definition for Ethernet MAC Configuration Register register */
#define ETH_MACCR_ARP_Pos                             (31U)
#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
#define ETH_MACCR_SARC_Pos                            (28U)
#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
#define ETH_MACCR_IPC_Pos                             (27U)
#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
#define ETH_MACCR_IPG_Pos                             (24U)
#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
#define ETH_MACCR_GPSLCE_Pos                          (23U)
#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
#define ETH_MACCR_S2KP_Pos                            (22U)
#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
#define ETH_MACCR_CST_Pos                             (21U)
#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
#define ETH_MACCR_ACS_Pos                             (20U)
#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
#define ETH_MACCR_WD_Pos                              (19U)
#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
#define ETH_MACCR_JD_Pos                              (17U)
#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
#define ETH_MACCR_JE_Pos                              (16U)
#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
#define ETH_MACCR_FES_Pos                             (14U)
#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
#define ETH_MACCR_DM_Pos                              (13U)
#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
#define ETH_MACCR_LM_Pos                              (12U)
#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
#define ETH_MACCR_ECRSFD_Pos                          (11U)
#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
#define ETH_MACCR_DO_Pos                              (10U)
#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
#define ETH_MACCR_DCRS_Pos                            (9U)
#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
#define ETH_MACCR_DR_Pos                              (8U)
#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
#define ETH_MACCR_BL_Pos                              (5U)
#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_DC_Pos                              (4U)
#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
#define ETH_MACCR_PRELEN_Pos                          (2U)
#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
#define ETH_MACCR_TE_Pos                              (1U)
#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
#define ETH_MACCR_RE_Pos                              (0U)
#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

/* Bit definition for Ethernet MAC Extended Configuration Register register */
#define ETH_MACECR_EIPG_Pos                           (25U)
#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
#define ETH_MACECR_EIPGEN_Pos                         (24U)
#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
#define ETH_MACECR_USP_Pos                            (18U)
#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
#define ETH_MACECR_SPEN_Pos                           (17U)
#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
#define ETH_MACECR_DCRCC_Pos                          (16U)
#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
#define ETH_MACECR_GPSL_Pos                           (0U)
#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

/* Bit definition for Ethernet MAC Packet Filter Register */
#define ETH_MACPFR_RA_Pos                             (31U)
#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
#define ETH_MACPFR_DNTU_Pos                           (21U)
#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
#define ETH_MACPFR_IPFE_Pos                           (20U)
#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
#define ETH_MACPFR_VTFE_Pos                           (16U)
#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
#define ETH_MACPFR_HPF_Pos                            (10U)
#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
#define ETH_MACPFR_SAF_Pos                            (9U)
#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
#define ETH_MACPFR_SAIF_Pos                           (8U)
#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
#define ETH_MACPFR_PCF_Pos                            (6U)
#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACPFR_DBF_Pos                            (5U)
#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
#define ETH_MACPFR_PM_Pos                             (4U)
#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
#define ETH_MACPFR_DAIF_Pos                           (3U)
#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
#define ETH_MACPFR_HMC_Pos                            (2U)
#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
#define ETH_MACPFR_HUC_Pos                            (1U)
#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
#define ETH_MACPFR_PR_Pos                             (0U)
#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

/* Bit definition for Ethernet MAC Watchdog Timeout Register */
#define ETH_MACWTR_PWE_Pos                            (8U)
#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
#define ETH_MACWTR_WTO_Pos                            (0U)
#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTHR_HTH_Pos                           (0U)
#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTLR_HTL_Pos                           (0U)
#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
#define ETH_MACVTR_EIVLS_Pos                          (28U)
#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
#define ETH_MACVTR_ERIVLT_Pos                         (27U)
#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
#define ETH_MACVTR_EDVLP_Pos                          (26U)
#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
#define ETH_MACVTR_VTHM_Pos                           (25U)
#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
#define ETH_MACVTR_EVLRXS_Pos                         (24U)
#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
#define ETH_MACVTR_EVLS_Pos                           (21U)
#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
#define ETH_MACVTR_DOVLTC_Pos                         (20U)
#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
#define ETH_MACVTR_ERSVLM_Pos                         (19U)
#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
#define ETH_MACVTR_ESVL_Pos                           (18U)
#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
#define ETH_MACVTR_VTIM_Pos                           (17U)
#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
#define ETH_MACVTR_ETV_Pos                            (16U)
#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
#define ETH_MACVTR_VL_Pos                             (0U)
#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
#define ETH_MACVTR_VL_UP_Pos                          (13U)
#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACVTR_VL_VID_Pos                         (0U)
#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

/* Bit definition for Ethernet MAC VLAN Hash Table Register */
#define ETH_MACVHTR_VLHT_Pos                          (0U)
#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

/* Bit definition for Ethernet MAC VLAN Incl Register */
#define ETH_MACVIR_VLTI_Pos                           (20U)
#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
#define ETH_MACVIR_CSVL_Pos                           (19U)
#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
#define ETH_MACVIR_VLP_Pos                            (18U)
#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
#define ETH_MACVIR_VLC_Pos                            (16U)
#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define ETH_MACVIR_VLT_Pos                            (0U)
#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
#define ETH_MACVIR_VLT_UP_Pos                         (13U)
#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACVIR_VLT_VID_Pos                        (0U)
#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
#define ETH_MACIVIR_VLTI_Pos                          (20U)
#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
#define ETH_MACIVIR_CSVL_Pos                          (19U)
#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
#define ETH_MACIVIR_VLP_Pos                           (18U)
#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
#define ETH_MACIVIR_VLC_Pos                           (16U)
#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define ETH_MACIVIR_VLT_Pos                           (0U)
#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
#define ETH_MACTFCR_PT_Pos                            (16U)
#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
#define ETH_MACTFCR_DZPQ_Pos                          (7U)
#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
#define ETH_MACTFCR_PLT_Pos                           (4U)
#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
#define ETH_MACTFCR_TFE_Pos                           (1U)
#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
#define ETH_MACTFCR_FCB_Pos                           (0U)
#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
#define ETH_MACRFCR_UP_Pos                            (1U)
#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
#define ETH_MACRFCR_RFE_Pos                           (0U)
#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

/* Bit definition for Ethernet MAC Interrupt Status Register */
#define ETH_MACISR_RXSTSIS_Pos                        (14U)
#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
#define ETH_MACISR_TXSTSIS_Pos                        (13U)
#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
#define ETH_MACISR_TSIS_Pos                           (12U)
#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
#define ETH_MACISR_MMCTXIS_Pos                        (10U)
#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
#define ETH_MACISR_MMCRXIS_Pos                        (9U)
#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
#define ETH_MACISR_MMCIS_Pos                          (8U)
#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
#define ETH_MACISR_LPIIS_Pos                          (5U)
#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
#define ETH_MACISR_PMTIS_Pos                          (4U)
#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
#define ETH_MACISR_PHYIS_Pos                          (3U)
#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

/* Bit definition for Ethernet MAC Interrupt Enable Register */
#define ETH_MACIER_RXSTSIE_Pos                        (14U)
#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
#define ETH_MACIER_TXSTSIE_Pos                        (13U)
#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
#define ETH_MACIER_TSIE_Pos                           (12U)
#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
#define ETH_MACIER_LPIIE_Pos                          (5U)
#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
#define ETH_MACIER_PMTIE_Pos                          (4U)
#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
#define ETH_MACIER_PHYIE_Pos                          (3U)
#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

/* Bit definition for Ethernet MAC Rx Tx Status Register */
#define ETH_MACRXTXSR_RWT_Pos                         (8U)
#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
#define ETH_MACRXTXSR_TJT_Pos                         (0U)
#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

/* Bit definition for Ethernet MAC PMT Control Status Register */
#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
#define ETH_MACRWUPFR_D_Pos                           (0U)
#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

/* Bit definition for Ethernet MAC LPI Control Status Register */
#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
#define ETH_MACLCSR_LPITE_Pos                         (20U)
#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
#define ETH_MACLCSR_LPITXA_Pos                        (19U)
#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
#define ETH_MACLCSR_PLS_Pos                           (17U)
#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
#define ETH_MACLCSR_LPIEN_Pos                         (16U)
#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
#define ETH_MACLCSR_RLPIST_Pos                        (9U)
#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
#define ETH_MACLCSR_TLPIST_Pos                        (8U)
#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

/* Bit definition for Ethernet MAC LPI Timers Control Register */
#define ETH_MACLTCR_LST_Pos                           (16U)
#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
#define ETH_MACLTCR_TWT_Pos                           (0U)
#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

/* Bit definition for Ethernet MAC LPI Entry Timer Register */
#define ETH_MACLETR_LPIET_Pos                         (0U)
#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

/* Bit definition for Ethernet MAC 1US Tic Counter Register */
#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

/* Bit definition for Ethernet MAC Version Register */
#define ETH_MACVR_USERVER_Pos                         (8U)
#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
#define ETH_MACVR_SNPSVER_Pos                         (0U)
#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

/* Bit definition for Ethernet MAC Debug Register */
#define ETH_MACDR_TFCSTS_Pos                          (17U)
#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
#define ETH_MACDR_TPESTS_Pos                          (16U)
#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
#define ETH_MACDR_RPESTS_Pos                          (0U)
#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

/* Bit definition for Ethernet MAC HW Feature0 Register */
#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

/* Bit definition for Ethernet MAC HW Feature1 Register */
#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

/* Bit definition for Ethernet MAC HW Feature2 Register */
#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

/* Bit definition for Ethernet MAC MDIO Address Register */
#define ETH_MACMDIOAR_PSE_Pos                         (27U)
#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
#define ETH_MACMDIOAR_BTB_Pos                         (26U)
#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
#define ETH_MACMDIOAR_PA_Pos                          (21U)
#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
#define ETH_MACMDIOAR_RDA_Pos                         (16U)
#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
#define ETH_MACMDIOAR_NTC_Pos                         (12U)
#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
#define ETH_MACMDIOAR_CR_Pos                          (8U)
#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
#define ETH_MACMDIOAR_MOC_Pos                         (2U)
#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
#define ETH_MACMDIOAR_C45E_Pos                        (1U)
#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
#define ETH_MACMDIOAR_MB_Pos                          (0U)
#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

/* Bit definition for Ethernet MAC MDIO Data Register */
#define ETH_MACMDIODR_RA_Pos                          (16U)
#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
#define ETH_MACMDIODR_MD_Pos                          (0U)
#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

/* Bit definition for Ethernet ARP Address Register */
#define ETH_MACARPAR_ARPPA_Pos                         (0U)
#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

/* Bit definition for Ethernet MAC Address 0 High Register */
#define ETH_MACA0HR_AE_Pos                            (31U)
#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

/* Bit definition for Ethernet MAC Address 0 Low Register */
#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

/* Bit definition for Ethernet MAC Address 1 High Register */
#define ETH_MACA1HR_AE_Pos                            (31U)
#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
#define ETH_MACA1HR_SA_Pos                            (30U)
#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
#define ETH_MACA1HR_MBC_Pos                           (24U)
#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

/* Bit definition for Ethernet MAC Address 1 Low Register */
#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

/* Bit definition for Ethernet MAC Address 2 High Register */
#define ETH_MACA2HR_AE_Pos                            (31U)
#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
#define ETH_MACA2HR_SA_Pos                            (30U)
#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
#define ETH_MACA2HR_MBC_Pos                           (24U)
#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

/* Bit definition for Ethernet MAC Address 2 Low Register */
#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

/* Bit definition for Ethernet MAC Address 3 High Register */
#define ETH_MACA3HR_AE_Pos                            (31U)
#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
#define ETH_MACA3HR_SA_Pos                            (30U)
#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
#define ETH_MACA3HR_MBC_Pos                           (24U)
#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

/* Bit definition for Ethernet MAC Address 3 Low Register */
#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

/* Bit definition for Ethernet MAC Address High Register */
#define ETH_MACAHR_AE_Pos                             (31U)
#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
#define ETH_MACAHR_SA_Pos                             (30U)
#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
#define ETH_MACAHR_MBC_Pos                            (24U)
#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACAHR_MACAH_Pos                          (0U)
#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

/* Bit definition for Ethernet MAC Address Low Register */
#define ETH_MACALR_MACAL_Pos                          (0U)
#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

/* Bit definition for Ethernet MMC Control Register */
#define ETH_MMCCR_UCDBC_Pos                           (8U)
#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
#define ETH_MMCCR_CNTPRST_Pos                         (4U)
#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
#define ETH_MMCCR_RSTONRD_Pos                         (2U)
#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
#define ETH_MMCCR_CNTRST_Pos                          (0U)
#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

/* Bit definition for Ethernet MMC Rx Interrupt Register */
#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

/* Bit definition for Ethernet MMC Tx Interrupt Register */
#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

/* Bit definition for Ethernet MMC Rx interrupt Mask register */
#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

/* Bit definition for Ethernet MMC Rx alignment error packets register */
#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

/* Bit definition for Ethernet MAC L3 L4 Control Register */
#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

/* Bit definition for Ethernet MAC L4 Address Register */
#define ETH_MACL4AR_L4DP_Pos                          (16U)
#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
#define ETH_MACL4AR_L4SP_Pos                          (0U)
#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

/* Bit definition for Ethernet MAC L3 Address0 Register */
#define ETH_MACL3A0R_L3A0_Pos                         (0U)
#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

/* Bit definition for Ethernet MAC L4 Address1 Register */
#define ETH_MACL3A1R_L3A1_Pos                         (0U)
#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

/* Bit definition for Ethernet MAC L4 Address2 Register */
#define ETH_MACL3A2R_L3A2_Pos                         (0U)
#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

/* Bit definition for Ethernet MAC L4 Address3 Register */
#define ETH_MACL3A3R_L3A3_Pos                         (0U)
#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

/* Bit definition for Ethernet MAC Timestamp Control Register */
#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
#define ETH_MACTSCR_CSC_Pos                           (19U)
#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
#define ETH_MACTSCR_TSENALL_Pos                       (8U)
#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
#define ETH_MACTSCR_TSINIT_Pos                        (2U)
#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
#define ETH_MACTSCR_TSENA_Pos                         (0U)
#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

/* Bit definition for Ethernet MAC Sub-second Increment Register */
#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

/* Bit definition for Ethernet MAC System Time Seconds Register */
#define ETH_MACSTSR_TSS_Pos                           (0U)
#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
#define ETH_MACSTNR_TSSS_Pos                          (0U)
#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

/* Bit definition for Ethernet MAC System Time Seconds Update Register */
#define ETH_MACSTSUR_TSS_Pos                          (0U)
#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
#define ETH_MACSTNUR_TSSS_Pos                         (0U)
#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

/* Bit definition for Ethernet MAC Timestamp Addend Register */
#define ETH_MACTSAR_TSAR_Pos                          (0U)
#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

/* Bit definition for Ethernet MAC Timestamp Status Register */
#define ETH_MACTSSR_ATSNS_Pos                         (25U)
#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

/* Bit definition for Ethernet MAC Auxiliary Control Register*/
#define ETH_MACACR_ATSEN3_Pos                         (7U)
#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
#define ETH_MACACR_ATSEN2_Pos                         (6U)
#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
#define ETH_MACACR_ATSEN1_Pos                         (5U)
#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
#define ETH_MACACR_ATSEN0_Pos                         (4U)
#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
#define ETH_MACACR_ATSFC_Pos                          (0U)
#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
#define ETH_MACTSICNR_TSIC_Pos                        (0U)
#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
#define ETH_MACTSECNR_TSEC_Pos                        (0U)
#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

/* Bit definition for Ethernet MAC PPS Control Register */
#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

/* Bit definition for Ethernet MAC PPS Interval Register */
#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

/* Bit definition for Ethernet MAC PPS Width Register */
#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

/* Bit definition for Ethernet MAC PTP Offload Control Register */
#define ETH_MACPOCR_DN_Pos                            (8U)
#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
#define ETH_MACPOCR_PTOEN_Pos                         (0U)
#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
#define ETH_MACSPI0R_SPI0_Pos                         (0U)
#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
#define ETH_MACSPI1R_SPI1_Pos                         (0U)
#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
#define ETH_MACSPI2R_SPI2_Pos                         (0U)
#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

/* Bit definition for Ethernet MAC Log Message Interval Register */
#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
#define ETH_MACLMIR_LSI_Pos                           (0U)
#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

/* Bit definition for Ethernet MTL Operation Mode Register */
#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

/* Bit definition for Ethernet MTL Interrupt Status Register */
#define ETH_MTLISR_MACIS_Pos                          (16U)
#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
#define ETH_MTLISR_QIS_Pos                            (0U)
#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
#define ETH_MTLTQOMR_TTC_Pos                          (4U)
#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
#define ETH_MTLTQOMR_TSF_Pos                          (1U)
#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

/* Bit definition for Ethernet MTL Tx Queue Debug Register */
#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
#define ETH_MTLRQOMR_RQS_Pos                          (20U)
#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
#define ETH_MTLRQOMR_RFD_Pos                          (14U)
#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define ETH_MTLRQOMR_RFA_Pos                          (8U)
#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
#define ETH_MTLRQOMR_RSF_Pos                          (5U)
#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
#define ETH_MTLRQOMR_FEP_Pos                          (4U)
#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
#define ETH_MTLRQOMR_FUP_Pos                          (3U)
#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
#define ETH_MTLRQOMR_RTC_Pos                          (0U)
#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

/* Bit definition for Ethernet MTL Rx Queue Debug Register */
#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

/* Bit definition for Ethernet MTL Rx Queue Control Register */
#define ETH_MTLRQCR_RQPA_Pos                          (3U)
#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
#define ETH_MTLRQCR_RQW_Pos                           (0U)
#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

/* Bit definition for Ethernet DMA Mode Register */
#define ETH_DMAMR_INTM_Pos                            (16U)
#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
#define ETH_DMAMR_PR_Pos                              (12U)
#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
#define ETH_DMAMR_TXPR_Pos                            (11U)
#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
#define ETH_DMAMR_DA_Pos                              (1U)
#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
#define ETH_DMAMR_SWR_Pos                             (0U)
#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

/* Bit definition for Ethernet DMA SysBus Mode Register */
#define ETH_DMASBMR_RB_Pos                            (15U)
#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
#define ETH_DMASBMR_MB_Pos                            (14U)
#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
#define ETH_DMASBMR_AAL_Pos                           (12U)
#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
#define ETH_DMASBMR_FB_Pos                            (0U)
#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

/* Bit definition for Ethernet DMA Interrupt Status Register */
#define ETH_DMAISR_MACIS_Pos                          (17U)
#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
#define ETH_DMAISR_MTLIS_Pos                          (16U)
#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
#define ETH_DMAISR_DMACIS_Pos                         (0U)
#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

/* Bit definition for Ethernet DMA Debug Status Register */
#define ETH_DMADSR_TPS_Pos                            (12U)
#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_TPS_READING_Pos                    (12U)
#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
#define ETH_DMADSR_RPS_Pos                            (8U)
#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

/* Bit definition for Ethernet DMA Channel Control Register */
#define ETH_DMACCR_DSL_Pos                            (18U)
#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
#define ETH_DMACCR_MSS_Pos                            (0U)
#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

/* Bit definition for Ethernet DMA Channel Tx Control Register */
#define ETH_DMACTCR_TPBL_Pos                          (16U)
#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
#define ETH_DMACTCR_TSE_Pos                           (12U)
#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
#define ETH_DMACTCR_OSP_Pos                           (4U)
#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
#define ETH_DMACTCR_ST_Pos                            (0U)
#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

/* Bit definition for Ethernet DMA Channel Rx Control Register */
#define ETH_DMACRCR_RPF_Pos                           (31U)
#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
#define ETH_DMACRCR_RPBL_Pos                          (16U)
#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
#define ETH_DMACRCR_RBSZ_Pos                          (1U)
#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
#define ETH_DMACRCR_SR_Pos                            (0U)
#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
#define ETH_DMACTDTPR_TDT_Pos                         (2U)
#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
#define ETH_DMACRDTPR_RDT_Pos                         (2U)
#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
#define ETH_DMACIER_NIE_Pos                           (15U)
#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
#define ETH_DMACIER_AIE_Pos                           (14U)
#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
#define ETH_DMACIER_CDEE_Pos                          (13U)
#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
#define ETH_DMACIER_FBEE_Pos                          (12U)
#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
#define ETH_DMACIER_ERIE_Pos                          (11U)
#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
#define ETH_DMACIER_ETIE_Pos                          (10U)
#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
#define ETH_DMACIER_RWTE_Pos                          (9U)
#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
#define ETH_DMACIER_RSE_Pos                           (8U)
#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
#define ETH_DMACIER_RBUE_Pos                          (7U)
#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
#define ETH_DMACIER_RIE_Pos                           (6U)
#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
#define ETH_DMACIER_TBUE_Pos                          (2U)
#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
#define ETH_DMACIER_TXSE_Pos                          (1U)
#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
#define ETH_DMACIER_TIE_Pos                           (0U)
#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
#define ETH_DMACRIWTR_RWT_Pos                         (0U)
#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

/* Bit definition for Ethernet DMA Channel Status Register */
#define ETH_DMACSR_REB_Pos                            (19U)
#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
#define ETH_DMACSR_TEB_Pos                            (16U)
#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
#define ETH_DMACSR_NIS_Pos                            (15U)
#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
#define ETH_DMACSR_AIS_Pos                            (14U)
#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
#define ETH_DMACSR_CDE_Pos                            (13U)
#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
#define ETH_DMACSR_FBE_Pos                            (12U)
#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
#define ETH_DMACSR_ERI_Pos                            (11U)
#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
#define ETH_DMACSR_ETI_Pos                            (10U)
#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
#define ETH_DMACSR_RWT_Pos                            (9U)
#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
#define ETH_DMACSR_RPS_Pos                            (8U)
#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
#define ETH_DMACSR_RBU_Pos                            (7U)
#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
#define ETH_DMACSR_RI_Pos                             (6U)
#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
#define ETH_DMACSR_TBU_Pos                            (2U)
#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
#define ETH_DMACSR_TPS_Pos                            (1U)
#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
#define ETH_DMACSR_TI_Pos                             (0U)
#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

/* Bit definition for Ethernet DMA Channel missed frame count register */
#define ETH_DMACMFCR_MFCO_Pos                         (15U)
#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
#define ETH_DMACMFCR_MFC_Pos                          (0U)
#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

/******************************************************************************/
/*                                                                            */
/*                    External Interrupt/Event Controller                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for EXTI_RTSR1 register  *****************/
#define EXTI_RTSR1_RT0_Pos           (0U)
#define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
#define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
#define EXTI_RTSR1_RT1_Pos           (1U)
#define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
#define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
#define EXTI_RTSR1_RT2_Pos           (2U)
#define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
#define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
#define EXTI_RTSR1_RT3_Pos           (3U)
#define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
#define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
#define EXTI_RTSR1_RT4_Pos           (4U)
#define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
#define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
#define EXTI_RTSR1_RT5_Pos           (5U)
#define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
#define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
#define EXTI_RTSR1_RT6_Pos           (6U)
#define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
#define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
#define EXTI_RTSR1_RT7_Pos           (7U)
#define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
#define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
#define EXTI_RTSR1_RT8_Pos           (8U)
#define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
#define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
#define EXTI_RTSR1_RT9_Pos           (9U)
#define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
#define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
#define EXTI_RTSR1_RT10_Pos          (10U)
#define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
#define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
#define EXTI_RTSR1_RT11_Pos          (11U)
#define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
#define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
#define EXTI_RTSR1_RT12_Pos          (12U)
#define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
#define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
#define EXTI_RTSR1_RT13_Pos          (13U)
#define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
#define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
#define EXTI_RTSR1_RT14_Pos          (14U)
#define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
#define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
#define EXTI_RTSR1_RT15_Pos          (15U)
#define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
#define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
#define EXTI_RTSR1_RT16_Pos          (16U)
#define EXTI_RTSR1_RT16_Msk          (0x1UL << EXTI_RTSR1_RT16_Pos)            /*!< 0x00010000 */
#define EXTI_RTSR1_RT16              EXTI_RTSR1_RT16_Msk                       /*!< Rising trigger configuration for input line 16 */
#define EXTI_RTSR1_RT17_Pos          (17U)
#define EXTI_RTSR1_RT17_Msk          (0x1UL << EXTI_RTSR1_RT17_Pos)            /*!< 0x00020000 */
#define EXTI_RTSR1_RT17              EXTI_RTSR1_RT17_Msk                       /*!< Rising trigger configuration for input line 17 */
#define EXTI_RTSR1_RT18_Pos          (18U)
#define EXTI_RTSR1_RT18_Msk          (0x1UL << EXTI_RTSR1_RT18_Pos)            /*!< 0x00040000 */
#define EXTI_RTSR1_RT18              EXTI_RTSR1_RT18_Msk                       /*!< Rising trigger configuration for input line 18 */
#define EXTI_RTSR1_RT19_Pos          (19U)
#define EXTI_RTSR1_RT19_Msk          (0x1UL << EXTI_RTSR1_RT19_Pos)            /*!< 0x00080000 */
#define EXTI_RTSR1_RT19              EXTI_RTSR1_RT19_Msk                       /*!< Rising trigger configuration for input line 19 */
#define EXTI_RTSR1_RT20_Pos          (20U)
#define EXTI_RTSR1_RT20_Msk          (0x1UL << EXTI_RTSR1_RT20_Pos)            /*!< 0x00100000 */
#define EXTI_RTSR1_RT20              EXTI_RTSR1_RT20_Msk                       /*!< Rising trigger configuration for input line 20 */
#define EXTI_RTSR1_RT21_Pos          (21U)
#define EXTI_RTSR1_RT21_Msk          (0x1UL << EXTI_RTSR1_RT21_Pos)            /*!< 0x00200000 */
#define EXTI_RTSR1_RT21              EXTI_RTSR1_RT21_Msk                       /*!< Rising trigger configuration for input line 21 */

/*******************  Bit definition for EXTI_RTSR2 register  *****************/
#define EXTI_RTSR2_RT34_Pos          (2U)
#define EXTI_RTSR2_RT34_Msk          (0x1UL << EXTI_RTSR2_RT34_Pos)            /*!< 0x00000004 */
#define EXTI_RTSR2_RT34              EXTI_RTSR2_RT34_Msk                       /*!< Rising trigger configuration for input line 34 */
#define EXTI_RTSR2_RT46_Pos          (14U)
#define EXTI_RTSR2_RT46_Msk          (0x1UL << EXTI_RTSR2_RT46_Pos)            /*!< 0x00004000 */
#define EXTI_RTSR2_RT46              EXTI_RTSR2_RT46_Msk                       /*!< Rising trigger configuration for input line 46 */
#define EXTI_RTSR2_RT49_Pos          (17U)
#define EXTI_RTSR2_RT49_Msk          (0x1UL << EXTI_RTSR2_RT49_Pos)            /*!< 0x00020000 */
#define EXTI_RTSR2_RT49              EXTI_RTSR2_RT49_Msk                       /*!< Rising trigger configuration for input line 49 */
#define EXTI_RTSR2_RT51_Pos          (19U)
#define EXTI_RTSR2_RT51_Msk          (0x1UL << EXTI_RTSR2_RT51_Pos)            /*!< 0x00080000 */
#define EXTI_RTSR2_RT51              EXTI_RTSR2_RT51_Msk                       /*!< Rising trigger configuration for input line 51 */
#define EXTI_RTSR2_RT54_Pos          (22U)
#define EXTI_RTSR2_RT54_Msk          (0x1UL << EXTI_RTSR2_RT54_Pos)            /*!< 0x00400000 */
#define EXTI_RTSR2_RT54              EXTI_RTSR2_RT54_Msk                       /*!< Rising trigger configuration for input line 54 */

/*******************  Bit definition for EXTI_FTSR1 register  *****************/
#define EXTI_FTSR1_FT0_Pos           (0U)
#define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
#define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
#define EXTI_FTSR1_FT1_Pos           (1U)
#define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
#define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
#define EXTI_FTSR1_FT2_Pos           (2U)
#define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
#define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
#define EXTI_FTSR1_FT3_Pos           (3U)
#define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
#define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
#define EXTI_FTSR1_FT4_Pos           (4U)
#define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
#define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
#define EXTI_FTSR1_FT5_Pos           (5U)
#define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
#define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
#define EXTI_FTSR1_FT6_Pos           (6U)
#define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
#define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
#define EXTI_FTSR1_FT7_Pos           (7U)
#define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
#define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
#define EXTI_FTSR1_FT8_Pos           (8U)
#define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
#define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
#define EXTI_FTSR1_FT9_Pos           (9U)
#define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
#define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
#define EXTI_FTSR1_FT10_Pos          (10U)
#define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
#define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
#define EXTI_FTSR1_FT11_Pos          (11U)
#define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
#define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
#define EXTI_FTSR1_FT12_Pos          (12U)
#define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
#define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
#define EXTI_FTSR1_FT13_Pos          (13U)
#define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
#define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
#define EXTI_FTSR1_FT14_Pos          (14U)
#define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
#define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
#define EXTI_FTSR1_FT15_Pos          (15U)
#define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
#define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
#define EXTI_FTSR1_FT16_Pos          (16U)
#define EXTI_FTSR1_FT16_Msk          (0x1UL << EXTI_FTSR1_FT16_Pos)            /*!< 0x00010000 */
#define EXTI_FTSR1_FT16              EXTI_FTSR1_FT16_Msk                       /*!< Falling trigger configuration for input line 16 */
#define EXTI_FTSR1_FT17_Pos          (17U)
#define EXTI_FTSR1_FT17_Msk          (0x1UL << EXTI_FTSR1_FT17_Pos)            /*!< 0x00020000 */
#define EXTI_FTSR1_FT17              EXTI_FTSR1_FT17_Msk                       /*!< Falling trigger configuration for input line 17 */
#define EXTI_FTSR1_FT18_Pos          (18U)
#define EXTI_FTSR1_FT18_Msk          (0x1UL << EXTI_FTSR1_FT18_Pos)            /*!< 0x00040000 */
#define EXTI_FTSR1_FT18              EXTI_FTSR1_FT18_Msk                       /*!< Falling trigger configuration for input line 18 */
#define EXTI_FTSR1_FT19_Pos          (19U)
#define EXTI_FTSR1_FT19_Msk          (0x1UL << EXTI_FTSR1_FT19_Pos)            /*!< 0x00080000 */
#define EXTI_FTSR1_FT19              EXTI_FTSR1_FT19_Msk                       /*!< Falling trigger configuration for input line 19 */
#define EXTI_FTSR1_FT20_Pos          (20U)
#define EXTI_FTSR1_FT20_Msk          (0x1UL << EXTI_FTSR1_FT20_Pos)            /*!< 0x00100000 */
#define EXTI_FTSR1_FT20              EXTI_FTSR1_FT20_Msk                       /*!< Falling trigger configuration for input line 20 */
#define EXTI_FTSR1_FT21_Pos          (21U)
#define EXTI_FTSR1_FT21_Msk          (0x1UL << EXTI_FTSR1_FT21_Pos)            /*!< 0x00200000 */
#define EXTI_FTSR1_FT21              EXTI_FTSR1_FT21_Msk                       /*!< Falling trigger configuration for input line 21 */

/*******************  Bit definition for EXTI_FTSR2 register  *****************/
#define EXTI_FTSR2_FT34_Pos          (2U)
#define EXTI_FTSR2_FT34_Msk          (0x1UL << EXTI_FTSR2_FT34_Pos)            /*!< 0x00000004 */
#define EXTI_FTSR2_FT34              EXTI_FTSR2_FT34_Msk                       /*!< Falling trigger configuration for input line 34 */
#define EXTI_FTSR2_FT46_Pos          (14U)
#define EXTI_FTSR2_FT46_Msk          (0x1UL << EXTI_FTSR2_FT46_Pos)            /*!< 0x00004000 */
#define EXTI_FTSR2_FT46              EXTI_FTSR2_FT46_Msk                       /*!< Falling trigger configuration for input line 46 */
#define EXTI_FTSR2_FT49_Pos          (17U)
#define EXTI_FTSR2_FT49_Msk          (0x1UL << EXTI_FTSR2_FT49_Pos)            /*!< 0x00020000 */
#define EXTI_FTSR2_FT49              EXTI_FTSR2_FT49_Msk                       /*!< Falling trigger configuration for input line 49 */
#define EXTI_FTSR2_FT51_Pos          (19U)
#define EXTI_FTSR2_FT51_Msk          (0x1UL << EXTI_FTSR2_FT51_Pos)            /*!< 0x00080000 */
#define EXTI_FTSR2_FT51              EXTI_FTSR2_FT51_Msk                       /*!< Falling trigger configuration for input line 51 */
#define EXTI_FTSR2_FT54_Pos          (22U)
#define EXTI_FTSR2_FT54_Msk          (0x1UL << EXTI_FTSR2_FT54_Pos)            /*!< 0x00400000 */
#define EXTI_FTSR2_FT54              EXTI_FTSR2_FT54_Msk                       /*!< Falling trigger configuration for input line 54 */

/*******************  Bit definition for EXTI_SWIER1 register  ****************/
#define EXTI_SWIER1_SWI0_Pos         (0U)
#define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos         (1U)
#define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos         (2U)
#define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos         (3U)
#define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos         (4U)
#define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos         (5U)
#define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos         (6U)
#define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos         (7U)
#define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos         (8U)
#define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos         (9U)
#define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos        (10U)
#define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos        (11U)
#define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos        (12U)
#define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos        (13U)
#define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos        (14U)
#define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos        (15U)
#define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos        (16U)
#define EXTI_SWIER1_SWI16_Msk        (0x1UL << EXTI_SWIER1_SWI16_Pos)          /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16            EXTI_SWIER1_SWI16_Msk                     /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos        (17U)
#define EXTI_SWIER1_SWI17_Msk        (0x1UL << EXTI_SWIER1_SWI17_Pos)          /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17            EXTI_SWIER1_SWI17_Msk                     /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI18_Pos        (18U)
#define EXTI_SWIER1_SWI18_Msk        (0x1UL << EXTI_SWIER1_SWI18_Pos)          /*!< 0x00040000 */
#define EXTI_SWIER1_SWI18            EXTI_SWIER1_SWI18_Msk                     /*!< Software Interrupt on line 18 */
#define EXTI_SWIER1_SWI19_Pos        (19U)
#define EXTI_SWIER1_SWI19_Msk        (0x1UL << EXTI_SWIER1_SWI19_Pos)          /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19            EXTI_SWIER1_SWI19_Msk                     /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos        (20U)
#define EXTI_SWIER1_SWI20_Msk        (0x1UL << EXTI_SWIER1_SWI20_Pos)          /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20            EXTI_SWIER1_SWI20_Msk                     /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos        (21U)
#define EXTI_SWIER1_SWI21_Msk        (0x1UL << EXTI_SWIER1_SWI21_Pos)          /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21            EXTI_SWIER1_SWI21_Msk                     /*!< Software Interrupt on line 21 */

/*******************  Bit definition for EXTI_SWIER2 register  ****************/
#define EXTI_SWIER2_SWI34_Pos        (2U)
#define EXTI_SWIER2_SWI34_Msk        (0x1UL << EXTI_SWIER2_SWI34_Pos)          /*!< 0x00000004 */
#define EXTI_SWIER2_SWI34            EXTI_SWIER2_SWI34_Msk                     /*!< Software Interrupt on line 34 */
#define EXTI_SWIER2_SWI46_Pos        (14U)
#define EXTI_SWIER2_SWI46_Msk        (0x1UL << EXTI_SWIER2_SWI46_Pos)          /*!< 0x00004000 */
#define EXTI_SWIER2_SWI46            EXTI_SWIER2_SWI46_Msk                     /*!< Software Interrupt on line 46 */
#define EXTI_SWIER2_SWI49_Pos        (17U)
#define EXTI_SWIER2_SWI49_Msk        (0x1UL << EXTI_SWIER2_SWI49_Pos)          /*!< 0x00020000 */
#define EXTI_SWIER2_SWI49            EXTI_SWIER2_SWI49_Msk                     /*!< Software Interrupt on line 49 */
#define EXTI_SWIER2_SWI51_Pos        (19U)
#define EXTI_SWIER2_SWI51_Msk        (0x1UL << EXTI_SWIER2_SWI51_Pos)          /*!< 0x00080000 */
#define EXTI_SWIER2_SWI51            EXTI_SWIER2_SWI51_Msk                     /*!< Software Interrupt on line 51 */
#define EXTI_SWIER2_SWI54_Pos        (22U)
#define EXTI_SWIER2_SWI54_Msk        (0x1UL << EXTI_SWIER2_SWI54_Pos)          /*!< 0x00400000 */
#define EXTI_SWIER2_SWI54            EXTI_SWIER2_SWI54_Msk                     /*!< Software Interrupt on line 54 */

/*******************  Bit definition for EXTI_IMR1 register  ******************/
#define EXTI_IMR1_IM0_Pos            (0U)
#define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
#define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos            (1U)
#define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
#define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos            (2U)
#define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
#define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos            (3U)
#define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
#define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos            (4U)
#define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
#define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos            (5U)
#define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
#define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos            (6U)
#define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
#define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos            (7U)
#define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
#define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos            (8U)
#define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
#define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos            (9U)
#define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
#define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos           (10U)
#define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
#define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos           (11U)
#define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
#define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos           (12U)
#define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
#define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos           (13U)
#define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
#define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos           (14U)
#define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
#define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos           (15U)
#define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
#define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos           (16U)
#define EXTI_IMR1_IM16_Msk           (0x1UL << EXTI_IMR1_IM16_Pos)             /*!< 0x00010000 */
#define EXTI_IMR1_IM16               EXTI_IMR1_IM16_Msk                        /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos           (17U)
#define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
#define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos           (18U)
#define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
#define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos           (19U)
#define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
#define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos           (20U)
#define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */
#define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos           (21U)
#define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
#define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos           (22U)
#define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */
#define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos           (23U)
#define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
#define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos           (24U)
#define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */
#define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos           (25U)
#define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
#define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos           (26U)
#define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
#define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos           (27U)
#define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
#define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos           (28U)
#define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
#define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos           (29U)
#define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
#define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos           (30U)
#define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
#define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos           (31U)
#define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)             /*!< 0x80000000 */
#define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */

/*******************  Bit definition for EXTI_IMR2 register  ******************/
#define EXTI_IMR2_IM32_Pos           (0U)
#define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
#define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos           (1U)
#define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
#define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos           (2U)
#define EXTI_IMR2_IM34_Msk           (0x1UL << EXTI_IMR2_IM34_Pos)             /*!< 0x00000004 */
#define EXTI_IMR2_IM34               EXTI_IMR2_IM34_Msk                        /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos           (3U)
#define EXTI_IMR2_IM35_Msk           (0x1UL << EXTI_IMR2_IM35_Pos)             /*!< 0x00000008 */
#define EXTI_IMR2_IM35               EXTI_IMR2_IM35_Msk                        /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos           (4U)
#define EXTI_IMR2_IM36_Msk           (0x1UL << EXTI_IMR2_IM36_Pos)             /*!< 0x00000010 */
#define EXTI_IMR2_IM36               EXTI_IMR2_IM36_Msk                        /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos           (5U)
#define EXTI_IMR2_IM37_Msk           (0x1UL << EXTI_IMR2_IM37_Pos)             /*!< 0x00000020 */
#define EXTI_IMR2_IM37               EXTI_IMR2_IM37_Msk                        /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos           (6U)
#define EXTI_IMR2_IM38_Msk           (0x1UL << EXTI_IMR2_IM38_Pos)             /*!< 0x00000040 */
#define EXTI_IMR2_IM38               EXTI_IMR2_IM38_Msk                        /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos           (7U)
#define EXTI_IMR2_IM39_Msk           (0x1UL << EXTI_IMR2_IM39_Pos)             /*!< 0x00000080 */
#define EXTI_IMR2_IM39               EXTI_IMR2_IM39_Msk                        /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos           (8U)
#define EXTI_IMR2_IM40_Msk           (0x1UL << EXTI_IMR2_IM40_Pos)             /*!< 0x00000100 */
#define EXTI_IMR2_IM40               EXTI_IMR2_IM40_Msk                        /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos           (9U)
#define EXTI_IMR2_IM41_Msk           (0x1UL << EXTI_IMR2_IM41_Pos)             /*!< 0x00000200 */
#define EXTI_IMR2_IM41               EXTI_IMR2_IM41_Msk                        /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos           (10U)
#define EXTI_IMR2_IM42_Msk           (0x1UL << EXTI_IMR2_IM42_Pos)             /*!< 0x00000400 */
#define EXTI_IMR2_IM42               EXTI_IMR2_IM42_Msk                        /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM43_Pos           (11U)
#define EXTI_IMR2_IM43_Msk           (0x1UL << EXTI_IMR2_IM43_Pos)             /*!< 0x00000800 */
#define EXTI_IMR2_IM43               EXTI_IMR2_IM43_Msk                        /*!< Interrupt Mask on line 43 */
#define EXTI_IMR2_IM44_Pos           (12U)
#define EXTI_IMR2_IM44_Msk           (0x1UL << EXTI_IMR2_IM44_Pos)             /*!< 0x00001000 */
#define EXTI_IMR2_IM44               EXTI_IMR2_IM44_Msk                        /*!< Interrupt Mask on line 44 */
#define EXTI_IMR2_IM45_Pos           (13U)
#define EXTI_IMR2_IM45_Msk           (0x1UL << EXTI_IMR2_IM45_Pos)             /*!< 0x00002000 */
#define EXTI_IMR2_IM45               EXTI_IMR2_IM45_Msk                        /*!< Interrupt Mask on line 45 */
#define EXTI_IMR2_IM46_Pos           (14U)
#define EXTI_IMR2_IM46_Msk           (0x1UL << EXTI_IMR2_IM46_Pos)             /*!< 0x00004000 */
#define EXTI_IMR2_IM46               EXTI_IMR2_IM46_Msk                        /*!< Interrupt Mask on line 46 */
#define EXTI_IMR2_IM47_Pos           (15U)
#define EXTI_IMR2_IM47_Msk           (0x1UL << EXTI_IMR2_IM47_Pos)             /*!< 0x00008000 */
#define EXTI_IMR2_IM47               EXTI_IMR2_IM47_Msk                        /*!< Interrupt Mask on line 47 */
#define EXTI_IMR2_IM48_Pos           (16U)
#define EXTI_IMR2_IM48_Msk           (0x1UL << EXTI_IMR2_IM48_Pos)             /*!< 0x00010000 */
#define EXTI_IMR2_IM48               EXTI_IMR2_IM48_Msk                        /*!< Interrupt Mask on line 48 */
#define EXTI_IMR2_IM49_Pos           (17U)
#define EXTI_IMR2_IM49_Msk           (0x1UL << EXTI_IMR2_IM49_Pos)             /*!< 0x00020000 */
#define EXTI_IMR2_IM49               EXTI_IMR2_IM49_Msk                        /*!< Interrupt Mask on line 49 */
#define EXTI_IMR2_IM50_Pos           (18U)
#define EXTI_IMR2_IM50_Msk           (0x1UL << EXTI_IMR2_IM50_Pos)             /*!< 0x00040000 */
#define EXTI_IMR2_IM50               EXTI_IMR2_IM50_Msk                        /*!< Interrupt Mask on line 50 */
#define EXTI_IMR2_IM51_Pos           (19U)
#define EXTI_IMR2_IM51_Msk           (0x1UL << EXTI_IMR2_IM51_Pos)             /*!< 0x00080000 */
#define EXTI_IMR2_IM51               EXTI_IMR2_IM51_Msk                        /*!< Interrupt Mask on line 51 */
#define EXTI_IMR2_IM52_Pos           (20U)
#define EXTI_IMR2_IM52_Msk           (0x1UL << EXTI_IMR2_IM52_Pos)             /*!< 0x00100000 */
#define EXTI_IMR2_IM52               EXTI_IMR2_IM52_Msk                        /*!< Interrupt Mask on line 52 */
#define EXTI_IMR2_IM53_Pos           (21U)
#define EXTI_IMR2_IM53_Msk           (0x1UL << EXTI_IMR2_IM53_Pos)             /*!< 0x00200000 */
#define EXTI_IMR2_IM53               EXTI_IMR2_IM53_Msk                        /*!< Interrupt Mask on line 53 */
#define EXTI_IMR2_IM54_Pos           (22U)
#define EXTI_IMR2_IM54_Msk           (0x1UL << EXTI_IMR2_IM54_Pos)             /*!< 0x00400000 */
#define EXTI_IMR2_IM54               EXTI_IMR2_IM54_Msk                        /*!< Interrupt Mask on line 54 */
#define EXTI_IMR2_IM55_Pos           (23U)
#define EXTI_IMR2_IM55_Msk           (0x1UL << EXTI_IMR2_IM55_Pos)             /*!< 0x00800000 */
#define EXTI_IMR2_IM55               EXTI_IMR2_IM55_Msk                        /*!< Interrupt Mask on line 55 */
#define EXTI_IMR2_IM56_Pos           (24U)
#define EXTI_IMR2_IM56_Msk           (0x1UL << EXTI_IMR2_IM56_Pos)             /*!< 0x01000000 */
#define EXTI_IMR2_IM56               EXTI_IMR2_IM56_Msk                        /*!< Interrupt Mask on line 56 */
#define EXTI_IMR2_IM57_Pos           (25U)
#define EXTI_IMR2_IM57_Msk           (0x1UL << EXTI_IMR2_IM57_Pos)             /*!< 0x02000000 */
#define EXTI_IMR2_IM57               EXTI_IMR2_IM57_Msk                        /*!< Interrupt Mask on line 57 */
#define EXTI_IMR2_IM58_Pos           (26U)
#define EXTI_IMR2_IM58_Msk           (0x1UL << EXTI_IMR2_IM58_Pos)             /*!< 0x04000000 */
#define EXTI_IMR2_IM58               EXTI_IMR2_IM58_Msk                        /*!< Interrupt Mask on line 58 */
#define EXTI_IMR2_IM59_Pos           (27U)
#define EXTI_IMR2_IM59_Msk           (0x1UL << EXTI_IMR2_IM59_Pos)             /*!< 0x08000000 */
#define EXTI_IMR2_IM59               EXTI_IMR2_IM59_Msk                        /*!< Interrupt Mask on line 59 */

/*******************  Bit definition for EXTI_IMR3 register  ******************/
#define EXTI_IMR3_IM77_Pos           (13U)
#define EXTI_IMR3_IM77_Msk           (0x1UL << EXTI_IMR3_IM77_Pos)             /*!< 0x00002000 */
#define EXTI_IMR3_IM77               EXTI_IMR3_IM77_Msk                        /*!< Interrupt Mask on line 77 */

/*******************  Bit definition for EXTI_EMR1 register  ******************/
#define EXTI_EMR1_EM0_Pos            (0U)
#define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
#define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos            (1U)
#define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
#define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos            (2U)
#define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
#define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos            (3U)
#define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
#define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos            (4U)
#define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
#define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos            (5U)
#define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
#define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos            (6U)
#define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
#define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos            (7U)
#define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
#define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos            (8U)
#define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
#define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos            (9U)
#define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
#define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos           (10U)
#define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
#define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos           (11U)
#define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
#define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos           (12U)
#define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
#define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos           (13U)
#define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
#define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos           (14U)
#define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
#define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos           (15U)
#define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
#define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos           (16U)
#define EXTI_EMR1_EM16_Msk           (0x1UL << EXTI_EMR1_EM16_Pos)             /*!< 0x00010000 */
#define EXTI_EMR1_EM16               EXTI_EMR1_EM16_Msk                        /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos           (17U)
#define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
#define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos           (18U)
#define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
#define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos           (19U)
#define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
#define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos           (20U)
#define EXTI_EMR1_EM20_Msk           (0x1UL << EXTI_EMR1_EM20_Pos)             /*!< 0x00100000 */
#define EXTI_EMR1_EM20               EXTI_EMR1_EM20_Msk                        /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos           (21U)
#define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
#define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos           (22U)
#define EXTI_EMR1_EM22_Msk           (0x1UL << EXTI_EMR1_EM22_Pos)             /*!< 0x00400000 */
#define EXTI_EMR1_EM22               EXTI_EMR1_EM22_Msk                        /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos           (23U)
#define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
#define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos           (24U)
#define EXTI_EMR1_EM24_Msk           (0x1UL << EXTI_EMR1_EM24_Pos)             /*!< 0x01000000 */
#define EXTI_EMR1_EM24               EXTI_EMR1_EM24_Msk                        /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos           (25U)
#define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
#define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos           (26U)
#define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
#define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos           (27U)
#define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
#define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos           (28U)
#define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
#define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM30_Pos           (30U)
#define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
#define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos           (31U)
#define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
#define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */

/*******************  Bit definition for EXTI_EMR2 register  ******************/
#define EXTI_EMR2_EM32_Pos           (0U)
#define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
#define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
#define EXTI_EMR2_EM33_Pos           (1U)
#define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
#define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos           (2U)
#define EXTI_EMR2_EM34_Msk           (0x1UL << EXTI_EMR2_EM34_Pos)             /*!< 0x00000004 */
#define EXTI_EMR2_EM34               EXTI_EMR2_EM34_Msk                        /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos           (3U)
#define EXTI_EMR2_EM35_Msk           (0x1UL << EXTI_EMR2_EM35_Pos)             /*!< 0x00000008 */
#define EXTI_EMR2_EM35               EXTI_EMR2_EM35_Msk                        /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos           (4U)
#define EXTI_EMR2_EM36_Msk           (0x1UL << EXTI_EMR2_EM36_Pos)             /*!< 0x00000010 */
#define EXTI_EMR2_EM36               EXTI_EMR2_EM36_Msk                        /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos           (5U)
#define EXTI_EMR2_EM37_Msk           (0x1UL << EXTI_EMR2_EM37_Pos)             /*!< 0x00000020 */
#define EXTI_EMR2_EM37               EXTI_EMR2_EM37_Msk                        /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos           (6U)
#define EXTI_EMR2_EM38_Msk           (0x1UL << EXTI_EMR2_EM38_Pos)             /*!< 0x00000040 */
#define EXTI_EMR2_EM38               EXTI_EMR2_EM38_Msk                        /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos           (7U)
#define EXTI_EMR2_EM39_Msk           (0x1UL << EXTI_EMR2_EM39_Pos)             /*!< 0x00000080 */
#define EXTI_EMR2_EM39               EXTI_EMR2_EM39_Msk                        /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos           (8U)
#define EXTI_EMR2_EM40_Msk           (0x1UL << EXTI_EMR2_EM40_Pos)             /*!< 0x00000100 */
#define EXTI_EMR2_EM40               EXTI_EMR2_EM40_Msk                        /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos           (9U)
#define EXTI_EMR2_EM41_Msk           (0x1UL << EXTI_EMR2_EM41_Pos)             /*!< 0x00000200 */
#define EXTI_EMR2_EM41               EXTI_EMR2_EM41_Msk                        /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM42_Pos           (10U)
#define EXTI_EMR2_EM42_Msk           (0x1UL << EXTI_EMR2_EM42_Pos)             /*!< 0x00000400 */
#define EXTI_EMR2_EM42               EXTI_EMR2_EM42_Msk                        /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM43_Pos           (11U)
#define EXTI_EMR2_EM43_Msk           (0x1UL << EXTI_EMR2_EM43_Pos)             /*!< 0x00000800 */
#define EXTI_EMR2_EM43               EXTI_EMR2_EM43_Msk                        /*!< Event Mask on line 43 */
#define EXTI_EMR2_EM44_Pos           (12U)
#define EXTI_EMR2_EM44_Msk           (0x1UL << EXTI_EMR2_EM44_Pos)             /*!< 0x00001000 */
#define EXTI_EMR2_EM44               EXTI_EMR2_EM44_Msk                        /*!< Event Mask on line 44 */
#define EXTI_EMR2_EM45_Pos           (13U)
#define EXTI_EMR2_EM45_Msk           (0x1UL << EXTI_EMR2_EM45_Pos)             /*!< 0x00002000 */
#define EXTI_EMR2_EM45               EXTI_EMR2_EM45_Msk                        /*!< Event Mask on line 45 */
#define EXTI_EMR2_EM46_Pos           (14U)
#define EXTI_EMR2_EM46_Msk           (0x1UL << EXTI_EMR2_EM46_Pos)             /*!< 0x00004000 */
#define EXTI_EMR2_EM46               EXTI_EMR2_EM46_Msk                        /*!< Event Mask on line 46 */
#define EXTI_EMR2_EM47_Pos           (15U)
#define EXTI_EMR2_EM47_Msk           (0x1UL << EXTI_EMR2_EM47_Pos)             /*!< 0x00008000 */
#define EXTI_EMR2_EM47               EXTI_EMR2_EM47_Msk                        /*!< Event Mask on line 47 */
#define EXTI_EMR2_EM48_Pos           (16U)
#define EXTI_EMR2_EM48_Msk           (0x1UL << EXTI_EMR2_EM48_Pos)             /*!< 0x00010000 */
#define EXTI_EMR2_EM48               EXTI_EMR2_EM48_Msk                        /*!< Event Mask on line 48 */
#define EXTI_EMR2_EM49_Pos           (17U)
#define EXTI_EMR2_EM49_Msk           (0x1UL << EXTI_EMR2_EM49_Pos)             /*!< 0x00020000 */
#define EXTI_EMR2_EM49               EXTI_EMR2_EM49_Msk                        /*!< Event Mask on line 49 */
#define EXTI_EMR2_EM50_Pos           (18U)
#define EXTI_EMR2_EM50_Msk           (0x1UL << EXTI_EMR2_EM50_Pos)             /*!< 0x00040000 */
#define EXTI_EMR2_EM50               EXTI_EMR2_EM50_Msk                        /*!< Event Mask on line 50 */
#define EXTI_EMR2_EM51_Pos           (19U)
#define EXTI_EMR2_EM51_Msk           (0x1UL << EXTI_EMR2_EM51_Pos)             /*!< 0x00080000 */
#define EXTI_EMR2_EM51               EXTI_EMR2_EM51_Msk                        /*!< Event Mask on line 51 */
#define EXTI_EMR2_EM52_Pos           (20U)
#define EXTI_EMR2_EM52_Msk           (0x1UL << EXTI_EMR2_EM52_Pos)             /*!< 0x00100000 */
#define EXTI_EMR2_EM52               EXTI_EMR2_EM52_Msk                        /*!< Event Mask on line 52 */
#define EXTI_EMR2_EM53_Pos           (21U)
#define EXTI_EMR2_EM53_Msk           (0x1UL << EXTI_EMR2_EM53_Pos)             /*!< 0x00200000 */
#define EXTI_EMR2_EM53               EXTI_EMR2_EM53_Msk                        /*!< Event Mask on line 53 */
#define EXTI_EMR2_EM54_Pos           (22U)
#define EXTI_EMR2_EM54_Msk           (0x1UL << EXTI_EMR2_EM54_Pos)             /*!< 0x00400000 */
#define EXTI_EMR2_EM54               EXTI_EMR2_EM54_Msk                        /*!< Event Mask on line 54 */
#define EXTI_EMR2_EM55_Pos           (23U)
#define EXTI_EMR2_EM55_Msk           (0x1UL << EXTI_EMR2_EM55_Pos)             /*!< 0x00800000 */
#define EXTI_EMR2_EM55               EXTI_EMR2_EM55_Msk                        /*!< Event Mask on line 55 */
#define EXTI_EMR2_EM56_Pos           (24U)
#define EXTI_EMR2_EM56_Msk           (0x1UL << EXTI_EMR2_EM56_Pos)             /*!< 0x01000000 */
#define EXTI_EMR2_EM56               EXTI_EMR2_EM56_Msk                        /*!< Event Mask on line 56 */
#define EXTI_EMR2_EM57_Pos           (25U)
#define EXTI_EMR2_EM57_Msk           (0x1UL << EXTI_EMR2_EM57_Pos)             /*!< 0x02000000 */
#define EXTI_EMR2_EM57               EXTI_EMR2_EM57_Msk                        /*!< Event Mask on line 57 */
#define EXTI_EMR2_EM58_Pos           (26U)
#define EXTI_EMR2_EM58_Msk           (0x1UL << EXTI_EMR2_EM58_Pos)             /*!< 0x04000000 */
#define EXTI_EMR2_EM58               EXTI_EMR2_EM58_Msk                        /*!< Event Mask on line 58 */
#define EXTI_EMR2_EM59_Pos           (27U)
#define EXTI_EMR2_EM59_Msk           (0x1UL << EXTI_EMR2_EM59_Pos)             /*!< 0x08000000 */
#define EXTI_EMR2_EM59               EXTI_EMR2_EM59_Msk                        /*!< Event Mask on line 59 */

/*******************  Bit definition for EXTI_EMR3 register  ******************/
#define EXTI_EMR3_EM77_Pos           (13U)
#define EXTI_EMR3_EM77_Msk           (0x1UL << EXTI_EMR3_EM77_Pos)             /*!< 0x00002000 */
#define EXTI_EMR3_EM77               EXTI_EMR3_EM77_Msk                        /*!< Event Mask on line 77 */

/*******************  Bit definition for EXTI_PR1 register  *******************/
#define EXTI_PR1_PR0_Pos             (0U)
#define EXTI_PR1_PR0_Msk             (0x1UL << EXTI_PR1_PR0_Pos)               /*!< 0x00000001 */
#define EXTI_PR1_PR0                 EXTI_PR1_PR0_Msk                          /*!< Pending bit for line 0 */
#define EXTI_PR1_PR1_Pos             (1U)
#define EXTI_PR1_PR1_Msk             (0x1UL << EXTI_PR1_PR1_Pos)               /*!< 0x00000002 */
#define EXTI_PR1_PR1                 EXTI_PR1_PR1_Msk                          /*!< Pending bit for line 1 */
#define EXTI_PR1_PR2_Pos             (2U)
#define EXTI_PR1_PR2_Msk             (0x1UL << EXTI_PR1_PR2_Pos)               /*!< 0x00000004 */
#define EXTI_PR1_PR2                 EXTI_PR1_PR2_Msk                          /*!< Pending bit for line 2 */
#define EXTI_PR1_PR3_Pos             (3U)
#define EXTI_PR1_PR3_Msk             (0x1UL << EXTI_PR1_PR3_Pos)               /*!< 0x00000008 */
#define EXTI_PR1_PR3                 EXTI_PR1_PR3_Msk                          /*!< Pending bit for line 3 */
#define EXTI_PR1_PR4_Pos             (4U)
#define EXTI_PR1_PR4_Msk             (0x1UL << EXTI_PR1_PR4_Pos)               /*!< 0x00000010 */
#define EXTI_PR1_PR4                 EXTI_PR1_PR4_Msk                          /*!< Pending bit for line 4 */
#define EXTI_PR1_PR5_Pos             (5U)
#define EXTI_PR1_PR5_Msk             (0x1UL << EXTI_PR1_PR5_Pos)               /*!< 0x00000020 */
#define EXTI_PR1_PR5                 EXTI_PR1_PR5_Msk                          /*!< Pending bit for line 5 */
#define EXTI_PR1_PR6_Pos             (6U)
#define EXTI_PR1_PR6_Msk             (0x1UL << EXTI_PR1_PR6_Pos)               /*!< 0x00000040 */
#define EXTI_PR1_PR6                 EXTI_PR1_PR6_Msk                          /*!< Pending bit for line 6 */
#define EXTI_PR1_PR7_Pos             (7U)
#define EXTI_PR1_PR7_Msk             (0x1UL << EXTI_PR1_PR7_Pos)               /*!< 0x00000080 */
#define EXTI_PR1_PR7                 EXTI_PR1_PR7_Msk                          /*!< Pending bit for line 7 */
#define EXTI_PR1_PR8_Pos             (8U)
#define EXTI_PR1_PR8_Msk             (0x1UL << EXTI_PR1_PR8_Pos)               /*!< 0x00000100 */
#define EXTI_PR1_PR8                 EXTI_PR1_PR8_Msk                          /*!< Pending bit for line 8 */
#define EXTI_PR1_PR9_Pos             (9U)
#define EXTI_PR1_PR9_Msk             (0x1UL << EXTI_PR1_PR9_Pos)               /*!< 0x00000200 */
#define EXTI_PR1_PR9                 EXTI_PR1_PR9_Msk                          /*!< Pending bit for line 9 */
#define EXTI_PR1_PR10_Pos            (10U)
#define EXTI_PR1_PR10_Msk            (0x1UL << EXTI_PR1_PR10_Pos)              /*!< 0x00000400 */
#define EXTI_PR1_PR10                EXTI_PR1_PR10_Msk                         /*!< Pending bit for line 10 */
#define EXTI_PR1_PR11_Pos            (11U)
#define EXTI_PR1_PR11_Msk            (0x1UL << EXTI_PR1_PR11_Pos)              /*!< 0x00000800 */
#define EXTI_PR1_PR11                EXTI_PR1_PR11_Msk                         /*!< Pending bit for line 11 */
#define EXTI_PR1_PR12_Pos            (12U)
#define EXTI_PR1_PR12_Msk            (0x1UL << EXTI_PR1_PR12_Pos)              /*!< 0x00001000 */
#define EXTI_PR1_PR12                EXTI_PR1_PR12_Msk                         /*!< Pending bit for line 12 */
#define EXTI_PR1_PR13_Pos            (13U)
#define EXTI_PR1_PR13_Msk            (0x1UL << EXTI_PR1_PR13_Pos)              /*!< 0x00002000 */
#define EXTI_PR1_PR13                EXTI_PR1_PR13_Msk                         /*!< Pending bit for line 13 */
#define EXTI_PR1_PR14_Pos            (14U)
#define EXTI_PR1_PR14_Msk            (0x1UL << EXTI_PR1_PR14_Pos)              /*!< 0x00004000 */
#define EXTI_PR1_PR14                EXTI_PR1_PR14_Msk                         /*!< Pending bit for line 14 */
#define EXTI_PR1_PR15_Pos            (15U)
#define EXTI_PR1_PR15_Msk            (0x1UL << EXTI_PR1_PR15_Pos)              /*!< 0x00008000 */
#define EXTI_PR1_PR15                EXTI_PR1_PR15_Msk                         /*!< Pending bit for line 15 */
#define EXTI_PR1_PR16_Pos            (16U)
#define EXTI_PR1_PR16_Msk            (0x1UL << EXTI_PR1_PR16_Pos)              /*!< 0x00010000 */
#define EXTI_PR1_PR16                EXTI_PR1_PR16_Msk                         /*!< Pending bit for line 16 */
#define EXTI_PR1_PR17_Pos            (17U)
#define EXTI_PR1_PR17_Msk            (0x1UL << EXTI_PR1_PR17_Pos)              /*!< 0x00020000 */
#define EXTI_PR1_PR17                EXTI_PR1_PR17_Msk                         /*!< Pending bit for line 17 */
#define EXTI_PR1_PR18_Pos            (18U)
#define EXTI_PR1_PR18_Msk            (0x1UL << EXTI_PR1_PR18_Pos)              /*!< 0x00040000 */
#define EXTI_PR1_PR18                EXTI_PR1_PR18_Msk                         /*!< Pending bit for line 18 */
#define EXTI_PR1_PR19_Pos            (19U)
#define EXTI_PR1_PR19_Msk            (0x1UL << EXTI_PR1_PR19_Pos)              /*!< 0x00080000 */
#define EXTI_PR1_PR19                EXTI_PR1_PR19_Msk                         /*!< Pending bit for line 19 */
#define EXTI_PR1_PR20_Pos            (20U)
#define EXTI_PR1_PR20_Msk            (0x1UL << EXTI_PR1_PR20_Pos)              /*!< 0x00100000 */
#define EXTI_PR1_PR20                EXTI_PR1_PR20_Msk                         /*!< Pending bit for line 20 */
#define EXTI_PR1_PR21_Pos            (21U)
#define EXTI_PR1_PR21_Msk            (0x1UL << EXTI_PR1_PR21_Pos)              /*!< 0x00200000 */
#define EXTI_PR1_PR21                EXTI_PR1_PR21_Msk                         /*!< Pending bit for line 21 */

/*******************  Bit definition for EXTI_PR2 register  *******************/
#define EXTI_PR2_PR34_Pos            (2U)
#define EXTI_PR2_PR34_Msk            (0x1UL << EXTI_PR2_PR34_Pos)              /*!< 0x00000004 */
#define EXTI_PR2_PR34                EXTI_PR2_PR34_Msk                        /*!< Event Mask on line 34 */
#define EXTI_PR2_PR46_Pos            (14U)
#define EXTI_PR2_PR46_Msk            (0x1UL << EXTI_PR2_PR46_Pos)             /*!< 0x00004000 */
#define EXTI_PR2_PR46                EXTI_PR2_PR46_Msk                        /*!< Event Mask on line 46 */
#define EXTI_PR2_PR49_Pos            (17U)
#define EXTI_PR2_PR49_Msk            (0x1UL << EXTI_PR2_PR49_Pos)             /*!< 0x00020000 */
#define EXTI_PR2_PR49                EXTI_PR2_PR49_Msk                        /*!< Event Mask on line 49 */
#define EXTI_PR2_PR51_Pos            (19U)
#define EXTI_PR2_PR51_Msk            (0x1UL << EXTI_PR2_PR51_Pos)             /*!< 0x00080000 */
#define EXTI_PR2_PR51                EXTI_PR2_PR51_Msk                        /*!< Event Mask on line 51 */
#define EXTI_PR2_PR54_Pos            (22U)
#define EXTI_PR2_PR54_Msk            (0x1UL << EXTI_PR2_PR54_Pos)             /*!< 0x00400000 */
#define EXTI_PR2_PR54                EXTI_PR2_PR54_Msk                        /*!< Event Mask on line 54 */

/******************************************************************************/
/*                                                                            */
/*                 Flexible Datarate Controller Area Network                  */
/*                                                                            */
/******************************************************************************/
/*!<FDCAN control and status registers */
/*****************  Bit definition for FDCAN_CREL register  *******************/
#define FDCAN_CREL_DAY_Pos           (0U)
#define FDCAN_CREL_DAY_Msk           (0xFFUL << FDCAN_CREL_DAY_Pos)            /*!< 0x000000FF */
#define FDCAN_CREL_DAY               FDCAN_CREL_DAY_Msk                        /*!<Timestamp Day                           */
#define FDCAN_CREL_MON_Pos           (8U)
#define FDCAN_CREL_MON_Msk           (0xFFUL << FDCAN_CREL_MON_Pos)            /*!< 0x0000FF00 */
#define FDCAN_CREL_MON               FDCAN_CREL_MON_Msk                        /*!<Timestamp Month                         */
#define FDCAN_CREL_YEAR_Pos          (16U)
#define FDCAN_CREL_YEAR_Msk          (0xFUL << FDCAN_CREL_YEAR_Pos)            /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR              FDCAN_CREL_YEAR_Msk                       /*!<Timestamp Year                          */
#define FDCAN_CREL_SUBSTEP_Pos       (20U)
#define FDCAN_CREL_SUBSTEP_Msk       (0xFUL << FDCAN_CREL_SUBSTEP_Pos)         /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP           FDCAN_CREL_SUBSTEP_Msk                    /*!<Sub-step of Core release                */
#define FDCAN_CREL_STEP_Pos          (24U)
#define FDCAN_CREL_STEP_Msk          (0xFUL << FDCAN_CREL_STEP_Pos)            /*!< 0x0F000000 */
#define FDCAN_CREL_STEP              FDCAN_CREL_STEP_Msk                       /*!<Step of Core release                    */
#define FDCAN_CREL_REL_Pos           (28U)
#define FDCAN_CREL_REL_Msk           (0xFUL << FDCAN_CREL_REL_Pos)             /*!< 0xF0000000 */
#define FDCAN_CREL_REL               FDCAN_CREL_REL_Msk                        /*!<Core release                            */

/*****************  Bit definition for FDCAN_ENDN register  *******************/
#define FDCAN_ENDN_ETV_Pos           (0U)
#define FDCAN_ENDN_ETV_Msk           (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)      /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV               FDCAN_ENDN_ETV_Msk                        /*!<Endianness Test Value                    */

/*****************  Bit definition for FDCAN_DBTP register  *******************/
#define FDCAN_DBTP_DSJW_Pos          (0U)
#define FDCAN_DBTP_DSJW_Msk          (0xFUL << FDCAN_DBTP_DSJW_Pos)            /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW              FDCAN_DBTP_DSJW_Msk                       /*!<Synchronization Jump Width              */
#define FDCAN_DBTP_DTSEG2_Pos        (4U)
#define FDCAN_DBTP_DTSEG2_Msk        (0xFUL << FDCAN_DBTP_DTSEG2_Pos)          /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2            FDCAN_DBTP_DTSEG2_Msk                     /*!<Data time segment after sample point    */
#define FDCAN_DBTP_DTSEG1_Pos        (8U)
#define FDCAN_DBTP_DTSEG1_Msk        (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)         /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1            FDCAN_DBTP_DTSEG1_Msk                     /*!<Data time segment before sample point   */
#define FDCAN_DBTP_DBRP_Pos          (16U)
#define FDCAN_DBTP_DBRP_Msk          (0x1FUL << FDCAN_DBTP_DBRP_Pos)           /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP              FDCAN_DBTP_DBRP_Msk                       /*!<Data BIt Rate Prescaler                 */
#define FDCAN_DBTP_TDC_Pos           (23U)
#define FDCAN_DBTP_TDC_Msk           (0x1UL << FDCAN_DBTP_TDC_Pos)             /*!< 0x00800000 */
#define FDCAN_DBTP_TDC               FDCAN_DBTP_TDC_Msk                        /*!<Transceiver Delay Compensation          */

/*****************  Bit definition for FDCAN_TEST register  *******************/
#define FDCAN_TEST_LBCK_Pos          (4U)
#define FDCAN_TEST_LBCK_Msk          (0x1UL << FDCAN_TEST_LBCK_Pos)            /*!< 0x00000010 */
#define FDCAN_TEST_LBCK              FDCAN_TEST_LBCK_Msk                       /*!<Loop Back mode                           */
#define FDCAN_TEST_TX_Pos            (5U)
#define FDCAN_TEST_TX_Msk            (0x3UL << FDCAN_TEST_TX_Pos)              /*!< 0x00000060 */
#define FDCAN_TEST_TX                FDCAN_TEST_TX_Msk                         /*!<Control of Transmit Pin                  */
#define FDCAN_TEST_RX_Pos            (7U)
#define FDCAN_TEST_RX_Msk            (0x1UL << FDCAN_TEST_RX_Pos)              /*!< 0x00000080 */
#define FDCAN_TEST_RX                FDCAN_TEST_RX_Msk                         /*!<Receive Pin                              */

/*****************  Bit definition for FDCAN_RWD register  ********************/
#define FDCAN_RWD_WDC_Pos            (0U)
#define FDCAN_RWD_WDC_Msk            (0xFFUL << FDCAN_RWD_WDC_Pos)             /*!< 0x000000FF */
#define FDCAN_RWD_WDC                FDCAN_RWD_WDC_Msk                         /*!<Watchdog configuration                   */
#define FDCAN_RWD_WDV_Pos            (8U)
#define FDCAN_RWD_WDV_Msk            (0xFFUL << FDCAN_RWD_WDV_Pos)             /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV                FDCAN_RWD_WDV_Msk                         /*!<Watchdog value                           */

/*****************  Bit definition for FDCAN_CCCR register  *******************/
#define FDCAN_CCCR_INIT_Pos          (0U)
#define FDCAN_CCCR_INIT_Msk          (0x1UL << FDCAN_CCCR_INIT_Pos)            /*!< 0x00000001 */
#define FDCAN_CCCR_INIT              FDCAN_CCCR_INIT_Msk                       /*!<Initialization                           */
#define FDCAN_CCCR_CCE_Pos           (1U)
#define FDCAN_CCCR_CCE_Msk           (0x1UL << FDCAN_CCCR_CCE_Pos)             /*!< 0x00000002 */
#define FDCAN_CCCR_CCE               FDCAN_CCCR_CCE_Msk                        /*!<Configuration Change Enable              */
#define FDCAN_CCCR_ASM_Pos           (2U)
#define FDCAN_CCCR_ASM_Msk           (0x1UL << FDCAN_CCCR_ASM_Pos)             /*!< 0x00000004 */
#define FDCAN_CCCR_ASM               FDCAN_CCCR_ASM_Msk                        /*!<ASM Restricted Operation Mode            */
#define FDCAN_CCCR_CSA_Pos           (3U)
#define FDCAN_CCCR_CSA_Msk           (0x1UL << FDCAN_CCCR_CSA_Pos)             /*!< 0x00000008 */
#define FDCAN_CCCR_CSA               FDCAN_CCCR_CSA_Msk                        /*!<Clock Stop Acknowledge                   */
#define FDCAN_CCCR_CSR_Pos           (4U)
#define FDCAN_CCCR_CSR_Msk           (0x1UL << FDCAN_CCCR_CSR_Pos)             /*!< 0x00000010 */
#define FDCAN_CCCR_CSR               FDCAN_CCCR_CSR_Msk                        /*!<Clock Stop Request                       */
#define FDCAN_CCCR_MON_Pos           (5U)
#define FDCAN_CCCR_MON_Msk           (0x1UL << FDCAN_CCCR_MON_Pos)             /*!< 0x00000020 */
#define FDCAN_CCCR_MON               FDCAN_CCCR_MON_Msk                        /*!<Bus Monitoring Mode                      */
#define FDCAN_CCCR_DAR_Pos           (6U)
#define FDCAN_CCCR_DAR_Msk           (0x1UL << FDCAN_CCCR_DAR_Pos)             /*!< 0x00000040 */
#define FDCAN_CCCR_DAR               FDCAN_CCCR_DAR_Msk                        /*!<Disable Automatic Retransmission         */
#define FDCAN_CCCR_TEST_Pos          (7U)
#define FDCAN_CCCR_TEST_Msk          (0x1UL << FDCAN_CCCR_TEST_Pos)            /*!< 0x00000080 */
#define FDCAN_CCCR_TEST              FDCAN_CCCR_TEST_Msk                       /*!<Test Mode Enable                         */
#define FDCAN_CCCR_FDOE_Pos          (8U)
#define FDCAN_CCCR_FDOE_Msk          (0x1UL << FDCAN_CCCR_FDOE_Pos)            /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE              FDCAN_CCCR_FDOE_Msk                       /*!<FD Operation Enable                      */
#define FDCAN_CCCR_BRSE_Pos          (9U)
#define FDCAN_CCCR_BRSE_Msk          (0x1UL << FDCAN_CCCR_BRSE_Pos)            /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE              FDCAN_CCCR_BRSE_Msk                       /*!<FDCAN Bit Rate Switching                 */
#define FDCAN_CCCR_PXHD_Pos          (12U)
#define FDCAN_CCCR_PXHD_Msk          (0x1UL << FDCAN_CCCR_PXHD_Pos)            /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD              FDCAN_CCCR_PXHD_Msk                       /*!<Protocol Exception Handling Disable      */
#define FDCAN_CCCR_EFBI_Pos          (13U)
#define FDCAN_CCCR_EFBI_Msk          (0x1UL << FDCAN_CCCR_EFBI_Pos)            /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI              FDCAN_CCCR_EFBI_Msk                       /*!<Edge Filtering during Bus Integration    */
#define FDCAN_CCCR_TXP_Pos           (14U)
#define FDCAN_CCCR_TXP_Msk           (0x1UL << FDCAN_CCCR_TXP_Pos)             /*!< 0x00004000 */
#define FDCAN_CCCR_TXP               FDCAN_CCCR_TXP_Msk                        /*!<Two CAN bit times Pause                  */
#define FDCAN_CCCR_NISO_Pos          (15U)
#define FDCAN_CCCR_NISO_Msk          (0x1UL << FDCAN_CCCR_NISO_Pos)            /*!< 0x00008000 */
#define FDCAN_CCCR_NISO              FDCAN_CCCR_NISO_Msk                       /*!<Non ISO Operation                        */

/*****************  Bit definition for FDCAN_NBTP register  *******************/
#define FDCAN_NBTP_NTSEG2_Pos        (0U)
#define FDCAN_NBTP_NTSEG2_Msk        (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)         /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2            FDCAN_NBTP_NTSEG2_Msk                     /*!<Nominal Time segment after sample point  */
#define FDCAN_NBTP_NTSEG1_Pos        (8U)
#define FDCAN_NBTP_NTSEG1_Msk        (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)         /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1            FDCAN_NBTP_NTSEG1_Msk                     /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos          (16U)
#define FDCAN_NBTP_NBRP_Msk          (0x1FFUL << FDCAN_NBTP_NBRP_Pos)          /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP              FDCAN_NBTP_NBRP_Msk                       /*!<Bit Rate Prescaler                       */
#define FDCAN_NBTP_NSJW_Pos          (25U)
#define FDCAN_NBTP_NSJW_Msk          (0x7FUL << FDCAN_NBTP_NSJW_Pos)           /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW              FDCAN_NBTP_NSJW_Msk                       /*!<Nominal (Re)Synchronization Jump Width   */

/*****************  Bit definition for FDCAN_TSCC register  *******************/
#define FDCAN_TSCC_TSS_Pos           (0U)
#define FDCAN_TSCC_TSS_Msk           (0x3UL << FDCAN_TSCC_TSS_Pos)             /*!< 0x00000003 */
#define FDCAN_TSCC_TSS               FDCAN_TSCC_TSS_Msk                        /*!<Timestamp Select                         */
#define FDCAN_TSCC_TCP_Pos           (16U)
#define FDCAN_TSCC_TCP_Msk           (0xFUL << FDCAN_TSCC_TCP_Pos)             /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP               FDCAN_TSCC_TCP_Msk                        /*!<Timestamp Counter Prescaler              */

/*****************  Bit definition for FDCAN_TSCV register  *******************/
#define FDCAN_TSCV_TSC_Pos           (0U)
#define FDCAN_TSCV_TSC_Msk           (0xFFFFUL << FDCAN_TSCV_TSC_Pos)          /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC               FDCAN_TSCV_TSC_Msk                        /*!<Timestamp Counter                        */

/*****************  Bit definition for FDCAN_TOCC register  *******************/
#define FDCAN_TOCC_ETOC_Pos          (0U)
#define FDCAN_TOCC_ETOC_Msk          (0x1UL << FDCAN_TOCC_ETOC_Pos)            /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC              FDCAN_TOCC_ETOC_Msk                       /*!<Enable Timeout Counter                   */
#define FDCAN_TOCC_TOS_Pos           (1U)
#define FDCAN_TOCC_TOS_Msk           (0x3UL << FDCAN_TOCC_TOS_Pos)             /*!< 0x00000006 */
#define FDCAN_TOCC_TOS               FDCAN_TOCC_TOS_Msk                        /*!<Timeout Select                           */
#define FDCAN_TOCC_TOP_Pos           (16U)
#define FDCAN_TOCC_TOP_Msk           (0xFFFFUL << FDCAN_TOCC_TOP_Pos)          /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP               FDCAN_TOCC_TOP_Msk                        /*!<Timeout Period                           */

/*****************  Bit definition for FDCAN_TOCV register  *******************/
#define FDCAN_TOCV_TOC_Pos           (0U)
#define FDCAN_TOCV_TOC_Msk           (0xFFFFUL << FDCAN_TOCV_TOC_Pos)          /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC               FDCAN_TOCV_TOC_Msk                        /*!<Timeout Counter                          */

/*****************  Bit definition for FDCAN_ECR register  ********************/
#define FDCAN_ECR_TEC_Pos            (0U)
#define FDCAN_ECR_TEC_Msk            (0xFFUL << FDCAN_ECR_TEC_Pos)             /*!< 0x000000FF */
#define FDCAN_ECR_TEC                FDCAN_ECR_TEC_Msk                         /*!<Transmit Error Counter                   */
#define FDCAN_ECR_REC_Pos            (8U)
#define FDCAN_ECR_REC_Msk            (0x7FUL << FDCAN_ECR_REC_Pos)             /*!< 0x00007F00 */
#define FDCAN_ECR_REC                FDCAN_ECR_REC_Msk                         /*!<Receive Error Counter                    */
#define FDCAN_ECR_RP_Pos             (15U)
#define FDCAN_ECR_RP_Msk             (0x1UL << FDCAN_ECR_RP_Pos)               /*!< 0x00008000 */
#define FDCAN_ECR_RP                 FDCAN_ECR_RP_Msk                          /*!<Receive Error Passive                    */
#define FDCAN_ECR_CEL_Pos            (16U)
#define FDCAN_ECR_CEL_Msk            (0xFFUL << FDCAN_ECR_CEL_Pos)             /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL                FDCAN_ECR_CEL_Msk                         /*!<CAN Error Logging                        */

/*****************  Bit definition for FDCAN_PSR register  ********************/
#define FDCAN_PSR_LEC_Pos            (0U)
#define FDCAN_PSR_LEC_Msk            (0x7UL << FDCAN_PSR_LEC_Pos)              /*!< 0x00000007 */
#define FDCAN_PSR_LEC                FDCAN_PSR_LEC_Msk                         /*!<Last Error Code                          */
#define FDCAN_PSR_ACT_Pos            (3U)
#define FDCAN_PSR_ACT_Msk            (0x3UL << FDCAN_PSR_ACT_Pos)              /*!< 0x00000018 */
#define FDCAN_PSR_ACT                FDCAN_PSR_ACT_Msk                         /*!<Activity                                 */
#define FDCAN_PSR_EP_Pos             (5U)
#define FDCAN_PSR_EP_Msk             (0x1UL << FDCAN_PSR_EP_Pos)               /*!< 0x00000020 */
#define FDCAN_PSR_EP                 FDCAN_PSR_EP_Msk                          /*!<Error Passive                            */
#define FDCAN_PSR_EW_Pos             (6U)
#define FDCAN_PSR_EW_Msk             (0x1UL << FDCAN_PSR_EW_Pos)               /*!< 0x00000040 */
#define FDCAN_PSR_EW                 FDCAN_PSR_EW_Msk                          /*!<Warning Status                           */
#define FDCAN_PSR_BO_Pos             (7U)
#define FDCAN_PSR_BO_Msk             (0x1UL << FDCAN_PSR_BO_Pos)               /*!< 0x00000080 */
#define FDCAN_PSR_BO                 FDCAN_PSR_BO_Msk                          /*!<Bus_Off Status                           */
#define FDCAN_PSR_DLEC_Pos           (8U)
#define FDCAN_PSR_DLEC_Msk           (0x7UL << FDCAN_PSR_DLEC_Pos)             /*!< 0x00000700 */
#define FDCAN_PSR_DLEC               FDCAN_PSR_DLEC_Msk                        /*!<Data Last Error Code                     */
#define FDCAN_PSR_RESI_Pos           (11U)
#define FDCAN_PSR_RESI_Msk           (0x1UL << FDCAN_PSR_RESI_Pos)             /*!< 0x00000800 */
#define FDCAN_PSR_RESI               FDCAN_PSR_RESI_Msk                        /*!<ESI flag of last received FDCAN Message  */
#define FDCAN_PSR_RBRS_Pos           (12U)
#define FDCAN_PSR_RBRS_Msk           (0x1UL << FDCAN_PSR_RBRS_Pos)             /*!< 0x00001000 */
#define FDCAN_PSR_RBRS               FDCAN_PSR_RBRS_Msk                        /*!<BRS flag of last received FDCAN Message  */
#define FDCAN_PSR_REDL_Pos           (13U)
#define FDCAN_PSR_REDL_Msk           (0x1UL << FDCAN_PSR_REDL_Pos)             /*!< 0x00002000 */
#define FDCAN_PSR_REDL               FDCAN_PSR_REDL_Msk                        /*!<Received FDCAN Message                   */
#define FDCAN_PSR_PXE_Pos            (14U)
#define FDCAN_PSR_PXE_Msk            (0x1UL << FDCAN_PSR_PXE_Pos)              /*!< 0x00004000 */
#define FDCAN_PSR_PXE                FDCAN_PSR_PXE_Msk                         /*!<Protocol Exception Event                 */
#define FDCAN_PSR_TDCV_Pos           (16U)
#define FDCAN_PSR_TDCV_Msk           (0x7FUL << FDCAN_PSR_TDCV_Pos)            /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV               FDCAN_PSR_TDCV_Msk                        /*!<Transmitter Delay Compensation Value     */

/*****************  Bit definition for FDCAN_TDCR register  *******************/
#define FDCAN_TDCR_TDCF_Pos          (0U)
#define FDCAN_TDCR_TDCF_Msk          (0x7FUL << FDCAN_TDCR_TDCF_Pos)           /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF              FDCAN_TDCR_TDCF_Msk                       /*!<Transmitter Delay Compensation Filter    */
#define FDCAN_TDCR_TDCO_Pos          (8U)
#define FDCAN_TDCR_TDCO_Msk          (0x7FUL << FDCAN_TDCR_TDCO_Pos)           /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO              FDCAN_TDCR_TDCO_Msk                       /*!<Transmitter Delay Compensation Offset    */

/*****************  Bit definition for FDCAN_IR register  *********************/
#define FDCAN_IR_RF0N_Pos            (0U)
#define FDCAN_IR_RF0N_Msk            (0x1UL << FDCAN_IR_RF0N_Pos)              /*!< 0x00000001 */
#define FDCAN_IR_RF0N                FDCAN_IR_RF0N_Msk                         /*!<Rx FIFO 0 New Message                    */
#define FDCAN_IR_RF0F_Pos            (1U)
#define FDCAN_IR_RF0F_Msk            (0x1UL << FDCAN_IR_RF0F_Pos)              /*!< 0x00000002 */
#define FDCAN_IR_RF0F                FDCAN_IR_RF0F_Msk                         /*!<Rx FIFO 0 Full                           */
#define FDCAN_IR_RF0L_Pos            (2U)
#define FDCAN_IR_RF0L_Msk            (0x1UL << FDCAN_IR_RF0L_Pos)              /*!< 0x00000004 */
#define FDCAN_IR_RF0L                FDCAN_IR_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
#define FDCAN_IR_RF1N_Pos            (3U)
#define FDCAN_IR_RF1N_Msk            (0x1UL << FDCAN_IR_RF1N_Pos)              /*!< 0x00000008 */
#define FDCAN_IR_RF1N                FDCAN_IR_RF1N_Msk                         /*!<Rx FIFO 1 New Message                    */
#define FDCAN_IR_RF1F_Pos            (4U)
#define FDCAN_IR_RF1F_Msk            (0x1UL << FDCAN_IR_RF1F_Pos)              /*!< 0x00000010 */
#define FDCAN_IR_RF1F                FDCAN_IR_RF1F_Msk                         /*!<Rx FIFO 1 Full                           */
#define FDCAN_IR_RF1L_Pos            (5U)
#define FDCAN_IR_RF1L_Msk            (0x1UL << FDCAN_IR_RF1L_Pos)              /*!< 0x00000020 */
#define FDCAN_IR_RF1L                FDCAN_IR_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
#define FDCAN_IR_HPM_Pos             (6U)
#define FDCAN_IR_HPM_Msk             (0x1UL << FDCAN_IR_HPM_Pos)               /*!< 0x00000040 */
#define FDCAN_IR_HPM                 FDCAN_IR_HPM_Msk                          /*!<High Priority Message                    */
#define FDCAN_IR_TC_Pos              (7U)
#define FDCAN_IR_TC_Msk              (0x1UL << FDCAN_IR_TC_Pos)                /*!< 0x00000080 */
#define FDCAN_IR_TC                  FDCAN_IR_TC_Msk                           /*!<Transmission Completed                   */
#define FDCAN_IR_TCF_Pos             (8U)
#define FDCAN_IR_TCF_Msk             (0x1UL << FDCAN_IR_TCF_Pos)               /*!< 0x00000100 */
#define FDCAN_IR_TCF                 FDCAN_IR_TCF_Msk                          /*!<Transmission Cancellation Finished       */
#define FDCAN_IR_TFE_Pos             (9U)
#define FDCAN_IR_TFE_Msk             (0x1UL << FDCAN_IR_TFE_Pos)               /*!< 0x00000200 */
#define FDCAN_IR_TFE                 FDCAN_IR_TFE_Msk                          /*!<Tx FIFO Empty                            */
#define FDCAN_IR_TEFN_Pos            (10U)
#define FDCAN_IR_TEFN_Msk            (0x1UL << FDCAN_IR_TEFN_Pos)              /*!< 0x00000400 */
#define FDCAN_IR_TEFN                FDCAN_IR_TEFN_Msk                         /*!<Tx Event FIFO New Entry                  */
#define FDCAN_IR_TEFF_Pos            (11U)
#define FDCAN_IR_TEFF_Msk            (0x1UL << FDCAN_IR_TEFF_Pos)              /*!< 0x00000800 */
#define FDCAN_IR_TEFF                FDCAN_IR_TEFF_Msk                         /*!<Tx Event FIFO Full                       */
#define FDCAN_IR_TEFL_Pos            (12U)
#define FDCAN_IR_TEFL_Msk            (0x1UL << FDCAN_IR_TEFL_Pos)              /*!< 0x00001000 */
#define FDCAN_IR_TEFL                FDCAN_IR_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
#define FDCAN_IR_TSW_Pos             (13U)
#define FDCAN_IR_TSW_Msk             (0x1UL << FDCAN_IR_TSW_Pos)               /*!< 0x00002000 */
#define FDCAN_IR_TSW                 FDCAN_IR_TSW_Msk                          /*!<Timestamp Wraparound                     */
#define FDCAN_IR_MRAF_Pos            (14U)
#define FDCAN_IR_MRAF_Msk            (0x1UL << FDCAN_IR_MRAF_Pos)              /*!< 0x00004000 */
#define FDCAN_IR_MRAF                FDCAN_IR_MRAF_Msk                         /*!<Message RAM Access Failure               */
#define FDCAN_IR_TOO_Pos             (15U)
#define FDCAN_IR_TOO_Msk             (0x1UL << FDCAN_IR_TOO_Pos)               /*!< 0x00008000 */
#define FDCAN_IR_TOO                 FDCAN_IR_TOO_Msk                          /*!<Timeout Occurred                         */
#define FDCAN_IR_ELO_Pos             (16U)
#define FDCAN_IR_ELO_Msk             (0x1UL << FDCAN_IR_ELO_Pos)               /*!< 0x00010000 */
#define FDCAN_IR_ELO                 FDCAN_IR_ELO_Msk                          /*!<Error Logging Overflow                   */
#define FDCAN_IR_EP_Pos              (17U)
#define FDCAN_IR_EP_Msk              (0x1UL << FDCAN_IR_EP_Pos)                /*!< 0x00020000 */
#define FDCAN_IR_EP                  FDCAN_IR_EP_Msk                           /*!<Error Passive                            */
#define FDCAN_IR_EW_Pos              (18U)
#define FDCAN_IR_EW_Msk              (0x1UL << FDCAN_IR_EW_Pos)                /*!< 0x00040000 */
#define FDCAN_IR_EW                  FDCAN_IR_EW_Msk                           /*!<Warning Status                           */
#define FDCAN_IR_BO_Pos              (19U)
#define FDCAN_IR_BO_Msk              (0x1UL << FDCAN_IR_BO_Pos)                /*!< 0x00080000 */
#define FDCAN_IR_BO                  FDCAN_IR_BO_Msk                           /*!<Bus_Off Status                           */
#define FDCAN_IR_WDI_Pos             (20U)
#define FDCAN_IR_WDI_Msk             (0x1UL << FDCAN_IR_WDI_Pos)               /*!< 0x00100000 */
#define FDCAN_IR_WDI                 FDCAN_IR_WDI_Msk                          /*!<Watchdog Interrupt                       */
#define FDCAN_IR_PEA_Pos             (21U)
#define FDCAN_IR_PEA_Msk             (0x1UL << FDCAN_IR_PEA_Pos)               /*!< 0x00200000 */
#define FDCAN_IR_PEA                 FDCAN_IR_PEA_Msk                          /*!<Protocol Error in Arbitration Phase      */
#define FDCAN_IR_PED_Pos             (22U)
#define FDCAN_IR_PED_Msk             (0x1UL << FDCAN_IR_PED_Pos)               /*!< 0x00400000 */
#define FDCAN_IR_PED                 FDCAN_IR_PED_Msk                          /*!<Protocol Error in Data Phase             */
#define FDCAN_IR_ARA_Pos             (23U)
#define FDCAN_IR_ARA_Msk             (0x1UL << FDCAN_IR_ARA_Pos)               /*!< 0x00800000 */
#define FDCAN_IR_ARA                 FDCAN_IR_ARA_Msk                          /*!<Access to Reserved Address               */

/*****************  Bit definition for FDCAN_IE register  *********************/
#define FDCAN_IE_RF0NE_Pos           (0U)
#define FDCAN_IE_RF0NE_Msk           (0x1UL << FDCAN_IE_RF0NE_Pos)             /*!< 0x00000001 */
#define FDCAN_IE_RF0NE               FDCAN_IE_RF0NE_Msk                        /*!<Rx FIFO 0 New Message Enable             */
#define FDCAN_IE_RF0FE_Pos           (1U)
#define FDCAN_IE_RF0FE_Msk           (0x1UL << FDCAN_IE_RF0FE_Pos)             /*!< 0x00000002 */
#define FDCAN_IE_RF0FE               FDCAN_IE_RF0FE_Msk                        /*!<Rx FIFO 0 Full Enable                    */
#define FDCAN_IE_RF0LE_Pos           (2U)
#define FDCAN_IE_RF0LE_Msk           (0x1UL << FDCAN_IE_RF0LE_Pos)             /*!< 0x00000004 */
#define FDCAN_IE_RF0LE               FDCAN_IE_RF0LE_Msk                        /*!<Rx FIFO 0 Message Lost Enable            */
#define FDCAN_IE_RF1NE_Pos           (3U)
#define FDCAN_IE_RF1NE_Msk           (0x1UL << FDCAN_IE_RF1NE_Pos)             /*!< 0x00000008 */
#define FDCAN_IE_RF1NE               FDCAN_IE_RF1NE_Msk                        /*!<Rx FIFO 1 New Message Enable             */
#define FDCAN_IE_RF1FE_Pos           (4U)
#define FDCAN_IE_RF1FE_Msk           (0x1UL << FDCAN_IE_RF1FE_Pos)             /*!< 0x00000010 */
#define FDCAN_IE_RF1FE               FDCAN_IE_RF1FE_Msk                        /*!<Rx FIFO 1 Full Enable                    */
#define FDCAN_IE_RF1LE_Pos           (5U)
#define FDCAN_IE_RF1LE_Msk           (0x1UL << FDCAN_IE_RF1LE_Pos)             /*!< 0x00000020 */
#define FDCAN_IE_RF1LE               FDCAN_IE_RF1LE_Msk                        /*!<Rx FIFO 1 Message Lost Enable            */
#define FDCAN_IE_HPME_Pos            (6U)
#define FDCAN_IE_HPME_Msk            (0x1UL << FDCAN_IE_HPME_Pos)              /*!< 0x00000040 */
#define FDCAN_IE_HPME                FDCAN_IE_HPME_Msk                         /*!<High Priority Message Enable             */
#define FDCAN_IE_TCE_Pos             (7U)
#define FDCAN_IE_TCE_Msk             (0x1UL << FDCAN_IE_TCE_Pos)               /*!< 0x00000080 */
#define FDCAN_IE_TCE                 FDCAN_IE_TCE_Msk                          /*!<Transmission Completed Enable            */
#define FDCAN_IE_TCFE_Pos            (8U)
#define FDCAN_IE_TCFE_Msk            (0x1UL << FDCAN_IE_TCFE_Pos)              /*!< 0x00000100 */
#define FDCAN_IE_TCFE                FDCAN_IE_TCFE_Msk                         /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos            (9U)
#define FDCAN_IE_TFEE_Msk            (0x1UL << FDCAN_IE_TFEE_Pos)              /*!< 0x00000200 */
#define FDCAN_IE_TFEE                FDCAN_IE_TFEE_Msk                         /*!<Tx FIFO Empty Enable                     */
#define FDCAN_IE_TEFNE_Pos           (10U)
#define FDCAN_IE_TEFNE_Msk           (0x1UL << FDCAN_IE_TEFNE_Pos)             /*!< 0x00000400 */
#define FDCAN_IE_TEFNE               FDCAN_IE_TEFNE_Msk                        /*!<Tx Event FIFO New Entry Enable           */
#define FDCAN_IE_TEFFE_Pos           (11U)
#define FDCAN_IE_TEFFE_Msk           (0x1UL << FDCAN_IE_TEFFE_Pos)             /*!< 0x00000800 */
#define FDCAN_IE_TEFFE               FDCAN_IE_TEFFE_Msk                        /*!<Tx Event FIFO Full Enable                */
#define FDCAN_IE_TEFLE_Pos           (12U)
#define FDCAN_IE_TEFLE_Msk           (0x1UL << FDCAN_IE_TEFLE_Pos)             /*!< 0x00001000 */
#define FDCAN_IE_TEFLE               FDCAN_IE_TEFLE_Msk                        /*!<Tx Event FIFO Element Lost Enable        */
#define FDCAN_IE_TSWE_Pos            (13U)
#define FDCAN_IE_TSWE_Msk            (0x1UL << FDCAN_IE_TSWE_Pos)              /*!< 0x00002000 */
#define FDCAN_IE_TSWE                FDCAN_IE_TSWE_Msk                         /*!<Timestamp Wraparound Enable              */
#define FDCAN_IE_MRAFE_Pos           (14U)
#define FDCAN_IE_MRAFE_Msk           (0x1UL << FDCAN_IE_MRAFE_Pos)             /*!< 0x00004000 */
#define FDCAN_IE_MRAFE               FDCAN_IE_MRAFE_Msk                        /*!<Message RAM Access Failure Enable        */
#define FDCAN_IE_TOOE_Pos            (15U)
#define FDCAN_IE_TOOE_Msk            (0x1UL << FDCAN_IE_TOOE_Pos)              /*!< 0x00008000 */
#define FDCAN_IE_TOOE                FDCAN_IE_TOOE_Msk                         /*!<Timeout Occurred Enable                  */
#define FDCAN_IE_ELOE_Pos            (16U)
#define FDCAN_IE_ELOE_Msk            (0x1UL << FDCAN_IE_ELOE_Pos)              /*!< 0x00010000 */
#define FDCAN_IE_ELOE                FDCAN_IE_ELOE_Msk                         /*!<Error Logging Overflow Enable            */
#define FDCAN_IE_EPE_Pos             (17U)
#define FDCAN_IE_EPE_Msk             (0x1UL << FDCAN_IE_EPE_Pos)               /*!< 0x00020000 */
#define FDCAN_IE_EPE                 FDCAN_IE_EPE_Msk                          /*!<Error Passive Enable                     */
#define FDCAN_IE_EWE_Pos             (18U)
#define FDCAN_IE_EWE_Msk             (0x1UL << FDCAN_IE_EWE_Pos)               /*!< 0x00040000 */
#define FDCAN_IE_EWE                 FDCAN_IE_EWE_Msk                          /*!<Warning Status Enable                    */
#define FDCAN_IE_BOE_Pos             (19U)
#define FDCAN_IE_BOE_Msk             (0x1UL << FDCAN_IE_BOE_Pos)               /*!< 0x00080000 */
#define FDCAN_IE_BOE                 FDCAN_IE_BOE_Msk                          /*!<Bus_Off Status Enable                    */
#define FDCAN_IE_WDIE_Pos            (20U)
#define FDCAN_IE_WDIE_Msk            (0x1UL << FDCAN_IE_WDIE_Pos)              /*!< 0x00100000 */
#define FDCAN_IE_WDIE                FDCAN_IE_WDIE_Msk                         /*!<Watchdog Interrupt Enable                */
#define FDCAN_IE_PEAE_Pos            (21U)
#define FDCAN_IE_PEAE_Msk            (0x1UL << FDCAN_IE_PEAE_Pos)              /*!< 0x00200000 */
#define FDCAN_IE_PEAE                FDCAN_IE_PEAE_Msk                         /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos            (22U)
#define FDCAN_IE_PEDE_Msk            (0x1UL << FDCAN_IE_PEDE_Pos)              /*!< 0x00400000 */
#define FDCAN_IE_PEDE                FDCAN_IE_PEDE_Msk                         /*!<Protocol Error in Data Phase Enable      */
#define FDCAN_IE_ARAE_Pos            (23U)
#define FDCAN_IE_ARAE_Msk            (0x1UL << FDCAN_IE_ARAE_Pos)              /*!< 0x00800000 */
#define FDCAN_IE_ARAE                FDCAN_IE_ARAE_Msk                         /*!<Access to Reserved Address Enable        */

/*****************  Bit definition for FDCAN_ILS register  ********************/
#define FDCAN_ILS_RXFIFO0_Pos        (0U)
#define FDCAN_ILS_RXFIFO0_Msk        (0x1UL << FDCAN_ILS_RXFIFO0_Pos)          /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0            FDCAN_ILS_RXFIFO0_Msk                     /*!<Rx FIFO 0 Message Lost
                                                                                        Rx FIFO 0 is Full
                                                                                        Rx FIFO 0 Has New Message                */
#define FDCAN_ILS_RXFIFO1_Pos        (1U)
#define FDCAN_ILS_RXFIFO1_Msk        (0x1UL << FDCAN_ILS_RXFIFO1_Pos)          /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1            FDCAN_ILS_RXFIFO1_Msk                     /*!<Rx FIFO 1 Message Lost
                                                                                        Rx FIFO 1 is Full
                                                                                        Rx FIFO 1 Has New Message                */
#define FDCAN_ILS_SMSG_Pos           (2U)
#define FDCAN_ILS_SMSG_Msk           (0x1UL << FDCAN_ILS_SMSG_Pos)             /*!< 0x00000004 */
#define FDCAN_ILS_SMSG               FDCAN_ILS_SMSG_Msk                        /*!<Transmission Cancellation Finished
                                                                                        Transmission Completed
                                                                                        High Priority Message                    */
#define FDCAN_ILS_TFERR_Pos          (3U)
#define FDCAN_ILS_TFERR_Msk          (0x1UL << FDCAN_ILS_TFERR_Pos)            /*!< 0x00000008 */
#define FDCAN_ILS_TFERR              FDCAN_ILS_TFERR_Msk                       /*!<Tx Event FIFO Element Lost
                                                                                        Tx Event FIFO Full
                                                                                        Tx Event FIFO New Entry
                                                                                        Tx FIFO Empty Interrupt Line             */
#define FDCAN_ILS_MISC_Pos           (4U)
#define FDCAN_ILS_MISC_Msk           (0x1UL << FDCAN_ILS_MISC_Pos)             /*!< 0x00000010 */
#define FDCAN_ILS_MISC               FDCAN_ILS_MISC_Msk                        /*!<Timeout Occurred
                                                                                        Message RAM Access Failure
                                                                                        Timestamp Wraparound                    */
#define FDCAN_ILS_BERR_Pos           (5U)
#define FDCAN_ILS_BERR_Msk           (0x1UL << FDCAN_ILS_BERR_Pos)             /*!< 0x00000020 */
#define FDCAN_ILS_BERR               FDCAN_ILS_BERR_Msk                        /*!<Error Passive
                                                                                        Error Logging Overflow                   */
#define FDCAN_ILS_PERR_Pos           (6U)
#define FDCAN_ILS_PERR_Msk           (0x1UL << FDCAN_ILS_PERR_Pos)             /*!< 0x00000040 */
#define FDCAN_ILS_PERR               FDCAN_ILS_PERR_Msk                        /*!<Access to Reserved Address Line
                                                                                        Protocol Error in Data Phase Line
                                                                                        Protocol Error in Arbitration Phase Line
                                                                                        Watchdog Interrupt Line
                                                                                        Bus_Off Status
                                                                                        Warning Status                           */

/*****************  Bit definition for FDCAN_ILE register  ********************/
#define FDCAN_ILE_EINT0_Pos          (0U)
#define FDCAN_ILE_EINT0_Msk          (0x1UL << FDCAN_ILE_EINT0_Pos)            /*!< 0x00000001 */
#define FDCAN_ILE_EINT0              FDCAN_ILE_EINT0_Msk                       /*!<Enable Interrupt Line 0                  */
#define FDCAN_ILE_EINT1_Pos          (1U)
#define FDCAN_ILE_EINT1_Msk          (0x1UL << FDCAN_ILE_EINT1_Pos)            /*!< 0x00000002 */
#define FDCAN_ILE_EINT1              FDCAN_ILE_EINT1_Msk                       /*!<Enable Interrupt Line 1                  */

/*****************  Bit definition for FDCAN_RXGFC register  ******************/
#define FDCAN_RXGFC_RRFE_Pos         (0U)
#define FDCAN_RXGFC_RRFE_Msk         (0x1UL << FDCAN_RXGFC_RRFE_Pos)           /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE             FDCAN_RXGFC_RRFE_Msk                      /*!<Reject Remote Frames Extended            */
#define FDCAN_RXGFC_RRFS_Pos         (1U)
#define FDCAN_RXGFC_RRFS_Msk         (0x1UL << FDCAN_RXGFC_RRFS_Pos)           /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS             FDCAN_RXGFC_RRFS_Msk                      /*!<Reject Remote Frames Standard            */
#define FDCAN_RXGFC_ANFE_Pos         (2U)
#define FDCAN_RXGFC_ANFE_Msk         (0x3UL << FDCAN_RXGFC_ANFE_Pos)           /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE             FDCAN_RXGFC_ANFE_Msk                      /*!<Accept Non-matching Frames Extended      */
#define FDCAN_RXGFC_ANFS_Pos         (4U)
#define FDCAN_RXGFC_ANFS_Msk         (0x3UL << FDCAN_RXGFC_ANFS_Pos)           /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS             FDCAN_RXGFC_ANFS_Msk                      /*!<Accept Non-matching Frames Standard      */
#define FDCAN_RXGFC_F1OM_Pos         (8U)
#define FDCAN_RXGFC_F1OM_Msk         (0x1UL << FDCAN_RXGFC_F1OM_Pos)           /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM             FDCAN_RXGFC_F1OM_Msk                      /*!<FIFO 1 operation mode                    */
#define FDCAN_RXGFC_F0OM_Pos         (9U)
#define FDCAN_RXGFC_F0OM_Msk         (0x1UL << FDCAN_RXGFC_F0OM_Pos)           /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM             FDCAN_RXGFC_F0OM_Msk                      /*!<FIFO 0 operation mode                    */
#define FDCAN_RXGFC_LSS_Pos          (16U)
#define FDCAN_RXGFC_LSS_Msk          (0x1FUL << FDCAN_RXGFC_LSS_Pos)           /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS              FDCAN_RXGFC_LSS_Msk                       /*!<List Size Standard                       */
#define FDCAN_RXGFC_LSE_Pos          (24U)
#define FDCAN_RXGFC_LSE_Msk          (0xFUL << FDCAN_RXGFC_LSE_Pos)            /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE              FDCAN_RXGFC_LSE_Msk                       /*!<List Size Extended                       */

/*****************  Bit definition for FDCAN_XIDAM register  ******************/
#define FDCAN_XIDAM_EIDM_Pos         (0U)
#define FDCAN_XIDAM_EIDM_Msk         (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)    /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM             FDCAN_XIDAM_EIDM_Msk                      /*!<Extended ID Mask                         */

/*****************  Bit definition for FDCAN_HPMS register  *******************/
#define FDCAN_HPMS_BIDX_Pos          (0U)
#define FDCAN_HPMS_BIDX_Msk          (0x7UL << FDCAN_HPMS_BIDX_Pos)            /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX              FDCAN_HPMS_BIDX_Msk                       /*!<Buffer Index                             */
#define FDCAN_HPMS_MSI_Pos           (6U)
#define FDCAN_HPMS_MSI_Msk           (0x3UL << FDCAN_HPMS_MSI_Pos)             /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI               FDCAN_HPMS_MSI_Msk                        /*!<Message Storage Indicator                */
#define FDCAN_HPMS_FIDX_Pos          (8U)
#define FDCAN_HPMS_FIDX_Msk          (0x1FUL << FDCAN_HPMS_FIDX_Pos)           /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX              FDCAN_HPMS_FIDX_Msk                       /*!<Filter Index                             */
#define FDCAN_HPMS_FLST_Pos          (15U)
#define FDCAN_HPMS_FLST_Msk          (0x1UL << FDCAN_HPMS_FLST_Pos)            /*!< 0x00008000 */
#define FDCAN_HPMS_FLST              FDCAN_HPMS_FLST_Msk                       /*!<Filter List                              */

/*****************  Bit definition for FDCAN_RXF0S register  ******************/
#define FDCAN_RXF0S_F0FL_Pos         (0U)
#define FDCAN_RXF0S_F0FL_Msk         (0xFUL << FDCAN_RXF0S_F0FL_Pos)           /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL             FDCAN_RXF0S_F0FL_Msk                      /*!<Rx FIFO 0 Fill Level                     */
#define FDCAN_RXF0S_F0GI_Pos         (8U)
#define FDCAN_RXF0S_F0GI_Msk         (0x3UL << FDCAN_RXF0S_F0GI_Pos)           /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI             FDCAN_RXF0S_F0GI_Msk                      /*!<Rx FIFO 0 Get Index                      */
#define FDCAN_RXF0S_F0PI_Pos         (16U)
#define FDCAN_RXF0S_F0PI_Msk         (0x3UL << FDCAN_RXF0S_F0PI_Pos)           /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI             FDCAN_RXF0S_F0PI_Msk                      /*!<Rx FIFO 0 Put Index                      */
#define FDCAN_RXF0S_F0F_Pos          (24U)
#define FDCAN_RXF0S_F0F_Msk          (0x1UL << FDCAN_RXF0S_F0F_Pos)            /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F              FDCAN_RXF0S_F0F_Msk                       /*!<Rx FIFO 0 Full                           */
#define FDCAN_RXF0S_RF0L_Pos         (25U)
#define FDCAN_RXF0S_RF0L_Msk         (0x1UL << FDCAN_RXF0S_RF0L_Pos)           /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L             FDCAN_RXF0S_RF0L_Msk                      /*!<Rx FIFO 0 Message Lost                   */

/*****************  Bit definition for FDCAN_RXF0A register  ******************/
#define FDCAN_RXF0A_F0AI_Pos         (0U)
#define FDCAN_RXF0A_F0AI_Msk         (0x7UL << FDCAN_RXF0A_F0AI_Pos)           /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI             FDCAN_RXF0A_F0AI_Msk                      /*!<Rx FIFO 0 Acknowledge Index              */

/*****************  Bit definition for FDCAN_RXF1S register  ******************/
#define FDCAN_RXF1S_F1FL_Pos         (0U)
#define FDCAN_RXF1S_F1FL_Msk         (0xFUL << FDCAN_RXF1S_F1FL_Pos)           /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL             FDCAN_RXF1S_F1FL_Msk                      /*!<Rx FIFO 1 Fill Level                     */
#define FDCAN_RXF1S_F1GI_Pos         (8U)
#define FDCAN_RXF1S_F1GI_Msk         (0x3UL << FDCAN_RXF1S_F1GI_Pos)           /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI             FDCAN_RXF1S_F1GI_Msk                      /*!<Rx FIFO 1 Get Index                      */
#define FDCAN_RXF1S_F1PI_Pos         (16U)
#define FDCAN_RXF1S_F1PI_Msk         (0x3UL << FDCAN_RXF1S_F1PI_Pos)           /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI             FDCAN_RXF1S_F1PI_Msk                      /*!<Rx FIFO 1 Put Index                      */
#define FDCAN_RXF1S_F1F_Pos          (24U)
#define FDCAN_RXF1S_F1F_Msk          (0x1UL << FDCAN_RXF1S_F1F_Pos)            /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F              FDCAN_RXF1S_F1F_Msk                       /*!<Rx FIFO 1 Full                           */
#define FDCAN_RXF1S_RF1L_Pos         (25U)
#define FDCAN_RXF1S_RF1L_Msk         (0x1UL << FDCAN_RXF1S_RF1L_Pos)           /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L             FDCAN_RXF1S_RF1L_Msk                      /*!<Rx FIFO 1 Message Lost                   */

/*****************  Bit definition for FDCAN_RXF1A register  ******************/
#define FDCAN_RXF1A_F1AI_Pos         (0U)
#define FDCAN_RXF1A_F1AI_Msk         (0x7UL << FDCAN_RXF1A_F1AI_Pos)           /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI             FDCAN_RXF1A_F1AI_Msk                      /*!<Rx FIFO 1 Acknowledge Index              */

/*****************  Bit definition for FDCAN_TXBC register  *******************/
#define FDCAN_TXBC_TFQM_Pos          (24U)
#define FDCAN_TXBC_TFQM_Msk          (0x1UL << FDCAN_TXBC_TFQM_Pos)            /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM              FDCAN_TXBC_TFQM_Msk                       /*!<Tx FIFO/Queue Mode                       */

/*****************  Bit definition for FDCAN_TXFQS register  ******************/
#define FDCAN_TXFQS_TFFL_Pos         (0U)
#define FDCAN_TXFQS_TFFL_Msk         (0x7UL << FDCAN_TXFQS_TFFL_Pos)           /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL             FDCAN_TXFQS_TFFL_Msk                      /*!<Tx FIFO Free Level                       */
#define FDCAN_TXFQS_TFGI_Pos         (8U)
#define FDCAN_TXFQS_TFGI_Msk         (0x3UL << FDCAN_TXFQS_TFGI_Pos)           /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI             FDCAN_TXFQS_TFGI_Msk                      /*!<Tx FIFO Get Index                        */
#define FDCAN_TXFQS_TFQPI_Pos        (16U)
#define FDCAN_TXFQS_TFQPI_Msk        (0x3UL << FDCAN_TXFQS_TFQPI_Pos)          /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI            FDCAN_TXFQS_TFQPI_Msk                     /*!<Tx FIFO/Queue Put Index                  */
#define FDCAN_TXFQS_TFQF_Pos         (21U)
#define FDCAN_TXFQS_TFQF_Msk         (0x1UL << FDCAN_TXFQS_TFQF_Pos)           /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF             FDCAN_TXFQS_TFQF_Msk                      /*!<Tx FIFO/Queue Full                       */

/*****************  Bit definition for FDCAN_TXBRP register  ******************/
#define FDCAN_TXBRP_TRP_Pos          (0U)
#define FDCAN_TXBRP_TRP_Msk          (0x7UL << FDCAN_TXBRP_TRP_Pos)            /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP              FDCAN_TXBRP_TRP_Msk                       /*!<Transmission Request Pending             */

/*****************  Bit definition for FDCAN_TXBAR register  ******************/
#define FDCAN_TXBAR_AR_Pos           (0U)
#define FDCAN_TXBAR_AR_Msk           (0x7UL << FDCAN_TXBAR_AR_Pos)             /*!< 0x00000007 */
#define FDCAN_TXBAR_AR               FDCAN_TXBAR_AR_Msk                        /*!<Add Request                              */

/*****************  Bit definition for FDCAN_TXBCR register  ******************/
#define FDCAN_TXBCR_CR_Pos           (0U)
#define FDCAN_TXBCR_CR_Msk           (0x7UL << FDCAN_TXBCR_CR_Pos)             /*!< 0x00000007 */
#define FDCAN_TXBCR_CR               FDCAN_TXBCR_CR_Msk                        /*!<Cancellation Request                     */

/*****************  Bit definition for FDCAN_TXBTO register  ******************/
#define FDCAN_TXBTO_TO_Pos           (0U)
#define FDCAN_TXBTO_TO_Msk           (0x7UL << FDCAN_TXBTO_TO_Pos)             /*!< 0x00000007 */
#define FDCAN_TXBTO_TO               FDCAN_TXBTO_TO_Msk                        /*!<Transmission Occurred                    */

/*****************  Bit definition for FDCAN_TXBCF register  ******************/
#define FDCAN_TXBCF_CF_Pos           (0U)
#define FDCAN_TXBCF_CF_Msk           (0x7UL << FDCAN_TXBCF_CF_Pos)             /*!< 0x00000007 */
#define FDCAN_TXBCF_CF               FDCAN_TXBCF_CF_Msk                        /*!<Cancellation Finished                    */

/*****************  Bit definition for FDCAN_TXBTIE register  *****************/
#define FDCAN_TXBTIE_TIE_Pos         (0U)
#define FDCAN_TXBTIE_TIE_Msk         (0x7UL << FDCAN_TXBTIE_TIE_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE             FDCAN_TXBTIE_TIE_Msk                      /*!<Transmission Interrupt Enable            */

/*****************  Bit definition for FDCAN_ TXBCIE register  ****************/
#define FDCAN_TXBCIE_CFIE_Pos        (0U)
#define FDCAN_TXBCIE_CFIE_Msk        (0x7UL << FDCAN_TXBCIE_CFIE_Pos)          /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE            FDCAN_TXBCIE_CFIE_Msk                     /*!<Cancellation Finished Interrupt Enable   */

/*****************  Bit definition for FDCAN_TXEFS register  ******************/
#define FDCAN_TXEFS_EFFL_Pos         (0U)
#define FDCAN_TXEFS_EFFL_Msk         (0x7UL << FDCAN_TXEFS_EFFL_Pos)           /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL             FDCAN_TXEFS_EFFL_Msk                      /*!<Event FIFO Fill Level                    */
#define FDCAN_TXEFS_EFGI_Pos         (8U)
#define FDCAN_TXEFS_EFGI_Msk         (0x3UL << FDCAN_TXEFS_EFGI_Pos)           /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI             FDCAN_TXEFS_EFGI_Msk                      /*!<Event FIFO Get Index                     */
#define FDCAN_TXEFS_EFPI_Pos         (16U)
#define FDCAN_TXEFS_EFPI_Msk         (0x3UL << FDCAN_TXEFS_EFPI_Pos)           /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI             FDCAN_TXEFS_EFPI_Msk                      /*!<Event FIFO Put Index                     */
#define FDCAN_TXEFS_EFF_Pos          (24U)
#define FDCAN_TXEFS_EFF_Msk          (0x1UL << FDCAN_TXEFS_EFF_Pos)            /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF              FDCAN_TXEFS_EFF_Msk                       /*!<Event FIFO Full                          */
#define FDCAN_TXEFS_TEFL_Pos         (25U)
#define FDCAN_TXEFS_TEFL_Msk         (0x1UL << FDCAN_TXEFS_TEFL_Pos)           /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL             FDCAN_TXEFS_TEFL_Msk                      /*!<Tx Event FIFO Element Lost               */

/*****************  Bit definition for FDCAN_TXEFA register  ******************/
#define FDCAN_TXEFA_EFAI_Pos         (0U)
#define FDCAN_TXEFA_EFAI_Msk         (0x3UL << FDCAN_TXEFA_EFAI_Pos)           /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI             FDCAN_TXEFA_EFAI_Msk                      /*!<Event FIFO Acknowledge Index             */

  /*!<FDCAN config registers */
/*****************  Bit definition for FDCAN_CKDIV register  ******************/
#define FDCAN_CKDIV_PDIV_Pos         (0U)
#define FDCAN_CKDIV_PDIV_Msk         (0xFUL << FDCAN_CKDIV_PDIV_Pos)           /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV             FDCAN_CKDIV_PDIV_Msk                      /*!<Input Clock Divider                      */


/******************************************************************************/
/*                                                                            */
/*                                    FLASH                                   */
/*                                                                            */
/******************************************************************************/
#define FLASH_LATENCY_DEFAULT                (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /* default flash latency 3WS ) */

/*******************  Bits definition for FLASH_ACR register  *****************/
#define FLASH_ACR_LATENCY_Pos                (0U)
#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)                    /*!< 0x0000000F */
#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk                               /*!< Read Latency */
#define FLASH_ACR_LATENCY_0                  (0x1UL << FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000001 */
#define FLASH_ACR_LATENCY_1                  (0x2UL << FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000002 */
#define FLASH_ACR_LATENCY_2                  (0x4UL << FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000004 */
#define FLASH_ACR_LATENCY_3                  (0x8UL << FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000008 */
#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)                 /*!< 0x00000030 */
#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk                            /*!< Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)                 /*!< 0x00000010 */
#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)                 /*!< 0x00000020 */

/******************  Bits definition for FLASH_KEYR register  *****************/
#define FLASH_KEYR_CUKEY_Pos                 (0U)
#define FLASH_KEYR_CUKEY_Msk                 (0xFFFFFFFFUL << FLASH_KEYR_CUKEY_Pos)              /*!< 0xFFFFFFFF */
#define FLASH_KEYR_CUKEY                     FLASH_KEYR_CUKEY_Msk                                /*!< Control unlock key */

/*******************  Bits definition for FLASH_CR register  ******************/
#define FLASH_CR_LOCK_Pos                    (0U)
#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)                        /*!< 0x00000001 */
#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                                   /*!< Configuration lock bit */
#define FLASH_CR_PG_Pos                      (1U)
#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)                          /*!< 0x00000002 */
#define FLASH_CR_PG                          FLASH_CR_PG_Msk                                     /*!< Internal buffer control bit */
#define FLASH_CR_SER_Pos                     (2U)
#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)                         /*!< 0x00000004 */
#define FLASH_CR_SER                         FLASH_CR_SER_Msk                                    /*!< Sector erase request */
#define FLASH_CR_BER_Pos                     (3U)
#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)                         /*!< 0x00000008 */
#define FLASH_CR_BER                         FLASH_CR_BER_Msk                                    /*!< Bank erase request */
#define FLASH_CR_FW_Pos                      (4U)
#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)                          /*!< 0x00000010 */
#define FLASH_CR_FW                          FLASH_CR_FW_Msk                                     /*!< Force write */
#define FLASH_CR_START_Pos                   (5U)
#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)                       /*!< 0x00000020 */
#define FLASH_CR_START                       FLASH_CR_START_Msk                                  /*!< Erase start control bit */
#define FLASH_CR_SSN_Pos                     (6U)
#define FLASH_CR_SSN_Msk                     (0x7UL << FLASH_CR_SSN_Pos)                         /*!< 0x000001C0 */
#define FLASH_CR_SSN                         FLASH_CR_SSN_Msk                                    /*!< Sector erase selection number */
#define FLASH_CR_SSN_0                       (0x1UL << FLASH_CR_SSN_Pos)                         /*!< 0x00000040 */
#define FLASH_CR_SSN_1                       (0x2UL << FLASH_CR_SSN_Pos)                         /*!< 0x00000080 */
#define FLASH_CR_SSN_2                       (0x4UL << FLASH_CR_SSN_Pos)                         /*!< 0x00000100 */
#define FLASH_CR_PG_OTP_Pos                  (16U)
#define FLASH_CR_PG_OTP_Msk                  (0x1UL << FLASH_CR_PG_OTP_Pos)                      /*!< 0x00010000 */
#define FLASH_CR_PG_OTP                      FLASH_CR_PG_OTP_Msk                                 /*!< Program Enable for OTP Area */
#define FLASH_CR_CRC_EN_Pos                  (17U)
#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)                      /*!< 0x00020000 */
#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk                                 /*!< CRC enable */
#define FLASH_CR_ALL_BANKS_Pos               (24U)
#define FLASH_CR_ALL_BANKS_Msk               (0x1UL << FLASH_CR_ALL_BANKS_Pos)                   /*!< 0x01000000 */
#define FLASH_CR_ALL_BANKS                   FLASH_CR_ALL_BANKS_Msk                              /*!< All banks select bit */

/*******************  Bits definition for FLASH_SR register  ******************/
#define FLASH_SR_BUSY_Pos                    (0U)
#define FLASH_SR_BUSY_Msk                    (0x1UL << FLASH_SR_BUSY_Pos)                        /*!< 0x00000001 */
#define FLASH_SR_BUSY                        FLASH_SR_BUSY_Msk                                   /*!< Busy flag */
#define FLASH_SR_WBNE_Pos                    (1U)
#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)                        /*!< 0x00000002 */
#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                                   /*!< Write buffer not empty flag */
#define FLASH_SR_QW_Pos                      (2U)
#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)                          /*!< 0x00000004 */
#define FLASH_SR_QW                          FLASH_SR_QW_Msk                                     /*!< Wait queue flag */
#define FLASH_SR_CRC_BUSY_Pos                (3U)
#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)                    /*!< 0x00000008 */
#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk                               /*!< CRC busy flag */
#define FLASH_SR_IS_PROGRAM_Pos              (4U)
#define FLASH_SR_IS_PROGRAM_Msk              (0x1UL << FLASH_SR_IS_PROGRAM_Pos)                  /*!< 0x00000010 */
#define FLASH_SR_IS_PROGRAM                  FLASH_SR_IS_PROGRAM_Msk                             /*!< Is program */
#define FLASH_SR_IS_ERASE_Pos                (5U)
#define FLASH_SR_IS_ERASE_Msk                (0x1UL << FLASH_SR_IS_ERASE_Pos)                    /*!< 0x00000020 */
#define FLASH_SR_IS_ERASE                    FLASH_SR_IS_ERASE_Msk                               /*!< Is an erase */
#define FLASH_SR_IS_OPTCHANGE_Pos            (6U)
#define FLASH_SR_IS_OPTCHANGE_Msk            (0x1UL << FLASH_SR_IS_OPTCHANGE_Pos)                /*!< 0x00000040 */
#define FLASH_SR_IS_OPTCHANGE                FLASH_SR_IS_OPTCHANGE_Msk                           /*!< Is an option change */

/******************  Bits definition for FLASH_IER register  ******************/
#define FLASH_IER_EOPIE_Pos                  (16U)
#define FLASH_IER_EOPIE_Msk                  (0x1UL << FLASH_IER_EOPIE_Pos)                      /*!< 0x00010000 */
#define FLASH_IER_EOPIE                      FLASH_IER_EOPIE_Msk                                 /*!< End of program interrupt enable bit */
#define FLASH_IER_WRPERRIE_Pos               (17U)
#define FLASH_IER_WRPERRIE_Msk               (0x1UL << FLASH_IER_WRPERRIE_Pos)                   /*!< 0x00020000 */
#define FLASH_IER_WRPERRIE                   FLASH_IER_WRPERRIE_Msk                              /*!< Write protection error interrupt enable bit */
#define FLASH_IER_PGSERRIE_Pos               (18U)
#define FLASH_IER_PGSERRIE_Msk               (0x1UL << FLASH_IER_PGSERRIE_Pos)                   /*!< 0x00040000 */
#define FLASH_IER_PGSERRIE                   FLASH_IER_PGSERRIE_Msk                              /*!< Programming sequence error interrupt enable bit */
#define FLASH_IER_STRBERRIE_Pos              (19U)
#define FLASH_IER_STRBERRIE_Msk              (0x1UL << FLASH_IER_STRBERRIE_Pos)                  /*!< 0x00080000 */
#define FLASH_IER_STRBERRIE                  FLASH_IER_STRBERRIE_Msk                             /*!< Strobe error interrupt enable bit */
#define FLASH_IER_OBLERRIE_Pos               (20U)
#define FLASH_IER_OBLERRIE_Msk               (0x1UL << FLASH_IER_OBLERRIE_Pos)                   /*!< 0x00100000 */
#define FLASH_IER_OBLERRIE                   FLASH_IER_OBLERRIE_Msk                              /*!< Option byte loading error interrupt enable bit */
#define FLASH_IER_INCERRIE_Pos               (21U)
#define FLASH_IER_INCERRIE_Msk               (0x1UL << FLASH_IER_INCERRIE_Pos)                   /*!< 0x00200000 */
#define FLASH_IER_INCERRIE                   FLASH_IER_INCERRIE_Msk                              /*!< Inconsistency error interrupt enable bit */
#define FLASH_IER_RDSERRIE_Pos               (24U)
#define FLASH_IER_RDSERRIE_Msk               (0x1UL << FLASH_IER_RDSERRIE_Pos)                   /*!< 0x01000000 */
#define FLASH_IER_RDSERRIE                   FLASH_IER_RDSERRIE_Msk                              /*!< Read security error interrupt enable bit */
#define FLASH_IER_SNECCERRIE_Pos             (25U)
#define FLASH_IER_SNECCERRIE_Msk             (0x1UL << FLASH_IER_SNECCERRIE_Pos)                 /*!< 0x02000000 */
#define FLASH_IER_SNECCERRIE                 FLASH_IER_SNECCERRIE_Msk                            /*!< ECC single correction error interrupt enable bit */
#define FLASH_IER_DBECCERRIE_Pos             (26U)
#define FLASH_IER_DBECCERRIE_Msk             (0x1UL << FLASH_IER_DBECCERRIE_Pos)                 /*!< 0x04000000 */
#define FLASH_IER_DBECCERRIE                 FLASH_IER_DBECCERRIE_Msk                            /*!< ECC double detection error interrupt enable bit */
#define FLASH_IER_CRCENDIE_Pos               (27U)
#define FLASH_IER_CRCENDIE_Msk               (0x1UL << FLASH_IER_CRCENDIE_Pos)                   /*!< 0x08000000 */
#define FLASH_IER_CRCENDIE                   FLASH_IER_CRCENDIE_Msk                              /*!< CRC end of calculation interrupt enable bit */
#define FLASH_IER_CRCRDERRIE_Pos             (28U)
#define FLASH_IER_CRCRDERRIE_Msk             (0x1UL << FLASH_IER_CRCRDERRIE_Pos)                 /*!< 0x10000000 */
#define FLASH_IER_CRCRDERRIE                 FLASH_IER_CRCRDERRIE_Msk                            /*!< CRC read error interrupt enable bit */

/******************  Bits definition for FLASH_ISR register  ******************/
#define FLASH_ISR_EOPF_Pos                   (16U)
#define FLASH_ISR_EOPF_Msk                   (0x1UL << FLASH_ISR_EOPF_Pos)                       /*!< 0x00010000 */
#define FLASH_ISR_EOPF                       FLASH_ISR_EOPF_Msk                                  /*!< End of program flag */
#define FLASH_ISR_WRPERRF_Pos                (17U)
#define FLASH_ISR_WRPERRF_Msk                (0x1UL << FLASH_ISR_WRPERRF_Pos)                    /*!< 0x00020000 */
#define FLASH_ISR_WRPERRF                    FLASH_ISR_WRPERRF_Msk                               /*!< Write protection error flag */
#define FLASH_ISR_PGSERRF_Pos                (18U)
#define FLASH_ISR_PGSERRF_Msk                (0x1UL << FLASH_ISR_PGSERRF_Pos)                    /*!< 0x00040000 */
#define FLASH_ISR_PGSERRF                    FLASH_ISR_PGSERRF_Msk                               /*!< Programming sequence error flag */
#define FLASH_ISR_STRBERRF_Pos               (19U)
#define FLASH_ISR_STRBERRF_Msk               (0x1UL << FLASH_ISR_STRBERRF_Pos)                   /*!< 0x00080000 */
#define FLASH_ISR_STRBERRF                   FLASH_ISR_STRBERRF_Msk                              /*!< Strobe error flag */
#define FLASH_ISR_OBLERRF_Pos                (20U)
#define FLASH_ISR_OBLERRF_Msk                (0x1UL << FLASH_ISR_OBLERRF_Pos)                    /*!< 0x00100000 */
#define FLASH_ISR_OBLERRF                    FLASH_ISR_OBLERRF_Msk                               /*!< Option byte loading error flag */
#define FLASH_ISR_INCERRF_Pos                (21U)
#define FLASH_ISR_INCERRF_Msk                (0x1UL << FLASH_ISR_INCERRF_Pos)                    /*!< 0x00200000 */
#define FLASH_ISR_INCERRF                    FLASH_ISR_INCERRF_Msk                               /*!< Inconsistency error flag */
#define FLASH_ISR_RDSERRF_Pos                (24U)
#define FLASH_ISR_RDSERRF_Msk                (0x1UL << FLASH_ISR_RDSERRF_Pos)                    /*!< 0x01000000 */
#define FLASH_ISR_RDSERRF                    FLASH_ISR_RDSERRF_Msk                               /*!< Read security error flag */
#define FLASH_ISR_SNECCERRF_Pos              (25U)
#define FLASH_ISR_SNECCERRF_Msk              (0x1UL << FLASH_ISR_SNECCERRF_Pos)                  /*!< 0x02000000 */
#define FLASH_ISR_SNECCERRF                  FLASH_ISR_SNECCERRF_Msk                             /*!< ECC single error flag */
#define FLASH_ISR_DBECCERRF_Pos              (26U)
#define FLASH_ISR_DBECCERRF_Msk              (0x1UL << FLASH_ISR_DBECCERRF_Pos)                  /*!< 0x04000000 */
#define FLASH_ISR_DBECCERRF                  FLASH_ISR_DBECCERRF_Msk                             /*!< ECC double error flag */
#define FLASH_ISR_CRCENDF_Pos                (27U)
#define FLASH_ISR_CRCENDF_Msk                (0x1UL << FLASH_ISR_CRCENDF_Pos)                    /*!< 0x08000000 */
#define FLASH_ISR_CRCENDF                    FLASH_ISR_CRCENDF_Msk                               /*!< CRC end of calculation flag */
#define FLASH_ISR_CRCRDERRF_Pos              (28U)
#define FLASH_ISR_CRCRDERRF_Msk              (0x1UL << FLASH_ISR_CRCRDERRF_Pos)                  /*!< 0x10000000 */
#define FLASH_ISR_CRCRDERRF                  FLASH_ISR_CRCRDERRF_Msk                             /*!< CRC read error flag */

/******************  Bits definition for FLASH_ICR register  ******************/
#define FLASH_ICR_EOPF_Pos                   (16U)
#define FLASH_ICR_EOPF_Msk                   (0x1UL << FLASH_ICR_EOPF_Pos)                       /*!< 0x00010000 */
#define FLASH_ICR_EOPF                       FLASH_ICR_EOPF_Msk                                  /*!< End of program flag clear */
#define FLASH_ICR_WRPERRF_Pos                (17U)
#define FLASH_ICR_WRPERRF_Msk                (0x1UL << FLASH_ICR_WRPERRF_Pos)                    /*!< 0x00020000 */
#define FLASH_ICR_WRPERRF                    FLASH_ICR_WRPERRF_Msk                               /*!< Write protection error flag clear */
#define FLASH_ICR_PGSERRF_Pos                (18U)
#define FLASH_ICR_PGSERRF_Msk                (0x1UL << FLASH_ICR_PGSERRF_Pos)                    /*!< 0x00040000 */
#define FLASH_ICR_PGSERRF                    FLASH_ICR_PGSERRF_Msk                               /*!< Programming sequence error flag clear */
#define FLASH_ICR_STRBERRF_Pos               (19U)
#define FLASH_ICR_STRBERRF_Msk               (0x1UL << FLASH_ICR_STRBERRF_Pos)                   /*!< 0x00080000 */
#define FLASH_ICR_STRBERRF                   FLASH_ICR_STRBERRF_Msk                              /*!< Strobe error flag clear */
#define FLASH_ICR_OBLERRF_Pos                (20U)
#define FLASH_ICR_OBLERRF_Msk                (0x1UL << FLASH_ICR_OBLERRF_Pos)                    /*!< 0x00100000 */
#define FLASH_ICR_OBLERRF                    FLASH_ICR_OBLERRF_Msk                               /*!< Option byte loading error flag clear */
#define FLASH_ICR_INCERRF_Pos                (21U)
#define FLASH_ICR_INCERRF_Msk                (0x1UL << FLASH_ICR_INCERRF_Pos)                    /*!< 0x00200000 */
#define FLASH_ICR_INCERRF                    FLASH_ICR_INCERRF_Msk                               /*!< Inconsistency error flag clear */
#define FLASH_ICR_RDSERRF_Pos                (24U)
#define FLASH_ICR_RDSERRF_Msk                (0x1UL << FLASH_ICR_RDSERRF_Pos)                    /*!< 0x01000000 */
#define FLASH_ICR_RDSERRF                    FLASH_ICR_RDSERRF_Msk                               /*!< Read security error flag clear */
#define FLASH_ICR_SNECCERRF_Pos              (25U)
#define FLASH_ICR_SNECCERRF_Msk              (0x1UL << FLASH_ICR_SNECCERRF_Pos)                  /*!< 0x02000000 */
#define FLASH_ICR_SNECCERRF                  FLASH_ICR_SNECCERRF_Msk                             /*!< ECC single error flag clear */
#define FLASH_ICR_DBECCERRF_Pos              (26U)
#define FLASH_ICR_DBECCERRF_Msk              (0x1UL << FLASH_ICR_DBECCERRF_Pos)                  /*!< 0x04000000 */
#define FLASH_ICR_DBECCERRF                  FLASH_ICR_DBECCERRF_Msk                             /*!< ECC double error flag clear */
#define FLASH_ICR_CRCENDF_Pos                (27U)
#define FLASH_ICR_CRCENDF_Msk                (0x1UL << FLASH_ICR_CRCENDF_Pos)                    /*!< 0x08000000 */
#define FLASH_ICR_CRCENDF                    FLASH_ICR_CRCENDF_Msk                               /*!< CRC end flag clear */
#define FLASH_ICR_CRCRDERRF_Pos              (28U)
#define FLASH_ICR_CRCRDERRF_Msk              (0x1UL << FLASH_ICR_CRCRDERRF_Pos)                  /*!< 0x10000000 */
#define FLASH_ICR_CRCRDERRF                  FLASH_ICR_CRCRDERRF_Msk                             /*!< CRC read error flag clear */

/*****************  Bits definition for FLASH_CRCCR register  *****************/
#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)                 /*!< 0x00000007 */
#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk                            /*!< CRC sector number */
#define FLASH_CRCCR_CRC_SECT_0               (0x1UL << FLASH_CRCCR_CRC_SECT_Pos)                 /*!< 0x00000001 */
#define FLASH_CRCCR_CRC_SECT_1               (0x2UL << FLASH_CRCCR_CRC_SECT_Pos)                 /*!< 0x00000002 */
#define FLASH_CRCCR_CRC_SECT_2               (0x4UL << FLASH_CRCCR_CRC_SECT_Pos)                 /*!< 0x00000004 */
#define FLASH_CRCCR_CRC_BY_SECT_Pos          (9U)
#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)              /*!< 0x00000200 */
#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk                         /*!< CRC sector mode select bit */
#define FLASH_CRCCR_ADD_SECT_Pos             (10U)
#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)                 /*!< 0x00000400 */
#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk                            /*!< CRC sector select bit */
#define FLASH_CRCCR_CLEAN_SECT_Pos           (11U)
#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)               /*!< 0x00000800 */
#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk                          /*!< CRC sector list clear bit */
#define FLASH_CRCCR_START_CRC_Pos            (16U)
#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos)                /*!< 0x00010000 */
#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk                           /*!< CRC start bit */
#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)                /*!< 0x00020000 */
#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk                           /*!< CRC clear bit */
#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)                /*!< 0x00300000 */
#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk                           /*!< CRC burst size */
#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)                /*!< 0x00100000 */
#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)                /*!< 0x00200000 */
#define FLASH_CRCCR_ALL_SECT_Pos             (24U)
#define FLASH_CRCCR_ALL_SECT_Msk             (0x1UL << FLASH_CRCCR_ALL_SECT_Pos)                 /*!< 0x01000000 */
#define FLASH_CRCCR_ALL_SECT                 FLASH_CRCCR_ALL_SECT_Msk                            /*!< All sectors selection */

/***************  Bits definition for FLASH_CRCSADDR register  ****************/
#define FLASH_CRCSADDR_CRC_START_ADDRESS_Pos (6U)
#define FLASH_CRCSADDR_CRC_START_ADDRESS_Msk (0x7FFUL << FLASH_CRCSADDR_CRC_START_ADDRESS_Pos)   /*!< 0x0001FFC0 */
#define FLASH_CRCSADDR_CRC_START_ADDRESS     FLASH_CRCSADDR_CRC_START_ADDRESS_Msk                /*!< CRC start address */

/***************  Bits definition for FLASH_CRCEADDR register  ****************/
#define FLASH_CRCEADDR_CRC_END_ADDRESS_Pos   (6U)
#define FLASH_CRCEADDR_CRC_END_ADDRESS_Msk   (0x7FFUL << FLASH_CRCEADDR_CRC_END_ADDRESS_Pos)     /*!< 0x0001FFC0 */
#define FLASH_CRCEADDR_CRC_END_ADDRESS       FLASH_CRCEADDR_CRC_END_ADDRESS_Msk                  /*!< CRC end address */

/***************  Bits definition for FLASH_CRCDATAR register  ****************/
#define FLASH_CRCDATAR_CRC_DATA_Pos          (0U)
#define FLASH_CRCDATAR_CRC_DATA_Msk          (0xFFFFFFFFUL << FLASH_CRCDATAR_CRC_DATA_Pos)       /*!< 0xFFFFFFFF */
#define FLASH_CRCDATAR_CRC_DATA              FLASH_CRCDATAR_CRC_DATA_Msk                         /*!< CRC result */

/**************  Bits definition for FLASH_ECCSFADDR register  ****************/
#define FLASH_ECCSFADDR_SEC_FADD_Pos         (0U)
#define FLASH_ECCSFADDR_SEC_FADD_Msk         (0xFFFFFFFFUL << FLASH_ECCSFADDR_SEC_FADD_Pos)      /*!< 0xFFFFFFFF */
#define FLASH_ECCSFADDR_SEC_FADD             FLASH_ECCSFADDR_SEC_FADD_Msk                        /*!< ECC single error correction fail address */

/**************  Bits definition for FLASH_ECCDFADDR register  ****************/
#define FLASH_ECCDFADDR_DED_FADD_Pos         (0U)
#define FLASH_ECCDFADDR_DED_FADD_Msk         (0xFFFFFFFFUL << FLASH_ECCDFADDR_DED_FADD_Pos)      /*!< 0xFFFFFFFF */
#define FLASH_ECCDFADDR_DED_FADD             FLASH_ECCDFADDR_DED_FADD_Msk                        /*!< ECC double error detection fail address */

/****************  Bits definition for FLASH_OPTKEYR register  ****************/
#define FLASH_OPTKEYR_OCUKEY_Pos             (0U)
#define FLASH_OPTKEYR_OCUKEY_Msk             (0xFFFFFFFFUL << FLASH_OPTKEYR_OCUKEY_Pos)          /*!< 0xFFFFFFFF */
#define FLASH_OPTKEYR_OCUKEY                 FLASH_OPTKEYR_OCUKEY_Msk                            /*!< Options configuration unlock key */

/*****************  Bits definition for FLASH_OPTCR register  *****************/
#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)                  /*!< 0x00000001 */
#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk                             /*!< Options lock */
#define FLASH_OPTCR_PG_OPT_Pos               (1U)
#define FLASH_OPTCR_PG_OPT_Msk               (0x1UL << FLASH_OPTCR_PG_OPT_Pos)                   /*!< 0x00000002 */
#define FLASH_OPTCR_PG_OPT                   FLASH_OPTCR_PG_OPT_Msk                              /*!< Program options */
#define FLASH_OPTCR_KVEIE_Pos                (27U)
#define FLASH_OPTCR_KVEIE_Msk                (0x1UL << FLASH_OPTCR_KVEIE_Pos)                    /*!< 0x08000000 */
#define FLASH_OPTCR_KVEIE                    FLASH_OPTCR_KVEIE_Msk                               /*!< Key valid error interrupt enable bit */
#define FLASH_OPTCR_KTEIE_Pos                (28U)
#define FLASH_OPTCR_KTEIE_Msk                (0x1UL << FLASH_OPTCR_KTEIE_Pos)                    /*!< 0x10000000 */
#define FLASH_OPTCR_KTEIE                    FLASH_OPTCR_KTEIE_Msk                               /*!< Key transfer error interrupt enable bit */
#define FLASH_OPTCR_OPTERRIE_Pos             (30U)
#define FLASH_OPTCR_OPTERRIE_Msk             (0x1UL << FLASH_OPTCR_OPTERRIE_Pos)                 /*!< 0x40000000 */
#define FLASH_OPTCR_OPTERRIE                 FLASH_OPTCR_OPTERRIE_Msk                            /*!< Options byte change error interrupt enable bit */

/****************  Bits definition for FLASH_OPTISR register  *****************/
#define FLASH_OPTISR_KVEF_Pos                (27U)
#define FLASH_OPTISR_KVEF_Msk                (0x1UL << FLASH_OPTISR_KVEF_Pos)                    /*!< 0x08000000 */
#define FLASH_OPTISR_KVEF                    FLASH_OPTISR_KVEF_Msk                               /*!< Key valid error flag */
#define FLASH_OPTISR_KTEF_Pos                (28U)
#define FLASH_OPTISR_KTEF_Msk                (0x1UL << FLASH_OPTISR_KTEF_Pos)                    /*!< 0x10000000 */
#define FLASH_OPTISR_KTEF                    FLASH_OPTISR_KTEF_Msk                               /*!< Key transfer error flag */
#define FLASH_OPTISR_OPTERRF_Pos             (30U)
#define FLASH_OPTISR_OPTERRF_Msk             (0x1UL << FLASH_OPTISR_OPTERRF_Pos)                 /*!< 0x40000000 */
#define FLASH_OPTISR_OPTERRF                 FLASH_OPTISR_OPTERRF_Msk                            /*!< Options byte change error flag */

/****************  Bits definition for FLASH_OPTICR register  *****************/
#define FLASH_OPTICR_KVEF_Pos                (27U)
#define FLASH_OPTICR_KVEF_Msk                (0x1UL << FLASH_OPTICR_KVEF_Pos)                    /*!< 0x08000000 */
#define FLASH_OPTICR_KVEF                    FLASH_OPTICR_KVEF_Msk                               /*!< Key valid error flag clear */
#define FLASH_OPTICR_KTEF_Pos                (28U)
#define FLASH_OPTICR_KTEF_Msk                (0x1UL << FLASH_OPTICR_KTEF_Pos)                    /*!< 0x10000000 */
#define FLASH_OPTICR_KTEF                    FLASH_OPTICR_KTEF_Msk                               /*!< Key transfer error flag clear */
#define FLASH_OPTICR_OPTERRF_Pos             (30U)
#define FLASH_OPTICR_OPTERRF_Msk             (0x1UL << FLASH_OPTICR_OPTERRF_Pos)                 /*!< 0x40000000 */
#define FLASH_OPTICR_OPTERRF                 FLASH_OPTICR_OPTERRF_Msk                            /*!< Options byte change error flag clear */

/****************  Bits definition for FLASH_OBKCR register  *****************/
#define FLASH_OBKCR_OBKINDEX_Pos             (0U)
#define FLASH_OBKCR_OBKINDEX_Msk             (0x1FUL << FLASH_OBKCR_OBKINDEX_Pos)               /*!< 0x0000001F */
#define FLASH_OBKCR_OBKINDEX                 FLASH_OBKCR_OBKINDEX_Msk                           /*!< Option byte key index */
#define FLASH_OBKCR_OBKINDEX_0               (0x1UL << FLASH_OBKCR_OBKINDEX_Pos)                /*!< 0x00000001 */
#define FLASH_OBKCR_OBKINDEX_1               (0x2UL << FLASH_OBKCR_OBKINDEX_Pos)                /*!< 0x00000002 */
#define FLASH_OBKCR_OBKINDEX_2               (0x4UL << FLASH_OBKCR_OBKINDEX_Pos)                /*!< 0x00000004 */
#define FLASH_OBKCR_OBKINDEX_3               (0x8UL << FLASH_OBKCR_OBKINDEX_Pos)                /*!< 0x00000008 */
#define FLASH_OBKCR_OBKINDEX_4               (0x10UL << FLASH_OBKCR_OBKINDEX_Pos)               /*!< 0x00000010 */
#define FLASH_OBKCR_NEXTKL_Pos               (8U)
#define FLASH_OBKCR_NEXTKL_Msk               (0x3UL << FLASH_OBKCR_NEXTKL_Pos)                  /*!< 0x00000300 */
#define FLASH_OBKCR_NEXTKL                   FLASH_OBKCR_NEXTKL_Msk                             /*!< Next key level */
#define FLASH_OBKCR_NEXTKL_0                 (0x1UL << FLASH_OBKCR_NEXTKL_Pos)                  /*!< 0x00000100 */
#define FLASH_OBKCR_NEXTKL_1                 (0x2UL << FLASH_OBKCR_NEXTKL_Pos)                  /*!< 0x00000200 */
#define FLASH_OBKCR_OBKSIZE_Pos              (10U)
#define FLASH_OBKCR_OBKSIZE_Msk              (0x3UL << FLASH_OBKCR_OBKSIZE_Pos)                 /*!< 0x00000C00 */
#define FLASH_OBKCR_OBKSIZE                  FLASH_OBKCR_OBKSIZE_Msk                            /*!< Option byte key size */
#define FLASH_OBKCR_OBKSIZE_0                (0x1UL << FLASH_OBKCR_OBKSIZE_Pos)                 /*!< 0x00000400 */
#define FLASH_OBKCR_OBKSIZE_1                (0x2UL << FLASH_OBKCR_OBKSIZE_Pos)                 /*!< 0x00000800 */
#define FLASH_OBKCR_KEYPROG_Pos              (14U)
#define FLASH_OBKCR_KEYPROG_Msk              (0x1UL << FLASH_OBKCR_KEYPROG_Pos)                 /*!< 0x00004000 */
#define FLASH_OBKCR_KEYPROG                  FLASH_OBKCR_KEYPROG_Msk                            /*!< Key program */
#define FLASH_OBKCR_KEYSTART_Pos             (15U)
#define FLASH_OBKCR_KEYSTART_Msk             (0x1UL << FLASH_OBKCR_KEYSTART_Pos)                /*!< 0x00008000 */
#define FLASH_OBKCR_KEYSTART                 FLASH_OBKCR_KEYSTART_Msk                           /*!< Key option start */

/****************  Bits definition for FLASH_OBKDRx register  *****************/
#define FLASH_OBKDRx_OBKDATA_Pos             (0U)
#define FLASH_OBKDRx_OBKDATA_Msk             (0xFFFFFFFFUL << FLASH_OBKDRx_OBKDATA_Pos)           /*!< 0xFFFFFFFF */
#define FLASH_OBKDRx_OBKDATA                 FLASH_OBKDRx_OBKDATA_Msk                             /*!< Option byte key data */

/*****************  Bits definition for FLASH_NVSR register  ******************/
#define FLASH_NVSR_NVSTATE_Pos               (0U)
#define FLASH_NVSR_NVSTATE_Msk               (0xFFUL << FLASH_NVSR_NVSTATE_Pos)                  /*!< 0x000000FF */
#define FLASH_NVSR_NVSTATE                   FLASH_NVSR_NVSTATE_Msk                              /*!< Non-volatile state */
#define FLASH_NVSR_NVSTATE_0                 (0x1UL << FLASH_NVSR_NVSTATE_Pos)                   /*!< 0x00000001 */
#define FLASH_NVSR_NVSTATE_1                 (0x2UL << FLASH_NVSR_NVSTATE_Pos)                   /*!< 0x00000002 */
#define FLASH_NVSR_NVSTATE_2                 (0x4UL << FLASH_NVSR_NVSTATE_Pos)                   /*!< 0x00000004 */
#define FLASH_NVSR_NVSTATE_3                 (0x8UL << FLASH_NVSR_NVSTATE_Pos)                   /*!< 0x00000008 */
#define FLASH_NVSR_NVSTATE_4                 (0x10UL << FLASH_NVSR_NVSTATE_Pos)                  /*!< 0x00000010 */
#define FLASH_NVSR_NVSTATE_5                 (0x20UL << FLASH_NVSR_NVSTATE_Pos)                  /*!< 0x00000020 */
#define FLASH_NVSR_NVSTATE_6                 (0x40UL << FLASH_NVSR_NVSTATE_Pos)                  /*!< 0x00000040 */
#define FLASH_NVSR_NVSTATE_7                 (0x80UL << FLASH_NVSR_NVSTATE_Pos)                  /*!< 0x00000080 */

/****************  Bits definition for FLASH_NVSRP register  ******************/
#define FLASH_NVSRP_NVSTATE_Pos              (0U)
#define FLASH_NVSRP_NVSTATE_Msk              (0xFFUL << FLASH_NVSRP_NVSTATE_Pos)                 /*!< 0x000000FF */
#define FLASH_NVSRP_NVSTATE                  FLASH_NVSRP_NVSTATE_Msk                             /*!< Non-volatile state */
#define FLASH_NVSRP_NVSTATE_0                (0x1UL << FLASH_NVSRP_NVSTATE_Pos)                  /*!< 0x00000001 */
#define FLASH_NVSRP_NVSTATE_1                (0x2UL << FLASH_NVSRP_NVSTATE_Pos)                  /*!< 0x00000002 */
#define FLASH_NVSRP_NVSTATE_2                (0x4UL << FLASH_NVSRP_NVSTATE_Pos)                  /*!< 0x00000004 */
#define FLASH_NVSRP_NVSTATE_3                (0x8UL << FLASH_NVSRP_NVSTATE_Pos)                  /*!< 0x00000008 */
#define FLASH_NVSRP_NVSTATE_4                (0x10UL << FLASH_NVSRP_NVSTATE_Pos)                 /*!< 0x00000010 */
#define FLASH_NVSRP_NVSTATE_5                (0x20UL << FLASH_NVSRP_NVSTATE_Pos)                 /*!< 0x00000020 */
#define FLASH_NVSRP_NVSTATE_6                (0x40UL << FLASH_NVSRP_NVSTATE_Pos)                 /*!< 0x00000040 */
#define FLASH_NVSRP_NVSTATE_7                (0x80UL << FLASH_NVSRP_NVSTATE_Pos)                 /*!< 0x00000080 */

/****************  Bits definition for FLASH_ROTSR register  ******************/
#define FLASH_ROTSR_OEM_PROVD_Pos            (0U)
#define FLASH_ROTSR_OEM_PROVD_Msk            (0xFFUL << FLASH_ROTSR_OEM_PROVD_Pos)               /*!< 0x000000FF */
#define FLASH_ROTSR_OEM_PROVD                FLASH_ROTSR_OEM_PROVD_Msk                           /*!< OEM provisioned state */
#define FLASH_ROTSR_OEM_PROVD_0              (0x1UL << FLASH_ROTSR_OEM_PROVD_Pos)                /*!< 0x00000001 */
#define FLASH_ROTSR_OEM_PROVD_1              (0x2UL << FLASH_ROTSR_OEM_PROVD_Pos)                /*!< 0x00000002 */
#define FLASH_ROTSR_OEM_PROVD_2              (0x4UL << FLASH_ROTSR_OEM_PROVD_Pos)                /*!< 0x00000004 */
#define FLASH_ROTSR_OEM_PROVD_3              (0x8UL << FLASH_ROTSR_OEM_PROVD_Pos)                /*!< 0x00000008 */
#define FLASH_ROTSR_OEM_PROVD_4              (0x10UL << FLASH_ROTSR_OEM_PROVD_Pos)               /*!< 0x00000010 */
#define FLASH_ROTSR_OEM_PROVD_5              (0x20UL << FLASH_ROTSR_OEM_PROVD_Pos)               /*!< 0x00000020 */
#define FLASH_ROTSR_OEM_PROVD_6              (0x40UL << FLASH_ROTSR_OEM_PROVD_Pos)               /*!< 0x00000040 */
#define FLASH_ROTSR_OEM_PROVD_7              (0x80UL << FLASH_ROTSR_OEM_PROVD_Pos)               /*!< 0x00000080 */
#define FLASH_ROTSR_DBG_AUTH_Pos             (8U)
#define FLASH_ROTSR_DBG_AUTH_Msk             (0xFFUL << FLASH_ROTSR_DBG_AUTH_Pos)                /*!< 0x0000FF00 */
#define FLASH_ROTSR_DBG_AUTH                 FLASH_ROTSR_DBG_AUTH_Msk                            /*!< Debug authentication method */
#define FLASH_ROTSR_DBG_AUTH_0               (0x1UL << FLASH_ROTSR_DBG_AUTH_Pos)                 /*!< 0x00000100 */
#define FLASH_ROTSR_DBG_AUTH_1               (0x2UL << FLASH_ROTSR_DBG_AUTH_Pos)                 /*!< 0x00000200 */
#define FLASH_ROTSR_DBG_AUTH_2               (0x4UL << FLASH_ROTSR_DBG_AUTH_Pos)                 /*!< 0x00000400 */
#define FLASH_ROTSR_DBG_AUTH_3               (0x8UL << FLASH_ROTSR_DBG_AUTH_Pos)                 /*!< 0x00000800 */
#define FLASH_ROTSR_DBG_AUTH_4               (0x10UL << FLASH_ROTSR_DBG_AUTH_Pos)                /*!< 0x00001000 */
#define FLASH_ROTSR_DBG_AUTH_5               (0x20UL << FLASH_ROTSR_DBG_AUTH_Pos)                /*!< 0x00002000 */
#define FLASH_ROTSR_DBG_AUTH_6               (0x40UL << FLASH_ROTSR_DBG_AUTH_Pos)                /*!< 0x00004000 */
#define FLASH_ROTSR_DBG_AUTH_7               (0x80UL << FLASH_ROTSR_DBG_AUTH_Pos)                /*!< 0x00008000 */
#define FLASH_ROTSR_IROT_SELECT_Pos          (24U)
#define FLASH_ROTSR_IROT_SELECT_Msk          (0xFFUL << FLASH_ROTSR_IROT_SELECT_Pos)             /*!< 0xFF000000 */
#define FLASH_ROTSR_IROT_SELECT              FLASH_ROTSR_IROT_SELECT_Msk                         /*!< iRoT selection */
#define FLASH_ROTSR_IROT_SELECT_0            (0x1UL << FLASH_ROTSR_IROT_SELECT_Pos)              /*!< 0x01000000 */
#define FLASH_ROTSR_IROT_SELECT_1            (0x2UL << FLASH_ROTSR_IROT_SELECT_Pos)              /*!< 0x02000000 */
#define FLASH_ROTSR_IROT_SELECT_2            (0x4UL << FLASH_ROTSR_IROT_SELECT_Pos)              /*!< 0x04000000 */
#define FLASH_ROTSR_IROT_SELECT_3            (0x8UL << FLASH_ROTSR_IROT_SELECT_Pos)              /*!< 0x08000000 */
#define FLASH_ROTSR_IROT_SELECT_4            (0x10UL << FLASH_ROTSR_IROT_SELECT_Pos)             /*!< 0x10000000 */
#define FLASH_ROTSR_IROT_SELECT_5            (0x20UL << FLASH_ROTSR_IROT_SELECT_Pos)             /*!< 0x20000000 */
#define FLASH_ROTSR_IROT_SELECT_6            (0x40UL << FLASH_ROTSR_IROT_SELECT_Pos)             /*!< 0x40000000 */
#define FLASH_ROTSR_IROT_SELECT_7            (0x80UL << FLASH_ROTSR_IROT_SELECT_Pos)             /*!< 0x80000000 */

/****************  Bits definition for FLASH_ROTSRP register  *****************/
#define FLASH_ROTSRP_OEM_PROVD_Pos           (0U)
#define FLASH_ROTSRP_OEM_PROVD_Msk           (0xFFUL << FLASH_ROTSRP_OEM_PROVD_Pos)              /*!< 0x000000FF */
#define FLASH_ROTSRP_OEM_PROVD               FLASH_ROTSRP_OEM_PROVD_Msk                          /*!< OEM provisioned state */
#define FLASH_ROTSRP_OEM_PROVD_0             (0x1UL << FLASH_ROTSRP_OEM_PROVD_Pos)               /*!< 0x00000001 */
#define FLASH_ROTSRP_OEM_PROVD_1             (0x2UL << FLASH_ROTSRP_OEM_PROVD_Pos)               /*!< 0x00000002 */
#define FLASH_ROTSRP_OEM_PROVD_2             (0x4UL << FLASH_ROTSRP_OEM_PROVD_Pos)               /*!< 0x00000004 */
#define FLASH_ROTSRP_OEM_PROVD_3             (0x8UL << FLASH_ROTSRP_OEM_PROVD_Pos)               /*!< 0x00000008 */
#define FLASH_ROTSRP_OEM_PROVD_4             (0x10UL << FLASH_ROTSRP_OEM_PROVD_Pos)              /*!< 0x00000010 */
#define FLASH_ROTSRP_OEM_PROVD_5             (0x20UL << FLASH_ROTSRP_OEM_PROVD_Pos)              /*!< 0x00000020 */
#define FLASH_ROTSRP_OEM_PROVD_6             (0x40UL << FLASH_ROTSRP_OEM_PROVD_Pos)              /*!< 0x00000040 */
#define FLASH_ROTSRP_OEM_PROVD_7             (0x80UL << FLASH_ROTSRP_OEM_PROVD_Pos)              /*!< 0x00000080 */
#define FLASH_ROTSRP_DBG_AUTH_Pos            (8U)
#define FLASH_ROTSRP_DBG_AUTH_Msk            (0xFFUL << FLASH_ROTSRP_DBG_AUTH_Pos)               /*!< 0x0000FF00 */
#define FLASH_ROTSRP_DBG_AUTH                FLASH_ROTSRP_DBG_AUTH_Msk                           /*!< Debug authentication method */
#define FLASH_ROTSRP_DBG_AUTH_0              (0x1UL << FLASH_ROTSRP_DBG_AUTH_Pos)                /*!< 0x00000100 */
#define FLASH_ROTSRP_DBG_AUTH_1              (0x2UL << FLASH_ROTSRP_DBG_AUTH_Pos)                /*!< 0x00000200 */
#define FLASH_ROTSRP_DBG_AUTH_2              (0x4UL << FLASH_ROTSRP_DBG_AUTH_Pos)                /*!< 0x00000400 */
#define FLASH_ROTSRP_DBG_AUTH_3              (0x8UL << FLASH_ROTSRP_DBG_AUTH_Pos)                /*!< 0x00000800 */
#define FLASH_ROTSRP_DBG_AUTH_4              (0x10UL << FLASH_ROTSRP_DBG_AUTH_Pos)               /*!< 0x00001000 */
#define FLASH_ROTSRP_DBG_AUTH_5              (0x20UL << FLASH_ROTSRP_DBG_AUTH_Pos)               /*!< 0x00002000 */
#define FLASH_ROTSRP_DBG_AUTH_6              (0x40UL << FLASH_ROTSRP_DBG_AUTH_Pos)               /*!< 0x00004000 */
#define FLASH_ROTSRP_DBG_AUTH_7              (0x80UL << FLASH_ROTSRP_DBG_AUTH_Pos)               /*!< 0x00008000 */
#define FLASH_ROTSRP_IROT_SELECT_Pos         (24U)
#define FLASH_ROTSRP_IROT_SELECT_Msk         (0xFFUL << FLASH_ROTSRP_IROT_SELECT_Pos)             /*!< 0xFF000000 */
#define FLASH_ROTSRP_IROT_SELECT             FLASH_ROTSRP_IROT_SELECT_Msk                         /*!< iRoT selection */
#define FLASH_ROTSRP_IROT_SELECT_0           (0x1UL << FLASH_ROTSRP_IROT_SELECT_Pos)              /*!< 0x01000000 */
#define FLASH_ROTSRP_IROT_SELECT_1           (0x2UL << FLASH_ROTSRP_IROT_SELECT_Pos)              /*!< 0x02000000 */
#define FLASH_ROTSRP_IROT_SELECT_2           (0x4UL << FLASH_ROTSRP_IROT_SELECT_Pos)              /*!< 0x04000000 */
#define FLASH_ROTSRP_IROT_SELECT_3           (0x8UL << FLASH_ROTSRP_IROT_SELECT_Pos)              /*!< 0x08000000 */
#define FLASH_ROTSRP_IROT_SELECT_4           (0x10UL << FLASH_ROTSRP_IROT_SELECT_Pos)             /*!< 0x10000000 */
#define FLASH_ROTSRP_IROT_SELECT_5           (0x20UL << FLASH_ROTSRP_IROT_SELECT_Pos)             /*!< 0x20000000 */
#define FLASH_ROTSRP_IROT_SELECT_6           (0x40UL << FLASH_ROTSRP_IROT_SELECT_Pos)             /*!< 0x40000000 */
#define FLASH_ROTSRP_IROT_SELECT_7           (0x80UL << FLASH_ROTSRP_IROT_SELECT_Pos)             /*!< 0x80000000 */

/****************  Bits definition for FLASH_OTPLSR register  *****************/
#define FLASH_OTPLSR_OTPL_Pos                (0U)
#define FLASH_OTPLSR_OTPL_Msk                (0xFFFFUL << FLASH_OTPLSR_OTPL_Pos)                 /*!< 0x0000FFFF */
#define FLASH_OTPLSR_OTPL                    FLASH_OTPLSR_OTPL_Msk                               /*!< OTP lock n (n=0 to 15) */

/***************  Bits definition for FLASH_OTPLSRP register  *****************/
#define FLASH_OTPLSRP_OTPL_Pos               (0U)
#define FLASH_OTPLSRP_OTPL_Msk               (0xFFFFUL << FLASH_OTPLSRP_OTPL_Pos)                /*!< 0x0000FFFF */
#define FLASH_OTPLSRP_OTPL                   FLASH_OTPLSRP_OTPL_Msk                              /*!< OTP lock n (n=0 to 15) */

/****************  Bits definition for FLASH_WRPSR register  ******************/
#define FLASH_WRPSR_WRPS_Pos                 (0U)
#define FLASH_WRPSR_WRPS_Msk                 (0xFFUL << FLASH_WRPSR_WRPS_Pos)                    /*!< 0x000000FF */
#define FLASH_WRPSR_WRPS                     FLASH_WRPSR_WRPS_Msk                                /*!< Write protection for sector n (n=0 to 7) */

/***************  Bits definition for FLASH_WRPSRP register  ******************/
#define FLASH_WRPSRP_WRPS_Pos                (0U)
#define FLASH_WRPSRP_WRPS_Msk                (0xFFUL << FLASH_WRPSRP_WRPS_Pos)                   /*!< 0x000000FF */
#define FLASH_WRPSRP_WRPS                    FLASH_WRPSRP_WRPS_Msk                               /*!< Write protection for sector n (n=0 to 7) */

/****************  Bits definition for FLASH_HDPSR register  ******************/
#define FLASH_HDPSR_HDP_AREA_START_Pos       (0U)
#define FLASH_HDPSR_HDP_AREA_START_Msk       (0xFFUL << FLASH_HDPSR_HDP_AREA_START_Pos)          /*!< 0x000000FF */
#define FLASH_HDPSR_HDP_AREA_START           FLASH_HDPSR_HDP_AREA_START_Msk                      /*!< Hide protection user flash area start */
#define FLASH_HDPSR_HDP_AREA_END_Pos         (16U)
#define FLASH_HDPSR_HDP_AREA_END_Msk         (0xFFUL << FLASH_HDPSR_HDP_AREA_END_Pos)            /*!< 0x00FF0000 */
#define FLASH_HDPSR_HDP_AREA_END             FLASH_HDPSR_HDP_AREA_END_Msk                        /*!< Hide protection user flash area end */

/***************  Bits definition for FLASH_HDPSRP register  ******************/
#define FLASH_HDPSRP_HDP_AREA_START_Pos      (0U)
#define FLASH_HDPSRP_HDP_AREA_START_Msk      (0xFFUL << FLASH_HDPSRP_HDP_AREA_START_Pos)         /*!< 0x000000FF */
#define FLASH_HDPSRP_HDP_AREA_START          FLASH_HDPSRP_HDP_AREA_START_Msk                     /*!< Hide protection user flash area start */
#define FLASH_HDPSRP_HDP_AREA_END_Pos        (16U)
#define FLASH_HDPSRP_HDP_AREA_END_Msk        (0xFFUL << FLASH_HDPSRP_HDP_AREA_END_Pos)           /*!< 0x00FF0000 */
#define FLASH_HDPSRP_HDP_AREA_END            FLASH_HDPSRP_HDP_AREA_END_Msk                       /*!< Hide protection user flash area end */

/***************  Bits definition for FLASH_EPOCHSR register  *****************/
#define FLASH_EPOCHSR_EPOCH_Pos              (0U)
#define FLASH_EPOCHSR_EPOCH_Msk              (0xFFFFFFUL << FLASH_EPOCHSR_EPOCH_Pos)             /*!< 0x00FFFFFF */
#define FLASH_EPOCHSR_EPOCH                  FLASH_EPOCHSR_EPOCH_Msk                             /*!< Epoch */

/**************  Bits definition for FLASH_EPOCHSRP register  *****************/
#define FLASH_EPOCHSRP_EPOCH_Pos             (0U)
#define FLASH_EPOCHSRP_EPOCH_Msk             (0xFFFFFFUL << FLASH_EPOCHSRP_EPOCH_Pos)            /*!< 0x00FFFFFF */
#define FLASH_EPOCHSRP_EPOCH                 FLASH_EPOCHSRP_EPOCH_Msk                            /*!< Epoch */

/****************  Bits definition for FLASH_OBW1SR register  *****************/
#define FLASH_OBW1SR_BOR_LEVEL_Pos           (2U)
#define FLASH_OBW1SR_BOR_LEVEL_Msk           (0x3UL << FLASH_OBW1SR_BOR_LEVEL_Pos)               /*!< 0x0000000C */
#define FLASH_OBW1SR_BOR_LEVEL               FLASH_OBW1SR_BOR_LEVEL_Msk                          /*!< Brownout level */
#define FLASH_OBW1SR_BOR_LEVEL_0             (0x1UL << FLASH_OBW1SR_BOR_LEVEL_Pos)               /*!< 0x00000004 */
#define FLASH_OBW1SR_BOR_LEVEL_1             (0x2UL << FLASH_OBW1SR_BOR_LEVEL_Pos)               /*!< 0x00000008 */
#define FLASH_OBW1SR_IWDG_HW_Pos             (4U)
#define FLASH_OBW1SR_IWDG_HW_Msk             (0x1UL << FLASH_OBW1SR_IWDG_HW_Pos)                 /*!< 0x00000010 */
#define FLASH_OBW1SR_IWDG_HW                 FLASH_OBW1SR_IWDG_HW_Msk                            /*!< Independent watchdog HW control */
#define FLASH_OBW1SR_NRST_STOP_Pos           (6U)
#define FLASH_OBW1SR_NRST_STOP_Msk           (0x1UL << FLASH_OBW1SR_NRST_STOP_Pos)               /*!< 0x00000040 */
#define FLASH_OBW1SR_NRST_STOP               FLASH_OBW1SR_NRST_STOP_Msk                          /*!< Reset on stop mode */
#define FLASH_OBW1SR_NRST_STBY_Pos           (7U)
#define FLASH_OBW1SR_NRST_STBY_Msk           (0x1UL << FLASH_OBW1SR_NRST_STBY_Pos)               /*!< 0x00000080 */
#define FLASH_OBW1SR_NRST_STBY               FLASH_OBW1SR_NRST_STBY_Msk                          /*!< Reset on standby mode */
#define FLASH_OBW1SR_XSPI1_HSLV_Pos          (8U)
#define FLASH_OBW1SR_XSPI1_HSLV_Msk          (0x1UL << FLASH_OBW1SR_XSPI1_HSLV_Pos)              /*!< 0x00000100 */
#define FLASH_OBW1SR_XSPI1_HSLV              FLASH_OBW1SR_XSPI1_HSLV_Msk                         /*!< XSPI1 High-speed at low voltage */
#define FLASH_OBW1SR_XSPI2_HSLV_Pos          (9U)
#define FLASH_OBW1SR_XSPI2_HSLV_Msk          (0x1UL << FLASH_OBW1SR_XSPI2_HSLV_Pos)              /*!< 0x00000200 */
#define FLASH_OBW1SR_XSPI2_HSLV              FLASH_OBW1SR_XSPI2_HSLV_Msk                         /*!< XSPI2 High-speed at low voltage */
#define FLASH_OBW1SR_IWDG_FZ_STOP_Pos        (17U)
#define FLASH_OBW1SR_IWDG_FZ_STOP_Msk        (0x1UL << FLASH_OBW1SR_IWDG_FZ_STOP_Pos)            /*!< 0x00020000 */
#define FLASH_OBW1SR_IWDG_FZ_STOP            FLASH_OBW1SR_IWDG_FZ_STOP_Msk                       /*!< IWDG Stop mode freeze */
#define FLASH_OBW1SR_IWDG_FZ_STBY_Pos        (18U)
#define FLASH_OBW1SR_IWDG_FZ_STBY_Msk        (0x1UL << FLASH_OBW1SR_IWDG_FZ_STBY_Pos)            /*!< 0x00040000 */
#define FLASH_OBW1SR_IWDG_FZ_STBY            FLASH_OBW1SR_IWDG_FZ_STBY_Msk                       /*!< IWDG Standby mode freeze */
#define FLASH_OBW1SR_PERSO_OK_Pos            (28U)
#define FLASH_OBW1SR_PERSO_OK_Msk            (0x1UL << FLASH_OBW1SR_PERSO_OK_Pos)                /*!< 0x10000000 */
#define FLASH_OBW1SR_PERSO_OK                FLASH_OBW1SR_PERSO_OK_Msk                           /*!< Personnalization OK */
#define FLASH_OBW1SR_VDDIO_HSLV_Pos          (29U)
#define FLASH_OBW1SR_VDDIO_HSLV_Msk          (0x1UL << FLASH_OBW1SR_VDDIO_HSLV_Pos)              /*!< 0x20000000 */
#define FLASH_OBW1SR_VDDIO_HSLV              FLASH_OBW1SR_VDDIO_HSLV_Msk                         /*!< I/O High-speed at low voltage */

/***************  Bits definition for FLASH_OBW1SRP register  *****************/
#define FLASH_OBW1SRP_BOR_LEVEL_Pos          (2U)
#define FLASH_OBW1SRP_BOR_LEVEL_Msk          (0x3UL << FLASH_OBW1SRP_BOR_LEVEL_Pos)              /*!< 0x0000000C */
#define FLASH_OBW1SRP_BOR_LEVEL              FLASH_OBW1SRP_BOR_LEVEL_Msk                         /*!< Brownout level */
#define FLASH_OBW1SRP_BOR_LEVEL_0            (0x1UL << FLASH_OBW1SRP_BOR_LEVEL_Pos)              /*!< 0x00000004 */
#define FLASH_OBW1SRP_BOR_LEVEL_1            (0x2UL << FLASH_OBW1SRP_BOR_LEVEL_Pos)              /*!< 0x00000008 */
#define FLASH_OBW1SRP_IWDG_HW_Pos            (4U)
#define FLASH_OBW1SRP_IWDG_HW_Msk            (0x1UL << FLASH_OBW1SRP_IWDG_HW_Pos)                /*!< 0x00000010 */
#define FLASH_OBW1SRP_IWDG_HW                FLASH_OBW1SRP_IWDG_HW_Msk                           /*!< Independent watchdog HW control */
#define FLASH_OBW1SRP_NRST_STOP_Pos          (6U)
#define FLASH_OBW1SRP_NRST_STOP_Msk          (0x1UL << FLASH_OBW1SRP_NRST_STOP_Pos)              /*!< 0x00000040 */
#define FLASH_OBW1SRP_NRST_STOP              FLASH_OBW1SRP_NRST_STOP_Msk                         /*!< Reset on stop mode */
#define FLASH_OBW1SRP_NRST_STBY_Pos          (7U)
#define FLASH_OBW1SRP_NRST_STBY_Msk          (0x1UL << FLASH_OBW1SRP_NRST_STBY_Pos)              /*!< 0x00000080 */
#define FLASH_OBW1SRP_NRST_STBY              FLASH_OBW1SRP_NRST_STBY_Msk                         /*!< Reset on standby mode */
#define FLASH_OBW1SRP_XSPI1_HSLV_Pos         (8U)
#define FLASH_OBW1SRP_XSPI1_HSLV_Msk         (0x1UL << FLASH_OBW1SRP_XSPI1_HSLV_Pos)             /*!< 0x00000100 */
#define FLASH_OBW1SRP_XSPI1_HSLV             FLASH_OBW1SRP_XSPI1_HSLV_Msk                        /*!< XSPI1 High-speed at low voltage */
#define FLASH_OBW1SRP_XSPI2_HSLV_Pos         (9U)
#define FLASH_OBW1SRP_XSPI2_HSLV_Msk         (0x1UL << FLASH_OBW1SRP_XSPI2_HSLV_Pos)             /*!< 0x00000200 */
#define FLASH_OBW1SRP_XSPI2_HSLV             FLASH_OBW1SRP_XSPI2_HSLV_Msk                        /*!< XSPI2 High-speed at low voltage */
#define FLASH_OBW1SRP_IWDG_FZ_STOP_Pos       (17U)
#define FLASH_OBW1SRP_IWDG_FZ_STOP_Msk       (0x1UL << FLASH_OBW1SRP_IWDG_FZ_STOP_Pos)           /*!< 0x00020000 */
#define FLASH_OBW1SRP_IWDG_FZ_STOP           FLASH_OBW1SRP_IWDG_FZ_STOP_Msk                      /*!< IWDG Stop mode freeze */
#define FLASH_OBW1SRP_IWDG_FZ_STBY_Pos       (18U)
#define FLASH_OBW1SRP_IWDG_FZ_STBY_Msk       (0x1UL << FLASH_OBW1SRP_IWDG_FZ_STBY_Pos)           /*!< 0x00040000 */
#define FLASH_OBW1SRP_IWDG_FZ_STBY           FLASH_OBW1SRP_IWDG_FZ_STBY_Msk                      /*!< IWDG Standby mode freeze */
#define FLASH_OBW1SRP_VDDIO_HSLV_Pos         (29U)
#define FLASH_OBW1SRP_VDDIO_HSLV_Msk         (0x1UL << FLASH_OBW1SRP_VDDIO_HSLV_Pos)             /*!< 0x20000000 */
#define FLASH_OBW1SRP_VDDIO_HSLV             FLASH_OBW1SRP_VDDIO_HSLV_Msk                        /*!< I/O High-speed at low voltage */

/****************  Bits definition for FLASH_OBW2SR register  *****************/
#define FLASH_OBW2SR_ITCM_AXI_SHARE_Pos      (0U)
#define FLASH_OBW2SR_ITCM_AXI_SHARE_Msk      (0x7UL << FLASH_OBW2SR_ITCM_AXI_SHARE_Pos)          /*!< 0x00000007 */
#define FLASH_OBW2SR_ITCM_AXI_SHARE          FLASH_OBW2SR_ITCM_AXI_SHARE_Msk                     /*!< ITCM AXI share */
#define FLASH_OBW2SR_ITCM_AXI_SHARE_0        (0x1UL << FLASH_OBW2SR_ITCM_AXI_SHARE_Pos)          /*!< 0x00000001 */
#define FLASH_OBW2SR_ITCM_AXI_SHARE_1        (0x2UL << FLASH_OBW2SR_ITCM_AXI_SHARE_Pos)          /*!< 0x00000002 */
#define FLASH_OBW2SR_ITCM_AXI_SHARE_2        (0x4UL << FLASH_OBW2SR_ITCM_AXI_SHARE_Pos)          /*!< 0x00000004 */
#define FLASH_OBW2SR_DTCM_AXI_SHARE_Pos      (4U)
#define FLASH_OBW2SR_DTCM_AXI_SHARE_Msk      (0x7UL << FLASH_OBW2SR_DTCM_AXI_SHARE_Pos)          /*!< 0x00000070 */
#define FLASH_OBW2SR_DTCM_AXI_SHARE          FLASH_OBW2SR_DTCM_AXI_SHARE_Msk                     /*!< DTCM AXI share */
#define FLASH_OBW2SR_DTCM_AXI_SHARE_0        (0x1UL << FLASH_OBW2SR_DTCM_AXI_SHARE_Pos)          /*!< 0x00000010 */
#define FLASH_OBW2SR_DTCM_AXI_SHARE_1        (0x2UL << FLASH_OBW2SR_DTCM_AXI_SHARE_Pos)          /*!< 0x00000020 */
#define FLASH_OBW2SR_DTCM_AXI_SHARE_2        (0x4UL << FLASH_OBW2SR_DTCM_AXI_SHARE_Pos)          /*!< 0x00000040 */
#define FLASH_OBW2SR_ECC_ON_SRAM_Pos         (8U)
#define FLASH_OBW2SR_ECC_ON_SRAM_Msk         (0x1UL << FLASH_OBW2SR_ECC_ON_SRAM_Pos)             /*!< 0x00000100 */
#define FLASH_OBW2SR_ECC_ON_SRAM             FLASH_OBW2SR_ECC_ON_SRAM_Msk                        /*!< ECC on SRAM */
#define FLASH_OBW2SR_I2C_NI3C_Pos            (9U)
#define FLASH_OBW2SR_I2C_NI3C_Msk            (0x1UL << FLASH_OBW2SR_I2C_NI3C_Pos)                /*!< 0x00000200 */
#define FLASH_OBW2SR_I2C_NI3C                FLASH_OBW2SR_I2C_NI3C_Msk                           /*!< I2C Not I3C */

/***************  Bits definition for FLASH_OBW2SRP register  *****************/
#define FLASH_OBW2SRP_ITCM_AXI_SHARE_Pos     (0U)
#define FLASH_OBW2SRP_ITCM_AXI_SHARE_Msk     (0x7UL << FLASH_OBW2SRP_ITCM_AXI_SHARE_Pos)         /*!< 0x00000007 */
#define FLASH_OBW2SRP_ITCM_AXI_SHARE         FLASH_OBW2SRP_ITCM_AXI_SHARE_Msk                    /*!< ITCM AXI share */
#define FLASH_OBW2SRP_ITCM_AXI_SHARE_0       (0x1UL << FLASH_OBW2SRP_ITCM_AXI_SHARE_Pos)         /*!< 0x00000001 */
#define FLASH_OBW2SRP_ITCM_AXI_SHARE_1       (0x2UL << FLASH_OBW2SRP_ITCM_AXI_SHARE_Pos)         /*!< 0x00000002 */
#define FLASH_OBW2SRP_ITCM_AXI_SHARE_2       (0x4UL << FLASH_OBW2SRP_ITCM_AXI_SHARE_Pos)         /*!< 0x00000004 */
#define FLASH_OBW2SRP_DTCM_AXI_SHARE_Pos     (4U)
#define FLASH_OBW2SRP_DTCM_AXI_SHARE_Msk     (0x7UL << FLASH_OBW2SRP_DTCM_AXI_SHARE_Pos)         /*!< 0x00000070 */
#define FLASH_OBW2SRP_DTCM_AXI_SHARE         FLASH_OBW2SRP_DTCM_AXI_SHARE_Msk                    /*!< DTCM AXI share */
#define FLASH_OBW2SRP_DTCM_AXI_SHARE_0       (0x1UL << FLASH_OBW2SRP_DTCM_AXI_SHARE_Pos)         /*!< 0x00000010 */
#define FLASH_OBW2SRP_DTCM_AXI_SHARE_1       (0x2UL << FLASH_OBW2SRP_DTCM_AXI_SHARE_Pos)         /*!< 0x00000020 */
#define FLASH_OBW2SRP_DTCM_AXI_SHARE_2       (0x4UL << FLASH_OBW2SRP_DTCM_AXI_SHARE_Pos)         /*!< 0x00000040 */
#define FLASH_OBW2SRP_ECC_ON_SRAM_Pos        (8U)
#define FLASH_OBW2SRP_ECC_ON_SRAM_Msk        (0x1UL << FLASH_OBW2SRP_ECC_ON_SRAM_Pos)            /*!< 0x00000100 */
#define FLASH_OBW2SRP_ECC_ON_SRAM            FLASH_OBW2SRP_ECC_ON_SRAM_Msk                       /*!< ECC on SRAM */
#define FLASH_OBW2SRP_I2C_NI3C_Pos           (9U)
#define FLASH_OBW2SRP_I2C_NI3C_Msk           (0x1UL << FLASH_OBW2SRP_I2C_NI3C_Pos)               /*!< 0x00000200 */
#define FLASH_OBW2SRP_I2C_NI3C               FLASH_OBW2SRP_I2C_NI3C_Msk                          /*!< I2C Not I3C */


/******************************************************************************/
/*                                                                            */
/*                          Flexible Memory Controller                        */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for FMC_BCR1 register  ********************/
#define FMC_BCR1_CCLKEN_Pos        (20U)
#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!< Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos         (21U)
#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!< Write FIFO Disable */
#define FMC_BCR1_BMAP_Pos          (24U)
#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!< FMC bank mapping */
#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                /*!< 0x01000000 */
#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                /*!< 0x02000000 */
#define FMC_BCR1_FMCEN_Pos         (31U)
#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!< FMC controller enable */

/******************  Bit definition for FMC_BCRx registers (x=1..4)  **********/
#define FMC_BCRx_MBKEN_Pos         (0U)
#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!< Memory bank enable bit */
#define FMC_BCRx_MUXEN_Pos         (1U)
#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!< Address/data multiplexing enable bit */
#define FMC_BCRx_MTYP_Pos          (2U)
#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!< Memory type */
#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
#define FMC_BCRx_MWID_Pos          (4U)
#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!< Memory data bus width */
#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
#define FMC_BCRx_FACCEN_Pos        (6U)
#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!< Flash access enable */
#define FMC_BCRx_BURSTEN_Pos       (8U)
#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!< Burst enable bit */
#define FMC_BCRx_WAITPOL_Pos       (9U)
#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!< Wait signal polarity bit */
#define FMC_BCRx_WAITCFG_Pos       (11U)
#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!< Wait timing configuration */
#define FMC_BCRx_WREN_Pos          (12U)
#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!< Write enable bit */
#define FMC_BCRx_WAITEN_Pos        (13U)
#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!< Wait enable bit */
#define FMC_BCRx_EXTMOD_Pos        (14U)
#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!< Extended mode enable */
#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!< Wait signal during asynchronous transfers */
#define FMC_BCRx_CPSIZE_Pos        (16U)
#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!< CRAM page size */
#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
#define FMC_BCRx_CBURSTRW_Pos      (19U)
#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!< Write burst enable */

/******************  Bit definition for FMC_BTRx registers (x=1..4)  **********/
#define FMC_BTRx_ADDSET_Pos        (0U)
#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!< Address setup phase duration */
#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
#define FMC_BTRx_ADDHLD_Pos        (4U)
#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!< Address-hold phase duration */
#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
#define FMC_BTRx_DATAST_Pos        (8U)
#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!< Data-phase duration */
#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
#define FMC_BTRx_BUSTURN_Pos       (16U)
#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!< Bus turnaround phase duration */
#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
#define FMC_BTRx_CLKDIV_Pos        (20U)
#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!< Clock divide ratio */
#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
#define FMC_BTRx_DATLAT_Pos        (24U)
#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!< Data latency for synchronous memory */
#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
#define FMC_BTRx_ACCMOD_Pos        (28U)
#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!< Access mode */
#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */

/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
#define FMC_BWTRx_ADDSET_Pos       (0U)
#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!< Address setup phase duration */
#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
#define FMC_BWTRx_ADDHLD_Pos       (4U)
#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!< Address-hold phase duration */
#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
#define FMC_BWTRx_DATAST_Pos       (8U)
#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!< Data-phase duration */
#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
#define FMC_BWTRx_BUSTURN_Pos      (16U)
#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!< Bus turnaround phase duration */
#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
#define FMC_BWTRx_ACCMOD_Pos       (28U)
#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!< Access mode */
#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */

/******************  Bit definition for FMC_PCR register  *********************/
#define FMC_PCR_PWAITEN_Pos        (1U)
#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!< Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos          (2U)
#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!< NAND Flash memory bank enable bit */
#define FMC_PCR_PWID_Pos           (4U)
#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!< Data bus width */
#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos          (6U)
#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!< ECC computation logic enable bit */
#define FMC_PCR_TCLR_Pos           (9U)
#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!< CLE to RE delay */
#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos            (13U)
#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!< ALE to RE delay */
#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
#define FMC_PCR_ECCPS_Pos          (17U)
#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!< ECC page size */
#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */
#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */
#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */

/*******************  Bit definition for FMC_SR register  *********************/
#define FMC_SR_IRS_Pos             (0U)
#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!< Interrupt rising edge status */
#define FMC_SR_ILS_Pos             (1U)
#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!< Interrupt high-level status */
#define FMC_SR_IFS_Pos             (2U)
#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!< Interrupt falling edge status */
#define FMC_SR_IREN_Pos            (3U)
#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!< Interrupt rising edge detection enable bit */
#define FMC_SR_ILEN_Pos            (4U)
#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!< Interrupt high-level detection enable bit */
#define FMC_SR_IFEN_Pos            (5U)
#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!< Interrupt falling edge detection enable bit */
#define FMC_SR_FEMPT_Pos           (6U)
#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!< FIFO empty */

/******************  Bit definition for FMC_PMEM register  ********************/
#define FMC_PMEM_MEMSET_Pos        (0U)
#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!< Common memory setup time */
#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT_Pos       (8U)
#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!< Common memory wait time */
#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD_Pos       (16U)
#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!< Common memory hold time */
#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ_Pos        (24U)
#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!< Common memory databus Hi-Z time */
#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

/******************  Bit definition for FMC_PATT register  ********************/
#define FMC_PATT_ATTSET_Pos        (0U)
#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!< Attribute memory setup time */
#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT_Pos       (8U)
#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!< Attribute memory wait time */
#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD_Pos       (16U)
#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!< Attribute memory hold time */
#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ_Pos        (24U)
#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!< Attribute memory data bus Hi-Z time */
#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

/******************  Bit definition for FMC_ECCR register  ********************/
#define FMC_ECCR_ECC_Pos           (0U)
#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)          /*!< 0xFFFFFFFF */
#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!< ECC result */

/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
#define FMC_SDCRx_NC_Pos           (0U)
#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!< Number of column address bits */
#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000001 */
#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000002 */
#define FMC_SDCRx_NR_Pos           (2U)
#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!< Number of row address bits */
#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000004 */
#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000008 */
#define FMC_SDCRx_MWID_Pos         (4U)
#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!< Memory data bus width */
#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000010 */
#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000020 */
#define FMC_SDCRx_NB_Pos           (6U)
#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!< Number of internal banks */
#define FMC_SDCRx_CAS_Pos          (7U)
#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!< CAS latency */
#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000080 */
#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000100 */
#define FMC_SDCRx_WP_Pos           (9U)
#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!< Write protection */
#define FMC_SDCRx_SDCLK_Pos        (10U)
#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!< SDRAM clock configuration */
#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000400 */
#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000800 */
#define FMC_SDCRx_RBURST_Pos       (12U)
#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!< Read burst */
#define FMC_SDCRx_RPIPE_Pos        (13U)
#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!< Read pipe */
#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00002000 */
#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00004000 */

/******************  Bit definition for FMC_SDTRx(1,2) register  **************/
#define FMC_SDTRx_TMRD_Pos         (0U)
#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!< Load mode register to active */
#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000001 */
#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000002 */
#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000004 */
#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000008 */
#define FMC_SDTRx_TXSR_Pos         (4U)
#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<Exit self-refresh delay */
#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000010 */
#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000020 */
#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000040 */
#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000080 */
#define FMC_SDTRx_TRAS_Pos         (8U)
#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!< Self refresh time */
#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000100 */
#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000200 */
#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000400 */
#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000800 */
#define FMC_SDTRx_TRC_Pos          (12U)
#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!< Row cycle delay */
#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00001000 */
#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00002000 */
#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00004000 */
#define FMC_SDTRx_TRC_3            (0x8UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00008000 */
#define FMC_SDTRx_TWR_Pos          (16U)
#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!< Recovery delay */
#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00010000 */
#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00020000 */
#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00040000 */
#define FMC_SDTRx_TWR_3            (0x8UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00080000 */
#define FMC_SDTRx_TRP_Pos          (20U)
#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!< Row precharge delay */
#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00100000 */
#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00200000 */
#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00400000 */
#define FMC_SDTRx_TRP_3            (0x8UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00800000 */
#define FMC_SDTRx_TRCD_Pos         (24U)
#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!< Row to column delay */
#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x01000000 */
#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x02000000 */
#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x04000000 */
#define FMC_SDTRx_TRCD_3           (0x8UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x08000000 */

/******************  Bit definition for FMC_SDCMR register  *******************/
#define FMC_SDCMR_MODE_Pos         (0U)
#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!< Command mode */
#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
#define FMC_SDCMR_CTB2_Pos         (3U)
#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!< Command target bank 2 */
#define FMC_SDCMR_CTB1_Pos         (4U)
#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!< Command target bank 1 */
#define FMC_SDCMR_NRFS_Pos         (5U)
#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!< Number of auto-refresh */
#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
#define FMC_SDCMR_MRD_Pos          (9U)
#define FMC_SDCMR_MRD_Msk          (0x3FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x007FFE00 */
#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!< Mode register definition */

/******************  Bit definition for FMC_SDRTR register  *******************/
#define FMC_SDRTR_CRE_Pos          (0U)
#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!< Clear refresh error flag */
#define FMC_SDRTR_COUNT_Pos        (1U)
#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!< Refresh timer count */
#define FMC_SDRTR_REIE_Pos         (14U)
#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!< RES interrupt enable */

/******************  Bit definition for FMC_SDSR register  ********************/
#define FMC_SDSR_RE_Pos            (0U)
#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!< Refresh error flag */
#define FMC_SDSR_MODES1_Pos        (1U)
#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!< Status mode for bank 1 */
#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
#define FMC_SDSR_MODES2_Pos        (3U)
#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!< Status mode for bank 2 */
#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */


/******************************************************************************/
/*                                                                            */
/*                       Graphic MMU (GFXMMU)                                 */
/*                                                                            */
/******************************************************************************/
/****************** Bits definition for GFXMMU_CR register ********************/
#define GFXMMU_CR_B0OIE_Pos                (0U)
#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)      /*!< 0x00000001 */
#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
#define GFXMMU_CR_B1OIE_Pos                (1U)
#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)      /*!< 0x00000002 */
#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
#define GFXMMU_CR_B2OIE_Pos                (2U)
#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)      /*!< 0x00000004 */
#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
#define GFXMMU_CR_B3OIE_Pos                (3U)
#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)      /*!< 0x00000008 */
#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
#define GFXMMU_CR_AMEIE_Pos                (4U)
#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)      /*!< 0x00000010 */
#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
#define GFXMMU_CR_BS_Pos                   (6U)
#define GFXMMU_CR_BS_Msk                   (0x1UL << GFXMMU_CR_BS_Pos)         /*!< 0x00000040 */
#define GFXMMU_CR_BS                       GFXMMU_CR_BS_Msk                    /*!< Block size */
#define GFXMMU_CR_ATE_Pos                  (15U)
#define GFXMMU_CR_ATE_Msk                  (0x1UL << GFXMMU_CR_ATE_Pos)        /*!< 0x00008000 */
#define GFXMMU_CR_ATE                      GFXMMU_CR_ATE_Msk                   /*!< Address translation enable */
#define GFXMMU_CR_B0PE_Pos                 (24U)
#define GFXMMU_CR_B0PE_Msk                 (0x1UL << GFXMMU_CR_B0PE_Pos)       /*!< 0x01000000 */
#define GFXMMU_CR_B0PE                     GFXMMU_CR_B0PE_Msk                  /*!< Buffer 0 packing enable */
#define GFXMMU_CR_B0PM_Pos                 (25U)
#define GFXMMU_CR_B0PM_Msk                 (0x1UL << GFXMMU_CR_B0PM_Pos)       /*!< 0x02000000 */
#define GFXMMU_CR_B0PM                     GFXMMU_CR_B0PM_Msk                  /*!< Buffer 0 packing mode */
#define GFXMMU_CR_B1PE_Pos                 (26U)
#define GFXMMU_CR_B1PE_Msk                 (0x1UL << GFXMMU_CR_B1PE_Pos)       /*!< 0x04000000 */
#define GFXMMU_CR_B1PE                     GFXMMU_CR_B1PE_Msk                  /*!< Buffer 1 packing enable */
#define GFXMMU_CR_B1PM_Pos                 (27U)
#define GFXMMU_CR_B1PM_Msk                 (0x1UL << GFXMMU_CR_B1PM_Pos)       /*!< 0x08000000 */
#define GFXMMU_CR_B1PM                     GFXMMU_CR_B1PM_Msk                  /*!< Buffer 1 packing mode */
#define GFXMMU_CR_B2PE_Pos                 (28U)
#define GFXMMU_CR_B2PE_Msk                 (0x1UL << GFXMMU_CR_B2PE_Pos)       /*!< 0x10000000 */
#define GFXMMU_CR_B2PE                     GFXMMU_CR_B2PE_Msk                  /*!< Buffer 0 packing enable */
#define GFXMMU_CR_B2PM_Pos                 (29U)
#define GFXMMU_CR_B2PM_Msk                 (0x1UL << GFXMMU_CR_B2PM_Pos)       /*!< 0x20000000 */
#define GFXMMU_CR_B2PM                     GFXMMU_CR_B2PM_Msk                  /*!< Buffer 0 packing mode */
#define GFXMMU_CR_B3PE_Pos                 (30U)
#define GFXMMU_CR_B3PE_Msk                 (0x1UL << GFXMMU_CR_B3PE_Pos)       /*!< 0x40000000 */
#define GFXMMU_CR_B3PE                     GFXMMU_CR_B3PE_Msk                  /*!< Buffer 0 packing enable */
#define GFXMMU_CR_B3PM_Pos                 (31U)
#define GFXMMU_CR_B3PM_Msk                 (0x1UL << GFXMMU_CR_B3PM_Pos)       /*!< 0x80000000 */
#define GFXMMU_CR_B3PM                     GFXMMU_CR_B3PM_Msk                  /*!< Buffer 0 packing mode */

/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos                 (0U)
#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)       /*!< 0x00000001 */
#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
#define GFXMMU_SR_B1OF_Pos                 (1U)
#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)       /*!< 0x00000002 */
#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
#define GFXMMU_SR_B2OF_Pos                 (2U)
#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)       /*!< 0x00000004 */
#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
#define GFXMMU_SR_B3OF_Pos                 (3U)
#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)       /*!< 0x00000008 */
#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
#define GFXMMU_SR_AMEF_Pos                 (4U)
#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)       /*!< 0x00000010 */
#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AXI master error flag */

/****************** Bits definition for GFXMMU_FCR register *******************/
#define GFXMMU_FCR_CB0OF_Pos               (0U)
#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)     /*!< 0x00000001 */
#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
#define GFXMMU_FCR_CB1OF_Pos               (1U)
#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)     /*!< 0x00000002 */
#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
#define GFXMMU_FCR_CB2OF_Pos               (2U)
#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)     /*!< 0x00000004 */
#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
#define GFXMMU_FCR_CB3OF_Pos               (3U)
#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)     /*!< 0x00000008 */
#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
#define GFXMMU_FCR_CAMEF_Pos               (4U)
#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)     /*!< 0x00000010 */
#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

/****************** Bits definition for GFXMMU_DVR register *******************/
#define GFXMMU_DVR_DV_Pos                  (0U)
#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

/****************** Bits definition for GFXMMU_DAR register *******************/
#define GFXMMU_DAR_DA_Pos                  (0U)
#define GFXMMU_DAR_DA_Msk                  (0xFFUL << GFXMMU_DVR_DA_Pos)       /*!< 0x000000FF */
#define GFXMMU_DAR_DA                      GFXMMU_DVR_DA_Msk                   /*!< DA[7:0] bits (Default alpha) */

/****************** Bits definition for GFXMMU_B0CR register ******************/
#define GFXMMU_B0CR_PBO_Pos                (4U)
#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)  /*!< 0x007FFFF0 */
#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B0CR_PBBA_Pos               (23U)
#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)   /*!< 0xFF800000 */
#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

/****************** Bits definition for GFXMMU_B1CR register ******************/
#define GFXMMU_B1CR_PBO_Pos                (4U)
#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)  /*!< 0x007FFFF0 */
#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B1CR_PBBA_Pos               (23U)
#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)   /*!< 0xFF800000 */
#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

/****************** Bits definition for GFXMMU_B2CR register ******************/
#define GFXMMU_B2CR_PBO_Pos                (4U)
#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)  /*!< 0x007FFFF0 */
#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B2CR_PBBA_Pos               (23U)
#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)   /*!< 0xFF800000 */
#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

/****************** Bits definition for GFXMMU_B3CR register ******************/
#define GFXMMU_B3CR_PBO_Pos                (4U)
#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)  /*!< 0x007FFFF0 */
#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B3CR_PBBA_Pos               (23U)
#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)   /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos                (0U)
#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)      /*!< 0x00000001 */
#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
#define GFXMMU_LUTxL_FVB_Pos               (8U)
#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)    /*!< 0x0000FF00 */
#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
#define GFXMMU_LUTxL_LVB_Pos               (16U)
#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)    /*!< 0x00FF0000 */
#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

/****************** Bits definition for GFXMMU_LUTxH register *****************/
#define GFXMMU_LUTxH_LO_Pos                (0U)
#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)  /*!< 0x0003FFFF */
#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[17:0] bits (Line offset) */


/******************************************************************************/
/*                                                                            */
/*                       Graphic Timer (GFXTIM)                               */
/*                                                                            */
/******************************************************************************/
/******************  Bits definition for GFXTIM_CR register  ******************/
#define GFXTIM_CR_TES_Pos              (0U)
#define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
#define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
#define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
#define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */

#define GFXTIM_CR_TEPOL_Pos            (4U)
#define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
#define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk

#define GFXTIM_CR_SYNCS_Pos            (8U)
#define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
#define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
#define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
#define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */

#define GFXTIM_CR_FCCOE_Pos            (16U)
#define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
#define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk

#define GFXTIM_CR_LCCOE_Pos            (17U)
#define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
#define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk

/******************  Bits definition for GFXTIM_CR register  ******************/
#define GFXTIM_CGCR_LCS_Pos           (0U)
#define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
#define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
#define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
#define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
#define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */

#define GFXTIM_CGCR_LCCCS_Pos         (4U)
#define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
#define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk

#define GFXTIM_CGCR_LCCFR_Pos         (8U)
#define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
#define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk

#define GFXTIM_CGCR_LCCHRS_Pos        (12U)
#define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
#define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
#define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
#define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
#define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */

#define GFXTIM_CGCR_FCS_Pos           (16U)
#define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
#define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
#define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
#define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
#define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */

#define GFXTIM_CGCR_FCCCS_Pos         (20U)
#define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
#define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
#define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
#define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
#define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */

#define GFXTIM_CGCR_FCCFR_Pos         (24U)
#define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
#define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk

#define GFXTIM_CGCR_FCCHRS_Pos        (28U)
#define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
#define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
#define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
#define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
#define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */

/******************  Bits definition for GFXTIM_TCR register  *****************/
#define GFXTIM_TCR_AFCEN_Pos           (0U)
#define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
#define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk

#define GFXTIM_TCR_FAFCR_Pos           (1U)
#define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
#define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk

#define GFXTIM_TCR_ALCEN_Pos           (4U)
#define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
#define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk

#define GFXTIM_TCR_FALCR_Pos           (5U)
#define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
#define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk

#define GFXTIM_TCR_RFC1EN_Pos          (16U)
#define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
#define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk

#define GFXTIM_TCR_RFC1CM_Pos          (17U)
#define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
#define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk

#define GFXTIM_TCR_FRFC1R_Pos          (18U)
#define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
#define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk

#define GFXTIM_TCR_RFC2EN_Pos          (20U)
#define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
#define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk

#define GFXTIM_TCR_RFC2CM_Pos          (21U)
#define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
#define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk

#define GFXTIM_TCR_FRFC2R_Pos          (22U)
#define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
#define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk

/******************  Bits definition for GFXTIM_TDR register  *****************/
#define GFXTIM_TDR_AFCDIS_Pos          (0U)
#define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
#define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk

#define GFXTIM_TDR_ALCDIS_Pos          (4U)
#define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
#define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk

#define GFXTIM_TDR_RFC1DIS_Pos         (16U)
#define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
#define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk

#define GFXTIM_TDR_RFC2DIS_Pos         (20U)
#define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
#define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk

/******************  Bits definition for GFXTIM_EVCR register  ****************/
#define GFXTIM_EVCR_EV1EN_Pos          (0U)
#define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
#define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk

#define GFXTIM_EVCR_EV2EN_Pos          (1U)
#define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
#define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk

#define GFXTIM_EVCR_EV3EN_Pos          (2U)
#define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
#define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk

#define GFXTIM_EVCR_EV4EN_Pos          (3U)
#define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
#define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk

/******************  Bits definition for GFXTIM_EVSR register  ****************/
#define GFXTIM_EVSR_LES1_Pos           (0U)
#define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
#define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
#define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
#define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
#define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */

#define GFXTIM_EVSR_FES1_Pos           (4U)
#define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
#define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
#define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
#define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
#define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */

#define GFXTIM_EVSR_LES2_Pos           (8U)
#define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
#define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
#define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
#define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
#define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */

#define GFXTIM_EVSR_FES2_Pos           (12U)
#define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
#define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
#define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
#define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
#define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */

#define GFXTIM_EVSR_LES3_Pos           (16U)
#define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
#define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
#define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
#define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
#define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */

#define GFXTIM_EVSR_FES3_Pos           (20U)
#define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
#define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
#define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
#define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
#define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */

#define GFXTIM_EVSR_LES4_Pos           (24U)
#define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
#define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
#define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
#define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
#define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */

#define GFXTIM_EVSR_FES4_Pos           (28U)
#define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
#define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
#define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
#define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
#define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */

/******************  Bits definition for GFXTIM_WDGTCR register  **************/
#define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
#define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
#define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk

#define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
#define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
#define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk

#define GFXTIM_WDGTCR_WDGS_Pos         (2U)
#define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
#define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk

#define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
#define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
#define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
#define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
#define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */

#define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
#define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
#define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
#define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
#define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
#define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
#define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */

#define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
#define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
#define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk

/******************  Bits definition for GFXTIM_ISR register  *****************/
#define GFXTIM_ISR_AFCOF_Pos           (0U)
#define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
#define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk

#define GFXTIM_ISR_ALCOF_Pos           (1U)
#define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
#define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk

#define GFXTIM_ISR_TEF_Pos             (2U)
#define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
#define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk

#define GFXTIM_ISR_AFCC1F_Pos          (4U)
#define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
#define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk

#define GFXTIM_ISR_ALCC1F_Pos          (8U)
#define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
#define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk

#define GFXTIM_ISR_ALCC2F_Pos          (9U)
#define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
#define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk

#define GFXTIM_ISR_RFC1RF_Pos          (12U)
#define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
#define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk

#define GFXTIM_ISR_RFC2RF_Pos          (13U)
#define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
#define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk

#define GFXTIM_ISR_EV1F_Pos            (16U)
#define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
#define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk

#define GFXTIM_ISR_EV2F_Pos            (17U)
#define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
#define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk

#define GFXTIM_ISR_EV3F_Pos            (18U)
#define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
#define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk

#define GFXTIM_ISR_EV4F_Pos            (19U)
#define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
#define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk

#define GFXTIM_ISR_WDGAF_Pos           (24U)
#define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
#define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk

#define GFXTIM_ISR_WDGPF_Pos           (25U)
#define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
#define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk

/******************  Bits definition for GFXTIM_ICR register  *****************/
#define GFXTIM_ICR_CAFCOF_Pos          (0U)
#define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
#define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk

#define GFXTIM_ICR_CALCOF_Pos          (1U)
#define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
#define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk

#define GFXTIM_ICR_CTEF_Pos            (2U)
#define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
#define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk

#define GFXTIM_ICR_CAFCC1F_Pos         (4U)
#define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
#define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk

#define GFXTIM_ICR_CALCC1F_Pos         (8U)
#define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
#define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk

#define GFXTIM_ICR_CALCC2F_Pos         (9U)
#define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
#define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk

#define GFXTIM_ICR_CRFC1RF_Pos         (12U)
#define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
#define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk

#define GFXTIM_ICR_CRFC2RF_Pos         (13U)
#define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
#define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk

#define GFXTIM_ICR_CEV1F_Pos           (16U)
#define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
#define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk

#define GFXTIM_ICR_CEV2F_Pos           (17U)
#define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
#define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk

#define GFXTIM_ICR_CEV3F_Pos           (18U)
#define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
#define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk

#define GFXTIM_ICR_CEV4F_Pos           (19U)
#define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
#define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk

#define GFXTIM_ICR_CWDGAF_Pos          (24U)
#define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
#define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk

#define GFXTIM_ICR_CWDGPF_Pos          (25U)
#define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
#define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk

/******************  Bits definition for GFXTIM_IER register  *****************/
#define GFXTIM_IER_AFCOIE_Pos          (0U)
#define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
#define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk

#define GFXTIM_IER_ALCOIE_Pos          (1U)
#define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
#define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk

#define GFXTIM_IER_TEIE_Pos            (2U)
#define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
#define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk

#define GFXTIM_IER_AFCC1IE_Pos         (4U)
#define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
#define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk

#define GFXTIM_IER_ALCC1IE_Pos         (8U)
#define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
#define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk

#define GFXTIM_IER_ALCC2IE_Pos         (9U)
#define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
#define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk

#define GFXTIM_IER_RFC1RIE_Pos         (12U)
#define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
#define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk

#define GFXTIM_IER_RFC2RIE_Pos         (13U)
#define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
#define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk

#define GFXTIM_IER_EV1IE_Pos           (16U)
#define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
#define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk

#define GFXTIM_IER_EV2IE_Pos           (17U)
#define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
#define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk

#define GFXTIM_IER_EV3IE_Pos           (18U)
#define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
#define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk

#define GFXTIM_IER_EV4IE_Pos           (19U)
#define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
#define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk

#define GFXTIM_IER_WDGAIE_Pos          (24U)
#define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
#define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk

#define GFXTIM_IER_WDGPIE_Pos          (25U)
#define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
#define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk

/******************  Bits definition for GFXTIM_TSR register  *****************/
#define GFXTIM_TSR_AFCS_Pos            (0U)
#define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
#define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk

#define GFXTIM_TSR_ALCS_Pos            (4U)
#define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
#define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk

#define GFXTIM_TSR_RFC1S_Pos           (16U)
#define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
#define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk

#define GFXTIM_TSR_RFC2S_Pos           (20U)
#define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
#define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk

/******************  Bits definition for GFXTIM_LCCRR register  ***************/
#define GFXTIM_LCCRR_RELOAD_Pos        (0U)
#define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
#define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk

/******************  Bits definition for GFXTIM_FCCRR register  ***************/
#define GFXTIM_FCCRR_RELOAD_Pos        (0U)
#define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
#define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk

/******************  Bits definition for GFXTIM_ATR register  *****************/
#define GFXTIM_ATR_LINE_Pos            (0U)
#define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
#define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk

#define GFXTIM_ATR_FRAME_Pos           (12U)
#define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
#define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk

/******************  Bits definition for GFXTIM_AFCR register  ****************/
#define GFXTIM_AFCR_FRAME_Pos          (0U)
#define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
#define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk

/******************  Bits definition for GFXTIM_ALCR register  ****************/
#define GFXTIM_ALCR_LINE_Pos           (0U)
#define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
#define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk

/******************  Bits definition for GFXTIM_AFCC1R register  **************/
#define GFXTIM_AFCC1R_FRAME_Pos        (0U)
#define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
#define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk

/******************  Bits definition for GFXTIM_ALCC1R register  **************/
#define GFXTIM_ALCC1R_LINE_Pos         (0U)
#define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
#define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk

/******************  Bits definition for GFXTIM_ALCC2R register  **************/
#define GFXTIM_ALCC2R_LINE_Pos         (0U)
#define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
#define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk

/******************  Bits definition for GFXTIM_RFC1R register  ***************/
#define GFXTIM_RFC1R_FRAME_Pos         (0U)
#define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
#define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk

/******************  Bits definition for GFXTIM_RFC1RR register  **************/
#define GFXTIM_RFC1RR_FRAME_Pos        (0U)
#define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
#define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk

/******************  Bits definition for GFXTIM_RFC2R register  ***************/
#define GFXTIM_RFC2R_FRAME_Pos         (0U)
#define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
#define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk

/******************  Bits definition for GFXTIM_RFC2RR register  **************/
#define GFXTIM_RFC2RR_FRAME_Pos        (0U)
#define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
#define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk

/******************  Bits definition for GFXTIM_WDGCR register  ***************/
#define GFXTIM_WDGCR_VALUE_Pos         (0U)
#define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
#define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk

/******************  Bits definition for GFXTIM_WDGRR register  ***************/
#define GFXTIM_WDGRR_RELOAD_Pos        (0U)
#define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
#define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk

/******************  Bits definition for GFXTIM_WDGPAR register  **************/
#define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
#define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
#define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk

/******************  Bits definition for GFXTIM_HWCFGR register  **************/

/******************  Bits definition for GFXTIM_VERR register  ****************/
#define GFXTIM_VERR_MINREV_Pos         (0U)
#define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
#define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk

#define GFXTIM_VERR_MAJREV_Pos         (4U)
#define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
#define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk

/******************  Bits definition for GFXTIM_IPIDR register  ***************/
#define GFXTIM_IPIDR_ID_Pos            (0U)
#define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
#define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk

/******************  Bits definition for GFXTIM_SIDR register  ****************/
#define GFXTIM_SIDR_SID_Pos            (0U)
#define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
#define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk


/******************************************************************************/
/*                                                                            */
/*                       General Purpose IOs (GPIO)                           */
/*                                                                            */
/******************************************************************************/
/******************  Bits definition for GPIO_MODER register  *****************/
#define GPIO_MODER_MODE0_Pos           (0U)
#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos           (2U)
#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos           (4U)
#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos           (6U)
#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos           (8U)
#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos           (10U)
#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos           (12U)
#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos           (14U)
#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos           (16U)
#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos           (18U)
#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos          (20U)
#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos          (22U)
#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos          (24U)
#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos          (26U)
#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos          (28U)
#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos          (30U)
#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */

/******************  Bits definition for GPIO_OTYPER register  ****************/
#define GPIO_OTYPER_OT0_Pos            (0U)
#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos            (1U)
#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos            (2U)
#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos            (3U)
#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos            (4U)
#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos            (5U)
#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos            (6U)
#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos            (7U)
#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos            (8U)
#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos            (9U)
#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos           (10U)
#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos           (11U)
#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos           (12U)
#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos           (13U)
#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos           (14U)
#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos           (15U)
#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

/******************  Bits definition for GPIO_OSPEEDR register  ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */

/******************  Bits definition for GPIO_PUPDR register  *****************/
#define GPIO_PUPDR_PUPD0_Pos           (0U)
#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos           (2U)
#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos           (4U)
#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos           (6U)
#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos           (8U)
#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos           (10U)
#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos           (12U)
#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos           (14U)
#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos           (16U)
#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos           (18U)
#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos          (20U)
#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos          (22U)
#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos          (24U)
#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos          (26U)
#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos          (28U)
#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos          (30U)
#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */

/******************  Bits definition for GPIO_IDR register  *******************/
#define GPIO_IDR_ID0_Pos               (0U)
#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos               (1U)
#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos               (2U)
#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos               (3U)
#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos               (4U)
#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos               (5U)
#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos               (6U)
#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos               (7U)
#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos               (8U)
#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos               (9U)
#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos              (10U)
#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos              (11U)
#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos              (12U)
#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos              (13U)
#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos              (14U)
#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos              (15U)
#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

/******************  Bits definition for GPIO_ODR register  *******************/
#define GPIO_ODR_OD0_Pos               (0U)
#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos               (1U)
#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos               (2U)
#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos               (3U)
#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos               (4U)
#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos               (5U)
#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos               (6U)
#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos               (7U)
#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos               (8U)
#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos               (9U)
#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos              (10U)
#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos              (11U)
#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos              (12U)
#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos              (13U)
#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos              (14U)
#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos              (15U)
#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

/******************  Bits definition for GPIO_BSRR register  ******************/
#define GPIO_BSRR_BS0_Pos              (0U)
#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos              (1U)
#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos              (2U)
#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos              (3U)
#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos              (4U)
#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos              (5U)
#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos              (6U)
#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos              (7U)
#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos              (8U)
#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos              (9U)
#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos             (10U)
#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos             (11U)
#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos             (12U)
#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos             (13U)
#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos             (14U)
#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos             (15U)
#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos              (16U)
#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos              (17U)
#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos              (18U)
#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos              (19U)
#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos              (20U)
#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos              (21U)
#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos              (22U)
#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos              (23U)
#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos              (24U)
#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos              (25U)
#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos             (26U)
#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos             (27U)
#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos             (28U)
#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos             (29U)
#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos             (30U)
#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos             (31U)
#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos             (0U)
#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos             (1U)
#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos             (2U)
#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos             (3U)
#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos             (4U)
#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos             (5U)
#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos             (6U)
#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos             (7U)
#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos             (8U)
#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos             (9U)
#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos            (10U)
#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos            (11U)
#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos            (12U)
#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos            (13U)
#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos            (14U)
#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos            (15U)
#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos             (16U)
#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos           (0U)
#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos           (4U)
#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos           (8U)
#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos           (12U)
#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos           (16U)
#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos           (20U)
#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos           (24U)
#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos           (28U)
#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */

/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos           (0U)
#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos           (4U)
#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos          (8U)
#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos          (12U)
#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos          (16U)
#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos          (20U)
#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos          (24U)
#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos          (28U)
#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */

/******************  Bits definition for GPIO_BRR register  ******************/
#define GPIO_BRR_BR0_Pos               (0U)
#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos               (1U)
#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos               (2U)
#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos               (3U)
#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos               (4U)
#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos               (5U)
#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos               (6U)
#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos               (7U)
#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos               (8U)
#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos               (9U)
#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos              (10U)
#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos              (11U)
#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos              (12U)
#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos              (13U)
#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos              (14U)
#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos              (15U)
#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk

/******************************************************************************/
/*                                                                            */
/*                                    HASH                                    */
/*                                                                            */
/******************************************************************************/
/******************  Bits definition for HASH_CR register  ********************/
#define HASH_CR_INIT_Pos                    (2U)
#define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
#define HASH_CR_INIT                        HASH_CR_INIT_Msk
#define HASH_CR_DMAE_Pos                    (3U)
#define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
#define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
#define HASH_CR_DATATYPE_Pos                (4U)
#define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
#define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
#define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
#define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
#define HASH_CR_MODE_Pos                    (6U)
#define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
#define HASH_CR_MODE                        HASH_CR_MODE_Msk
#define HASH_CR_NBW_Pos                     (8U)
#define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
#define HASH_CR_NBW                         HASH_CR_NBW_Msk
#define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
#define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
#define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
#define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
#define HASH_CR_DINNE_Pos                   (12U)
#define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
#define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
#define HASH_CR_MDMAT_Pos                   (13U)
#define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
#define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
#define HASH_CR_LKEY_Pos                    (16U)
#define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
#define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
#define HASH_CR_ALGO_Pos                    (17U)
#define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
#define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
#define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
#define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
#define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
#define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */

/******************  Bits definition for HASH_STR register  *******************/
#define HASH_STR_NBLW_Pos                   (0U)
#define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
#define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
#define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
#define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
#define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
#define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
#define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
#define HASH_STR_DCAL_Pos                   (8U)
#define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
#define HASH_STR_DCAL                       HASH_STR_DCAL_Msk

/******************  Bits definition for HASH_IMR register  *******************/
#define HASH_IMR_DINIE_Pos                  (0U)
#define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
#define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
#define HASH_IMR_DCIE_Pos                   (1U)
#define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
#define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk

/******************  Bits definition for HASH_SR register  ********************/
#define HASH_SR_DINIS_Pos                   (0U)
#define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
#define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
#define HASH_SR_DCIS_Pos                    (1U)
#define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
#define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
#define HASH_SR_DMAS_Pos                    (2U)
#define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
#define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
#define HASH_SR_BUSY_Pos                    (3U)
#define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
#define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
#define HASH_SR_NBWP_Pos                    (9U)
#define HASH_SR_NBWP_Msk                    (0x1FUL << HASH_SR_NBWP_Pos)            /*!< 0x00003E00 */
#define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
#define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
#define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
#define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
#define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
#define HASH_SR_NBWP_4                      (0x10UL << HASH_SR_NBWP_Pos)            /*!< 0x00002000 */
#define HASH_SR_NBWE_Pos                    (16U)
#define HASH_SR_NBWE_Msk                    (0x1FUL << HASH_SR_NBWE_Pos)            /*!< 0x001F0000 */
#define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
#define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
#define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
#define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
#define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
#define HASH_SR_NBWE_4                      (0x10UL << HASH_SR_NBWE_Pos)            /*!< 0x00100000 */
#define HASH_SR_DINNE_Pos                   (15U)
#define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
#define HASH_SR_DINNE                       HASH_SR_DINNE_Msk

/******************************************************************************/
/*                                                                            */
/*                      Inter-integrated Circuit Interface (I2C)              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I2C_CR1 register  ********************/
#define I2C_CR1_PE_Pos               (0U)
#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos             (1U)
#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos             (2U)
#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos           (3U)
#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos           (4U)
#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos           (5U)
#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos             (6U)
#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos            (7U)
#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos              (8U)
#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos           (12U)
#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos            (13U)
#define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos          (14U)
#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos          (15U)
#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos              (16U)
#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos        (17U)
#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos            (18U)
#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos             (19U)
#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos           (20U)
#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos           (21U)
#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos          (22U)
#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos            (23U)
#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
#define I2C_CR1_FMP_Pos              (24U)
#define I2C_CR1_FMP_Msk              (0x1UL << I2C_CR1_FMP_Pos)                /*!< 0x01000000 */
#define I2C_CR1_FMP                  I2C_CR1_FMP_Msk                           /*!< FMP enable */
#define I2C_CR1_ADDRACLR_Pos         (30U)
#define I2C_CR1_ADDRACLR_Msk         (0x1UL << I2C_CR1_ADDRACLR_Pos)           /*!< 0x40000000 */
#define I2C_CR1_ADDRACLR             I2C_CR1_ADDRACLR_Msk                      /*!< ADDRACLR enable */
#define I2C_CR1_STOPFACLR_Pos        (31U)
#define I2C_CR1_STOPFACLR_Msk        (0x1UL << I2C_CR1_STOPFACLR_Pos)          /*!< 0x80000000 */
#define I2C_CR1_STOPFACLR            I2C_CR1_STOPFACLR_Msk                     /*!< STOPFACLR enable */

/******************  Bit definition for I2C_CR2 register  *********************/
#define I2C_CR2_SADD_Pos             (0U)
#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos           (10U)
#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos            (11U)
#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos          (12U)
#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos            (13U)
#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
#define I2C_CR2_STOP_Pos             (14U)
#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos             (15U)
#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos           (16U)
#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos           (24U)
#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos          (25U)
#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos          (26U)
#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

/*******************  Bit definition for I2C_OAR1 register  *******************/
#define I2C_OAR1_OA1_Pos             (0U)
#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos         (10U)
#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos           (15U)
#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

/*******************  Bit definition for I2C_OAR2 register  *******************/
#define I2C_OAR2_OA2_Pos             (1U)
#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos          (8U)
#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
#define I2C_OAR2_OA2MASK01_Pos       (8U)
#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
#define I2C_OAR2_OA2MASK02_Pos       (9U)
#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos       (8U)
#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos       (10U)
#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos       (8U)
#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos       (9U)
#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
#define I2C_OAR2_OA2MASK07_Pos       (8U)
#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
#define I2C_OAR2_OA2EN_Pos           (15U)
#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

/*******************  Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL_Pos         (0U)
#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos         (8U)
#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos       (16U)
#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos       (20U)
#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos        (28U)
#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

/******************* Bit definition for I2C_TIMEOUTR register *****************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

/******************  Bit definition for I2C_ISR register  *********************/
#define I2C_ISR_TXE_Pos              (0U)
#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos             (1U)
#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos             (2U)
#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos             (3U)
#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF_Pos            (4U)
#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos            (5U)
#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
#define I2C_ISR_TC_Pos               (6U)
#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos              (7U)
#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos             (8U)
#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
#define I2C_ISR_ARLO_Pos             (9U)
#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos              (10U)
#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos           (11U)
#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos          (12U)
#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos            (13U)
#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos             (15U)
#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
#define I2C_ISR_DIR_Pos              (16U)
#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos          (17U)
#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

/******************  Bit definition for I2C_ICR register  *********************/
#define I2C_ICR_ADDRCF_Pos           (3U)
#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos           (4U)
#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos           (5U)
#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos           (8U)
#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos           (9U)
#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos            (10U)
#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos            (11U)
#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos         (12U)
#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos          (13U)
#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

/******************  Bit definition for I2C_PECR register  ********************/
#define I2C_PECR_PEC_Pos             (0U)
#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

/******************  Bit definition for I2C_RXDR register  ********************/
#define I2C_RXDR_RXDATA_Pos          (0U)
#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

/******************  Bit definition for I2C_TXDR register  ********************/
#define I2C_TXDR_TXDATA_Pos          (0U)
#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

/******************************************************************************/
/*                                                                            */
/*             Improved Inter-integrated Circuit Interface (I3C)              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I3C_CR register  *********************/
#define I3C_CR_DCNT_Pos                     (0U)
#define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
#define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
#define I3C_CR_RNW_Pos                      (16U)
#define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
#define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
#define I3C_CR_CCC_Pos                      (16U)
#define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
#define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
#define I3C_CR_ADD_Pos                      (17U)
#define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
#define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
#define I3C_CR_MTYPE_Pos                    (27U)
#define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
#define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
#define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
#define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
#define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
#define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
#define I3C_CR_MEND_Pos                     (31U)
#define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
#define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */

/*******************  Bit definition for I3C_CFGR register  *******************/
#define I3C_CFGR_EN_Pos                     (0U)
#define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
#define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
#define I3C_CFGR_CRINIT_Pos                 (1U)
#define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
#define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
#define I3C_CFGR_NOARBH_Pos                 (2U)
#define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
#define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
#define I3C_CFGR_RSTPTRN_Pos                (3U)
#define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
#define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
#define I3C_CFGR_EXITPTRN_Pos               (4U)
#define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
#define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
#define I3C_CFGR_HKSDAEN_Pos                (5U)
#define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
#define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
#define I3C_CFGR_HJACK_Pos                  (7U)
#define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
#define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
#define I3C_CFGR_RXDMAEN_Pos                (8U)
#define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
#define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
#define I3C_CFGR_RXFLUSH_Pos                (9U)
#define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
#define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
#define I3C_CFGR_RXTHRES_Pos                (10U)
#define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
#define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
#define I3C_CFGR_TXDMAEN_Pos                (12U)
#define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
#define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
#define I3C_CFGR_TXFLUSH_Pos                (13U)
#define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
#define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
#define I3C_CFGR_TXTHRES_Pos                (14U)
#define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
#define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
#define I3C_CFGR_SDMAEN_Pos                 (16U)
#define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
#define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
#define I3C_CFGR_SFLUSH_Pos                 (17U)
#define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
#define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
#define I3C_CFGR_SMODE_Pos                  (18U)
#define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
#define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
#define I3C_CFGR_TMODE_Pos                  (19U)
#define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
#define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
#define I3C_CFGR_CDMAEN_Pos                 (20U)
#define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
#define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
#define I3C_CFGR_CFLUSH_Pos                 (21U)
#define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
#define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
#define I3C_CFGR_TSFSET_Pos                 (30U)
#define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
#define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */

/*******************  Bit definition for I3C_RDR register  ********************/
#define I3C_RDR_RDB0_Pos                    (0U)
#define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
#define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */

/******************  Bit definition for I3C_RDWR register  ********************/
#define I3C_RDWR_RDBx_Pos                   (0U)
#define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
#define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
#define I3C_RDWR_RDB0_Pos                   (0U)
#define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
#define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
#define I3C_RDWR_RDB1_Pos                   (8U)
#define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
#define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
#define I3C_RDWR_RDB2_Pos                   (16U)
#define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
#define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
#define I3C_RDWR_RDB3_Pos                   (24U)
#define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
#define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */

/*******************  Bit definition for I3C_TDR register  ********************/
#define I3C_TDR_TDB0_Pos                    (0U)
#define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
#define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */

/******************  Bit definition for I3C_TDWR register  ********************/
#define I3C_TDWR_TDBx_Pos                   (0U)
#define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
#define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
#define I3C_TDWR_TDB0_Pos                   (0U)
#define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
#define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
#define I3C_TDWR_TDB1_Pos                   (8U)
#define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
#define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
#define I3C_TDWR_TDB2_Pos                   (16U)
#define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
#define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
#define I3C_TDWR_TDB3_Pos                   (24U)
#define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
#define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */

/*******************  Bit definition for I3C_IBIDR register  ******************/
#define I3C_IBIDR_IBIDBx_Pos                (0U)
#define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
#define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
#define I3C_IBIDR_IBIDB0_Pos                (0U)
#define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
#define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
#define I3C_IBIDR_IBIDB1_Pos                (8U)
#define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
#define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
#define I3C_IBIDR_IBIDB2_Pos                (16U)
#define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
#define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
#define I3C_IBIDR_IBIDB3_Pos                (24U)
#define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
#define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */

/******************  Bit definition for I3C_TGTTDR register  ******************/
#define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
#define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
#define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
#define I3C_TGTTDR_PRELOAD_Pos              (16U)
#define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
#define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */

/*******************  Bit definition for I3C_SR register  *********************/
#define I3C_SR_XDCNT_Pos                    (0U)
#define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
#define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
#define I3C_SR_ABT_Pos                      (17U)
#define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
#define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
#define I3C_SR_DIR_Pos                      (18U)
#define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
#define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
#define I3C_SR_MID_Pos                      (24U)
#define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
#define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */

/*******************  Bit definition for I3C_SER register  ********************/
#define I3C_SER_CODERR_Pos                  (0U)
#define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
#define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
#define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
#define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
#define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
#define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
#define I3C_SER_PERR_Pos                    (4U)
#define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
#define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
#define I3C_SER_STALL_Pos                   (5U)
#define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
#define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
#define I3C_SER_DOVR_Pos                    (6U)
#define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
#define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
#define I3C_SER_COVR_Pos                    (7U)
#define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
#define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
#define I3C_SER_ANACK_Pos                   (8U)
#define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
#define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
#define I3C_SER_DNACK_Pos                   (9U)
#define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
#define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
#define I3C_SER_DERR_Pos                    (10U)
#define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
#define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */

/*******************  Bit definition for I3C_RMR register  ********************/
#define I3C_RMR_IBIRDCNT_Pos                (0U)
#define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
#define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
#define I3C_RMR_RCODE_Pos                   (8U)
#define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
#define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
#define I3C_RMR_RADD_Pos                    (17U)
#define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
#define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */

/*******************  Bit definition for I3C_EVR register  ********************/
#define I3C_EVR_CFEF_Pos                    (0U)
#define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
#define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
#define I3C_EVR_TXFEF_Pos                   (1U)
#define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
#define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
#define I3C_EVR_CFNFF_Pos                   (2U)
#define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
#define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
#define I3C_EVR_SFNEF_Pos                   (3U)
#define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
#define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
#define I3C_EVR_TXFNFF_Pos                  (4U)
#define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
#define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
#define I3C_EVR_RXFNEF_Pos                  (5U)
#define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
#define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
#define I3C_EVR_TXLASTF_Pos                 (6U)
#define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
#define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
#define I3C_EVR_RXLASTF_Pos                 (7U)
#define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
#define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
#define I3C_EVR_FCF_Pos                     (9U)
#define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
#define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
#define I3C_EVR_RXTGTENDF_Pos               (10U)
#define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
#define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
#define I3C_EVR_ERRF_Pos                    (11U)
#define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
#define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
#define I3C_EVR_IBIF_Pos                    (15U)
#define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
#define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
#define I3C_EVR_IBIENDF_Pos                 (16U)
#define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
#define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
#define I3C_EVR_CRF_Pos                     (17U)
#define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
#define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
#define I3C_EVR_CRUPDF_Pos                  (18U)
#define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
#define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
#define I3C_EVR_HJF_Pos                     (19U)
#define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
#define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
#define I3C_EVR_WKPF_Pos                    (21U)
#define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
#define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
#define I3C_EVR_GETF_Pos                    (22U)
#define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
#define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
#define I3C_EVR_STAF_Pos                    (23U)
#define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
#define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
#define I3C_EVR_DAUPDF_Pos                  (24U)
#define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
#define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
#define I3C_EVR_MWLUPDF_Pos                 (25U)
#define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
#define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
#define I3C_EVR_MRLUPDF_Pos                 (26U)
#define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
#define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
#define I3C_EVR_RSTF_Pos                    (27U)
#define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
#define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
#define I3C_EVR_ASUPDF_Pos                  (28U)
#define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
#define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
#define I3C_EVR_INTUPDF_Pos                 (29U)
#define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
#define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
#define I3C_EVR_DEFF_Pos                    (30U)
#define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
#define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
#define I3C_EVR_GRPF_Pos                    (31U)
#define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
#define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */

/*******************  Bit definition for I3C_IER register  ********************/
#define I3C_IER_CFNFIE_Pos                  (2U)
#define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
#define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
#define I3C_IER_SFNEIE_Pos                  (3U)
#define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
#define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
#define I3C_IER_TXFNFIE_Pos                 (4U)
#define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
#define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
#define I3C_IER_RXFNEIE_Pos                 (5U)
#define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
#define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
#define I3C_IER_FCIE_Pos                    (9U)
#define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
#define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
#define I3C_IER_RXTGTENDIE_Pos              (10U)
#define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
#define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
#define I3C_IER_ERRIE_Pos                   (11U)
#define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
#define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
#define I3C_IER_IBIIE_Pos                   (15U)
#define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
#define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
#define I3C_IER_IBIENDIE_Pos                (16U)
#define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
#define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
#define I3C_IER_CRIE_Pos                    (17U)
#define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
#define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
#define I3C_IER_CRUPDIE_Pos                 (18U)
#define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
#define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
#define I3C_IER_HJIE_Pos                    (19U)
#define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
#define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
#define I3C_IER_WKPIE_Pos                   (21U)
#define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
#define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
#define I3C_IER_GETIE_Pos                   (22U)
#define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
#define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
#define I3C_IER_STAIE_Pos                   (23U)
#define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
#define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
#define I3C_IER_DAUPDIE_Pos                 (24U)
#define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
#define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
#define I3C_IER_MWLUPDIE_Pos                (25U)
#define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
#define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
#define I3C_IER_MRLUPDIE_Pos                (26U)
#define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
#define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
#define I3C_IER_RSTIE_Pos                   (27U)
#define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
#define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
#define I3C_IER_ASUPDIE_Pos                 (28U)
#define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
#define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
#define I3C_IER_INTUPDIE_Pos                (29U)
#define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
#define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
#define I3C_IER_DEFIE_Pos                   (30U)
#define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
#define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
#define I3C_IER_GRPIE_Pos                   (31U)
#define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
#define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */

/*******************  Bit definition for I3C_CEVR register  *******************/
#define I3C_CEVR_CFCF_Pos                   (9U)
#define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
#define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
#define I3C_CEVR_CRXTGTENDF_Pos             (10U)
#define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
#define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
#define I3C_CEVR_CERRF_Pos                  (11U)
#define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
#define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
#define I3C_CEVR_CIBIF_Pos                  (15U)
#define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
#define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
#define I3C_CEVR_CIBIENDF_Pos               (16U)
#define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
#define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
#define I3C_CEVR_CCRF_Pos                   (17U)
#define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
#define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
#define I3C_CEVR_CCRUPDF_Pos                (18U)
#define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
#define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
#define I3C_CEVR_CHJF_Pos                   (19U)
#define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
#define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
#define I3C_CEVR_CWKPF_Pos                  (21U)
#define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
#define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
#define I3C_CEVR_CGETF_Pos                  (22U)
#define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
#define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
#define I3C_CEVR_CSTAF_Pos                  (23U)
#define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
#define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
#define I3C_CEVR_CDAUPDF_Pos                (24U)
#define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
#define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
#define I3C_CEVR_CMWLUPDF_Pos               (25U)
#define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
#define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
#define I3C_CEVR_CMRLUPDF_Pos               (26U)
#define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
#define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
#define I3C_CEVR_CRSTF_Pos                  (27U)
#define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
#define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
#define I3C_CEVR_CASUPDF_Pos                (28U)
#define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
#define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
#define I3C_CEVR_CINTUPDF_Pos               (29U)
#define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
#define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
#define I3C_CEVR_CDEFF_Pos                  (30U)
#define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
#define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
#define I3C_CEVR_CGRPF_Pos                  (31U)
#define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
#define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */

/******************  Bit definition for I3C_DEVR0 register  *******************/
#define I3C_DEVR0_DAVAL_Pos                 (0U)
#define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
#define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
#define I3C_DEVR0_DA_Pos                    (1U)
#define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
#define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
#define I3C_DEVR0_IBIEN_Pos                 (16U)
#define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
#define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
#define I3C_DEVR0_CREN_Pos                  (17U)
#define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
#define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
#define I3C_DEVR0_HJEN_Pos                  (19U)
#define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
#define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
#define I3C_DEVR0_AS_Pos                    (20U)
#define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
#define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
#define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
#define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
#define I3C_DEVR0_RSTACT_Pos                (22U)
#define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
#define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
#define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
#define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
#define I3C_DEVR0_RSTVAL_Pos                (24U)
#define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
#define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */

/******************  Bit definition for I3C_DEVRX register  *******************/
#define I3C_DEVRX_DA_Pos                    (1U)
#define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
#define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
#define I3C_DEVRX_IBIACK_Pos                (16U)
#define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
#define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
#define I3C_DEVRX_CRACK_Pos                 (17U)
#define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
#define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
#define I3C_DEVRX_IBIDEN_Pos                (18U)
#define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
#define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
#define I3C_DEVRX_SUSP_Pos                  (19U)
#define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
#define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
#define I3C_DEVRX_DIS_Pos                   (31U)
#define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
#define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */

/******************  Bit definition for I3C_MAXRLR register  ******************/
#define I3C_MAXRLR_MRL_Pos                  (0U)
#define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
#define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
#define I3C_MAXRLR_IBIP_Pos                 (16U)
#define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
#define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
#define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
#define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
#define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */

/******************  Bit definition for I3C_MAXWLR register  ******************/
#define I3C_MAXWLR_MWL_Pos                  (0U)
#define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
#define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */

/****************  Bit definition for I3C_TIMINGR0 register  ******************/
#define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
#define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
#define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
#define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
#define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
#define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
#define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
#define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
#define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
#define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
#define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
#define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */

/****************  Bit definition for I3C_TIMINGR1 register  ******************/
#define I3C_TIMINGR1_AVAL_Pos               (0U)
#define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
#define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
#define I3C_TIMINGR1_ASNCR_Pos              (8U)
#define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
#define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
#define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
#define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
#define I3C_TIMINGR1_FREE_Pos               (16U)
#define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
#define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
#define I3C_TIMINGR1_SDA_HD_Pos             (28U)
#define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
#define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */

/****************  Bit definition for I3C_TIMINGR2 register  ******************/
#define I3C_TIMINGR2_STALLT_Pos             (0U)
#define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x00000001 */
#define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
#define I3C_TIMINGR2_STALLD_Pos             (1U)
#define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x00000002 */
#define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
#define I3C_TIMINGR2_STALLC_Pos             (2U)
#define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x00000004 */
#define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
#define I3C_TIMINGR2_STALLA_Pos             (3U)
#define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x00000008 */
#define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
#define I3C_TIMINGR2_STALL_Pos              (8U)
#define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x0000FF00 */
#define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */

/*******************  Bit definition for I3C_BCR register  ********************/
#define I3C_BCR_BCR_Pos                     (0U)
#define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
#define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
#define I3C_BCR_BCR0_Pos                    (0U)
#define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
#define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
#define I3C_BCR_BCR1_Pos                    (1U)
#define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
#define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
#define I3C_BCR_BCR2_Pos                    (2U)
#define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
#define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
#define I3C_BCR_BCR3_Pos                    (3U)
#define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
#define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
#define I3C_BCR_BCR4_Pos                    (4U)
#define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
#define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
#define I3C_BCR_BCR5_Pos                    (5U)
#define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
#define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
#define I3C_BCR_BCR6_Pos                    (6U)
#define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
#define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */

/*******************  Bit definition for I3C_DCR register  ********************/
#define I3C_DCR_DCR_Pos                     (0U)
#define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x000000FF */
#define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */

/*****************  Bit definition for I3C_GETCAPR register  ******************/
#define I3C_GETCAPR_CAPPEND_Pos             (14U)
#define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
#define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */

/*****************  Bit definition for I3C_CRCAPR register  *******************/
#define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
#define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
#define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
#define I3C_CRCAPR_CAPGRP_Pos               (9U)
#define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
#define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */

/****************  Bit definition for I3C_GETMXDSR register  ******************/
#define I3C_GETMXDSR_HOFFAS_Pos             (0U)
#define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
#define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
#define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
#define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
#define I3C_GETMXDSR_FMT_Pos                (8U)
#define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
#define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
#define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
#define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
#define I3C_GETMXDSR_RDTURN_Pos             (16U)
#define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
#define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
#define I3C_GETMXDSR_TSCO_Pos               (24U)
#define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
#define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */

/******************  Bit definition for I3C_EPIDR register  *******************/
#define I3C_EPIDR_MIPIID_Pos                (12U)
#define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
#define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
#define I3C_EPIDR_IDTSEL_Pos                (16U)
#define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
#define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
#define I3C_EPIDR_MIPIMID_Pos               (17U)
#define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
#define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */

/******************************************************************************/
/*                                                                            */
/*                           Independent WATCHDOG                             */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for IWDG_KR register  ********************/
#define IWDG_KR_KEY_Pos                (0U)
#define IWDG_KR_KEY_Msk                (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
#define IWDG_KR_KEY                    IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */

/*******************  Bit definition for IWDG_PR register  ********************/
#define IWDG_PR_PR_Pos                 (0U)
#define IWDG_PR_PR_Msk                 (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
#define IWDG_PR_PR                     IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
#define IWDG_PR_PR_0                   (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
#define IWDG_PR_PR_1                   (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
#define IWDG_PR_PR_2                   (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
#define IWDG_PR_PR_3                   (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */

/*******************  Bit definition for IWDG_RLR register  *******************/
#define IWDG_RLR_RL_Pos                (0U)
#define IWDG_RLR_RL_Msk                (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
#define IWDG_RLR_RL                    IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */

/*******************  Bit definition for IWDG_SR register  ********************/
#define IWDG_SR_PVU_Pos                (0U)
#define IWDG_SR_PVU_Msk                (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
#define IWDG_SR_PVU                    IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos                (1U)
#define IWDG_SR_RVU_Msk                (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
#define IWDG_SR_RVU                    IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos                (2U)
#define IWDG_SR_WVU_Msk                (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
#define IWDG_SR_WVU                    IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
#define IWDG_SR_EWU_Pos                (3U)
#define IWDG_SR_EWU_Msk                (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
#define IWDG_SR_EWU                    IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
#define IWDG_SR_ONF_Pos                (8U)
#define IWDG_SR_ONF_Msk                (0x1UL << IWDG_SR_ONF_Pos)              /*!< 0x00000100 */
#define IWDG_SR_ONF                    IWDG_SR_ONF_Msk                         /*!< Watchdog enable flag */
#define IWDG_SR_EWIF_Pos               (14U)
#define IWDG_SR_EWIF_Msk               (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
#define IWDG_SR_EWIF                   IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */

/******************  Bit definition for IWDG_WINR register  *******************/
#define IWDG_WINR_WIN_Pos              (0U)
#define IWDG_WINR_WIN_Msk              (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
#define IWDG_WINR_WIN                  IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */

/******************  Bit definition for IWDG_EWCR register  *******************/
#define IWDG_EWCR_EWIT_Pos             (0U)
#define IWDG_EWCR_EWIT_Msk             (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
#define IWDG_EWCR_EWIT                 IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
#define IWDG_EWCR_EWIC_Pos             (14U)
#define IWDG_EWCR_EWIC_Msk             (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00004000 */
#define IWDG_EWCR_EWIC                 IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early interrupt acknowledge */
#define IWDG_EWCR_EWIE_Pos             (15U)
#define IWDG_EWCR_EWIE_Msk             (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00008000 */
#define IWDG_EWCR_EWIE                 IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early interrupt enable */


/******************************************************************************/
/*                                                                            */
/*                        JPEG Encoder/Decoder                                */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for JPEG_CONFR0 register  ***************/
#define JPEG_CONFR0_START_Pos          (0U)
#define JPEG_CONFR0_START_Msk          (0x1UL << JPEG_CONFR0_START_Pos)        /*!< 0x00000001 */
#define JPEG_CONFR0_START              JPEG_CONFR0_START_Msk                   /*!<Start/Stop bit */

/********************  Bit definition for JPEG_CONFR1 register  ***************/
#define JPEG_CONFR1_NF_Pos             (0U)
#define JPEG_CONFR1_NF_Msk             (0x3UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000003 */
#define JPEG_CONFR1_NF                 JPEG_CONFR1_NF_Msk                      /*!<Number of color components */
#define JPEG_CONFR1_NF_0               (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
#define JPEG_CONFR1_NF_1               (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
#define JPEG_CONFR1_DE_Pos             (3U)
#define JPEG_CONFR1_DE_Msk             (0x1UL << JPEG_CONFR1_DE_Pos)           /*!< 0x00000008 */
#define JPEG_CONFR1_DE                 JPEG_CONFR1_DE_Msk                      /*!<Decoding Enable */
#define JPEG_CONFR1_COLORSPACE_Pos     (4U)
#define JPEG_CONFR1_COLORSPACE_Msk     (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000030 */
#define JPEG_CONFR1_COLORSPACE         JPEG_CONFR1_COLORSPACE_Msk              /*!<Color Space */
#define JPEG_CONFR1_COLORSPACE_0       (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
#define JPEG_CONFR1_COLORSPACE_1       (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
#define JPEG_CONFR1_NS_Pos             (6U)
#define JPEG_CONFR1_NS_Msk             (0x3UL << JPEG_CONFR1_NS_Pos)           /*!< 0x000000C0 */
#define JPEG_CONFR1_NS                 JPEG_CONFR1_NS_Msk                      /*!<Number of components for Scan */
#define JPEG_CONFR1_NS_0               (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
#define JPEG_CONFR1_NS_1               (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
#define JPEG_CONFR1_HDR_Pos            (8U)
#define JPEG_CONFR1_HDR_Msk            (0x1UL << JPEG_CONFR1_HDR_Pos)          /*!< 0x00000100 */
#define JPEG_CONFR1_HDR                JPEG_CONFR1_HDR_Msk                     /*!<Header Processing On/Off */
#define JPEG_CONFR1_YSIZE_Pos          (16U)
#define JPEG_CONFR1_YSIZE_Msk          (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)     /*!< 0xFFFF0000 */
#define JPEG_CONFR1_YSIZE              JPEG_CONFR1_YSIZE_Msk                   /*!<Number of lines in source image */

/********************  Bit definition for JPEG_CONFR2 register  ***************/
#define JPEG_CONFR2_NMCU_Pos           (0U)
#define JPEG_CONFR2_NMCU_Msk           (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)   /*!< 0x03FFFFFF */
#define JPEG_CONFR2_NMCU               JPEG_CONFR2_NMCU_Msk                    /*!<Number of MCU units minus 1 to encode */

/********************  Bit definition for JPEG_CONFR3 register  ***************/
#define JPEG_CONFR3_XSIZE_Pos          (16U)
#define JPEG_CONFR3_XSIZE_Msk          (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)     /*!< 0xFFFF0000 */
#define JPEG_CONFR3_XSIZE              JPEG_CONFR3_XSIZE_Msk                   /*!<Number of pixels per line */

/********************  Bit definition for JPEG_CONFR4 register  ***************/
#define JPEG_CONFR4_HD_Pos             (0U)
#define JPEG_CONFR4_HD_Msk             (0x1UL << JPEG_CONFR4_HD_Pos)           /*!< 0x00000001 */
#define JPEG_CONFR4_HD                 JPEG_CONFR4_HD_Msk                      /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR4_HA_Pos             (1U)
#define JPEG_CONFR4_HA_Msk             (0x1UL << JPEG_CONFR4_HA_Pos)           /*!< 0x00000002 */
#define JPEG_CONFR4_HA                 JPEG_CONFR4_HA_Msk                      /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR4_QT_Pos             (2U)
#define JPEG_CONFR4_QT_Msk             (0x3UL << JPEG_CONFR4_QT_Pos)           /*!< 0x0000000C */
#define JPEG_CONFR4_QT                 JPEG_CONFR4_QT_Msk                      /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR4_QT_0               (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
#define JPEG_CONFR4_QT_1               (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
#define JPEG_CONFR4_NB_Pos             (4U)
#define JPEG_CONFR4_NB_Msk             (0xFUL << JPEG_CONFR4_NB_Pos)           /*!< 0x000000F0 */
#define JPEG_CONFR4_NB                 JPEG_CONFR4_NB_Msk                      /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR4_NB_0               (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
#define JPEG_CONFR4_NB_1               (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
#define JPEG_CONFR4_NB_2               (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
#define JPEG_CONFR4_NB_3               (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
#define JPEG_CONFR4_VSF_Pos            (8U)
#define JPEG_CONFR4_VSF_Msk            (0xFUL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000F00 */
#define JPEG_CONFR4_VSF                JPEG_CONFR4_VSF_Msk                     /*!<Vertical sampling factor for component 1 */
#define JPEG_CONFR4_VSF_0              (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
#define JPEG_CONFR4_VSF_1              (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
#define JPEG_CONFR4_VSF_2              (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
#define JPEG_CONFR4_VSF_3              (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
#define JPEG_CONFR4_HSF_Pos            (12U)
#define JPEG_CONFR4_HSF_Msk            (0xFUL << JPEG_CONFR4_HSF_Pos)          /*!< 0x0000F000 */
#define JPEG_CONFR4_HSF                JPEG_CONFR4_HSF_Msk                     /*!<Horizontal sampling factor for component 1 */
#define JPEG_CONFR4_HSF_0              (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
#define JPEG_CONFR4_HSF_1              (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
#define JPEG_CONFR4_HSF_2              (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
#define JPEG_CONFR4_HSF_3              (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

/********************  Bit definition for JPEG_CONFR5 register  ***************/
#define JPEG_CONFR5_HD_Pos             (0U)
#define JPEG_CONFR5_HD_Msk             (0x1UL << JPEG_CONFR5_HD_Pos)           /*!< 0x00000001 */
#define JPEG_CONFR5_HD                 JPEG_CONFR5_HD_Msk                      /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR5_HA_Pos             (1U)
#define JPEG_CONFR5_HA_Msk             (0x1UL << JPEG_CONFR5_HA_Pos)           /*!< 0x00000002 */
#define JPEG_CONFR5_HA                 JPEG_CONFR5_HA_Msk                      /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR5_QT_Pos             (2U)
#define JPEG_CONFR5_QT_Msk             (0x3UL << JPEG_CONFR5_QT_Pos)           /*!< 0x0000000C */
#define JPEG_CONFR5_QT                 JPEG_CONFR5_QT_Msk                      /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR5_QT_0               (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
#define JPEG_CONFR5_QT_1               (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
#define JPEG_CONFR5_NB_Pos             (4U)
#define JPEG_CONFR5_NB_Msk             (0xFUL << JPEG_CONFR5_NB_Pos)           /*!< 0x000000F0 */
#define JPEG_CONFR5_NB                 JPEG_CONFR5_NB_Msk                      /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR5_NB_0               (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
#define JPEG_CONFR5_NB_1               (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
#define JPEG_CONFR5_NB_2               (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
#define JPEG_CONFR5_NB_3               (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
#define JPEG_CONFR5_VSF_Pos            (8U)
#define JPEG_CONFR5_VSF_Msk            (0xFUL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000F00 */
#define JPEG_CONFR5_VSF                JPEG_CONFR5_VSF_Msk                     /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR5_VSF_0              (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
#define JPEG_CONFR5_VSF_1              (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
#define JPEG_CONFR5_VSF_2              (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
#define JPEG_CONFR5_VSF_3              (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
#define JPEG_CONFR5_HSF_Pos            (12U)
#define JPEG_CONFR5_HSF_Msk            (0xFUL << JPEG_CONFR5_HSF_Pos)          /*!< 0x0000F000 */
#define JPEG_CONFR5_HSF                JPEG_CONFR5_HSF_Msk                     /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR5_HSF_0              (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
#define JPEG_CONFR5_HSF_1              (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
#define JPEG_CONFR5_HSF_2              (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
#define JPEG_CONFR5_HSF_3              (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

/********************  Bit definition for JPEG_CONFR6 register  ***************/
#define JPEG_CONFR6_HD_Pos             (0U)
#define JPEG_CONFR6_HD_Msk             (0x1UL << JPEG_CONFR6_HD_Pos)           /*!< 0x00000001 */
#define JPEG_CONFR6_HD                 JPEG_CONFR6_HD_Msk                      /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR6_HA_Pos             (1U)
#define JPEG_CONFR6_HA_Msk             (0x1UL << JPEG_CONFR6_HA_Pos)           /*!< 0x00000002 */
#define JPEG_CONFR6_HA                 JPEG_CONFR6_HA_Msk                      /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR6_QT_Pos             (2U)
#define JPEG_CONFR6_QT_Msk             (0x3UL << JPEG_CONFR6_QT_Pos)           /*!< 0x0000000C */
#define JPEG_CONFR6_QT                 JPEG_CONFR6_QT_Msk                      /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR6_QT_0               (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
#define JPEG_CONFR6_QT_1               (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
#define JPEG_CONFR6_NB_Pos             (4U)
#define JPEG_CONFR6_NB_Msk             (0xFUL << JPEG_CONFR6_NB_Pos)           /*!< 0x000000F0 */
#define JPEG_CONFR6_NB                 JPEG_CONFR6_NB_Msk                      /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR6_NB_0               (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
#define JPEG_CONFR6_NB_1               (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
#define JPEG_CONFR6_NB_2               (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
#define JPEG_CONFR6_NB_3               (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
#define JPEG_CONFR6_VSF_Pos            (8U)
#define JPEG_CONFR6_VSF_Msk            (0xFUL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000F00 */
#define JPEG_CONFR6_VSF                JPEG_CONFR6_VSF_Msk                     /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR6_VSF_0              (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
#define JPEG_CONFR6_VSF_1              (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
#define JPEG_CONFR6_VSF_2              (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
#define JPEG_CONFR6_VSF_3              (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
#define JPEG_CONFR6_HSF_Pos            (12U)
#define JPEG_CONFR6_HSF_Msk            (0xFUL << JPEG_CONFR6_HSF_Pos)          /*!< 0x0000F000 */
#define JPEG_CONFR6_HSF                JPEG_CONFR6_HSF_Msk                     /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR6_HSF_0              (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
#define JPEG_CONFR6_HSF_1              (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
#define JPEG_CONFR6_HSF_2              (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
#define JPEG_CONFR6_HSF_3              (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

/********************  Bit definition for JPEG_CONFR7 register  ***************/
#define JPEG_CONFR7_HD_Pos             (0U)
#define JPEG_CONFR7_HD_Msk             (0x1UL << JPEG_CONFR7_HD_Pos)           /*!< 0x00000001 */
#define JPEG_CONFR7_HD                 JPEG_CONFR7_HD_Msk                      /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR7_HA_Pos             (1U)
#define JPEG_CONFR7_HA_Msk             (0x1UL << JPEG_CONFR7_HA_Pos)           /*!< 0x00000002 */
#define JPEG_CONFR7_HA                 JPEG_CONFR7_HA_Msk                      /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR7_QT_Pos             (2U)
#define JPEG_CONFR7_QT_Msk             (0x3UL << JPEG_CONFR7_QT_Pos)           /*!< 0x0000000C */
#define JPEG_CONFR7_QT                 JPEG_CONFR7_QT_Msk                      /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR7_QT_0               (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
#define JPEG_CONFR7_QT_1               (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
#define JPEG_CONFR7_NB_Pos             (4U)
#define JPEG_CONFR7_NB_Msk             (0xFUL << JPEG_CONFR7_NB_Pos)           /*!< 0x000000F0 */
#define JPEG_CONFR7_NB                 JPEG_CONFR7_NB_Msk                      /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR7_NB_0               (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
#define JPEG_CONFR7_NB_1               (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
#define JPEG_CONFR7_NB_2               (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
#define JPEG_CONFR7_NB_3               (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
#define JPEG_CONFR7_VSF_Pos            (8U)
#define JPEG_CONFR7_VSF_Msk            (0xFUL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000F00 */
#define JPEG_CONFR7_VSF                JPEG_CONFR7_VSF_Msk                     /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR7_VSF_0              (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
#define JPEG_CONFR7_VSF_1              (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
#define JPEG_CONFR7_VSF_2              (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
#define JPEG_CONFR7_VSF_3              (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
#define JPEG_CONFR7_HSF_Pos            (12U)
#define JPEG_CONFR7_HSF_Msk            (0xFUL << JPEG_CONFR7_HSF_Pos)          /*!< 0x0000F000 */
#define JPEG_CONFR7_HSF                JPEG_CONFR7_HSF_Msk                     /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR7_HSF_0              (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
#define JPEG_CONFR7_HSF_1              (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
#define JPEG_CONFR7_HSF_2              (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
#define JPEG_CONFR7_HSF_3              (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

/********************  Bit definition for JPEG_CR register  *******************/
#define JPEG_CR_JCEN_Pos               (0U)
#define JPEG_CR_JCEN_Msk               (0x1UL << JPEG_CR_JCEN_Pos)             /*!< 0x00000001 */
#define JPEG_CR_JCEN                   JPEG_CR_JCEN_Msk                        /*!<Enable the JPEG Codec Core */
#define JPEG_CR_IFTIE_Pos              (1U)
#define JPEG_CR_IFTIE_Msk              (0x1UL << JPEG_CR_IFTIE_Pos)            /*!< 0x00000002 */
#define JPEG_CR_IFTIE                  JPEG_CR_IFTIE_Msk                       /*!<Input FIFO Threshold Interrupt Enable */
#define JPEG_CR_IFNFIE_Pos             (2U)
#define JPEG_CR_IFNFIE_Msk             (0x1UL << JPEG_CR_IFNFIE_Pos)           /*!< 0x00000004 */
#define JPEG_CR_IFNFIE                 JPEG_CR_IFNFIE_Msk                      /*!<Input FIFO Not Full Interrupt Enable */
#define JPEG_CR_OFTIE_Pos              (3U)
#define JPEG_CR_OFTIE_Msk              (0x1UL << JPEG_CR_OFTIE_Pos)            /*!< 0x00000008 */
#define JPEG_CR_OFTIE                  JPEG_CR_OFTIE_Msk                       /*!<Output FIFO Threshold Interrupt Enable */
#define JPEG_CR_OFNEIE_Pos             (4U)
#define JPEG_CR_OFNEIE_Msk             (0x1UL << JPEG_CR_OFNEIE_Pos)           /*!< 0x00000010 */
#define JPEG_CR_OFNEIE                 JPEG_CR_OFNEIE_Msk                      /*!<Output FIFO Not Empty Interrupt Enable */
#define JPEG_CR_EOCIE_Pos              (5U)
#define JPEG_CR_EOCIE_Msk              (0x1UL << JPEG_CR_EOCIE_Pos)            /*!< 0x00000020 */
#define JPEG_CR_EOCIE                  JPEG_CR_EOCIE_Msk                       /*!<End of Conversion Interrupt Enable */
#define JPEG_CR_HPDIE_Pos              (6U)
#define JPEG_CR_HPDIE_Msk              (0x1UL << JPEG_CR_HPDIE_Pos)            /*!< 0x00000040 */
#define JPEG_CR_HPDIE                  JPEG_CR_HPDIE_Msk                       /*!<Header Parsing Done Interrupt Enable */
#define JPEG_CR_IDMAEN_Pos             (11U)
#define JPEG_CR_IDMAEN_Msk             (0x1UL << JPEG_CR_IDMAEN_Pos)           /*!< 0x00000800 */
#define JPEG_CR_IDMAEN                 JPEG_CR_IDMAEN_Msk                      /*!< Input DMA enable */
#define JPEG_CR_ODMAEN_Pos             (12U)
#define JPEG_CR_ODMAEN_Msk             (0x1UL << JPEG_CR_ODMAEN_Pos)           /*!< 0x00001000 */
#define JPEG_CR_ODMAEN                 JPEG_CR_ODMAEN_Msk                      /*!< output DMA enable */
#define JPEG_CR_IFF_Pos                (13U)
#define JPEG_CR_IFF_Msk                (0x1UL << JPEG_CR_IFF_Pos)              /*!< 0x00002000 */
#define JPEG_CR_IFF                    JPEG_CR_IFF_Msk                         /*!<Flush the input FIFO */
#define JPEG_CR_OFF_Pos                (14U)
#define JPEG_CR_OFF_Msk                (0x1UL << JPEG_CR_OFF_Pos)              /*!< 0x00004000 */
#define JPEG_CR_OFF                    JPEG_CR_OFF_Msk                         /*!<Flush the output FIFO */

/********************  Bit definition for JPEG_SR register  *******************/
#define JPEG_SR_IFTF_Pos               (1U)
#define JPEG_SR_IFTF_Msk               (0x1UL << JPEG_SR_IFTF_Pos)             /*!< 0x00000002 */
#define JPEG_SR_IFTF                   JPEG_SR_IFTF_Msk                        /*!<Input FIFO is not full and is below its threshold flag */
#define JPEG_SR_IFNFF_Pos              (2U)
#define JPEG_SR_IFNFF_Msk              (0x1UL << JPEG_SR_IFNFF_Pos)            /*!< 0x00000004 */
#define JPEG_SR_IFNFF                  JPEG_SR_IFNFF_Msk                       /*!<Input FIFO Not Full Flag, a data can be written */
#define JPEG_SR_OFTF_Pos               (3U)
#define JPEG_SR_OFTF_Msk               (0x1UL << JPEG_SR_OFTF_Pos)             /*!< 0x00000008 */
#define JPEG_SR_OFTF                   JPEG_SR_OFTF_Msk                        /*!<Output FIFO is not empty and has reach its threshold */
#define JPEG_SR_OFNEF_Pos              (4U)
#define JPEG_SR_OFNEF_Msk              (0x1UL << JPEG_SR_OFNEF_Pos)            /*!< 0x00000010 */
#define JPEG_SR_OFNEF                  JPEG_SR_OFNEF_Msk                       /*!<Output FIFO is not empty, a data is available */
#define JPEG_SR_EOCF_Pos               (5U)
#define JPEG_SR_EOCF_Msk               (0x1UL << JPEG_SR_EOCF_Pos)             /*!< 0x00000020 */
#define JPEG_SR_EOCF                   JPEG_SR_EOCF_Msk                        /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
#define JPEG_SR_HPDF_Pos               (6U)
#define JPEG_SR_HPDF_Msk               (0x1UL << JPEG_SR_HPDF_Pos)             /*!< 0x00000040 */
#define JPEG_SR_HPDF                   JPEG_SR_HPDF_Msk                        /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
#define JPEG_SR_COF_Pos                (7U)
#define JPEG_SR_COF_Msk                (0x1UL << JPEG_SR_COF_Pos)              /*!< 0x00000080 */
#define JPEG_SR_COF                    JPEG_SR_COF_Msk                         /*!<JPEG Codec operation on going flag */

/********************  Bit definition for JPEG_CFR register  ******************/
#define JPEG_CFR_CEOCF_Pos             (4U)
#define JPEG_CFR_CEOCF_Msk             (0x1UL << JPEG_CFR_CEOCF_Pos)           /*!< 0x00000010 */
#define JPEG_CFR_CEOCF                 JPEG_CFR_CEOCF_Msk                      /*!<Clear End of Conversion Flag */
#define JPEG_CFR_CHPDF_Pos             (5U)
#define JPEG_CFR_CHPDF_Msk             (0x1UL << JPEG_CFR_CHPDF_Pos)           /*!< 0x00000020 */
#define JPEG_CFR_CHPDF                 JPEG_CFR_CHPDF_Msk                      /*!<Clear Header Parsing Done Flag */

/********************  Bit definition for JPEG_DIR register  ******************/
#define JPEG_DIR_DATAIN_Pos            (0U)
#define JPEG_DIR_DATAIN_Msk            (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)   /*!< 0xFFFFFFFF */
#define JPEG_DIR_DATAIN                JPEG_DIR_DATAIN_Msk                     /*!<Data Input FIFO */

/********************  Bit definition for JPEG_DOR register  ******************/
#define JPEG_DOR_DATAOUT_Pos           (0U)
#define JPEG_DOR_DATAOUT_Msk           (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)  /*!< 0xFFFFFFFF */
#define JPEG_DOR_DATAOUT               JPEG_DOR_DATAOUT_Msk                    /*!<Data Output FIFO */


/******************************************************************************/
/*                                                                            */
/*                         Low Power Timer (LPTIM)                            */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for LPTIM_ISR register  *******************/
#define LPTIM_ISR_CC1IF_Pos            (0U)
#define LPTIM_ISR_CC1IF_Msk            (0x1UL << LPTIM_ISR_CC1IF_Pos)          /*!< 0x00000001 */
#define LPTIM_ISR_CC1IF                LPTIM_ISR_CC1IF_Msk                     /*!< Capture/Compare 1 interrupt flag */
#define LPTIM_ISR_ARRM_Pos             (1U)
#define LPTIM_ISR_ARRM_Msk             (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
#define LPTIM_ISR_ARRM                 LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos          (2U)
#define LPTIM_ISR_EXTTRIG_Msk          (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG              LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
#define LPTIM_ISR_CMP1OK_Pos           (3U)
#define LPTIM_ISR_CMP1OK_Msk           (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
#define LPTIM_ISR_CMP1OK               LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
#define LPTIM_ISR_ARROK_Pos            (4U)
#define LPTIM_ISR_ARROK_Msk            (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
#define LPTIM_ISR_ARROK                LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos               (5U)
#define LPTIM_ISR_UP_Msk               (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
#define LPTIM_ISR_UP                   LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos             (6U)
#define LPTIM_ISR_DOWN_Msk             (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
#define LPTIM_ISR_DOWN                 LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
#define LPTIM_ISR_UE_Pos               (7U)
#define LPTIM_ISR_UE_Msk               (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
#define LPTIM_ISR_UE                   LPTIM_ISR_UE_Msk                        /*!< Update event */
#define LPTIM_ISR_REPOK_Pos            (8U)
#define LPTIM_ISR_REPOK_Msk            (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
#define LPTIM_ISR_REPOK                LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
#define LPTIM_ISR_CC2IF_Pos            (9U)
#define LPTIM_ISR_CC2IF_Msk            (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
#define LPTIM_ISR_CC2IF                LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
#define LPTIM_ISR_CC1OF_Pos            (12U)
#define LPTIM_ISR_CC1OF_Msk            (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
#define LPTIM_ISR_CC1OF                LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
#define LPTIM_ISR_CC2OF_Pos            (13U)
#define LPTIM_ISR_CC2OF_Msk            (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
#define LPTIM_ISR_CC2OF                LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
#define LPTIM_ISR_CMP2OK_Pos           (19U)
#define LPTIM_ISR_CMP2OK_Msk           (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
#define LPTIM_ISR_CMP2OK               LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
#define LPTIM_ISR_DIEROK_Pos           (24U)
#define LPTIM_ISR_DIEROK_Msk           (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
#define LPTIM_ISR_DIEROK               LPTIM_ISR_DIEROK_Msk                    /*!< Interrupt enable register update OK */

/******************  Bit definition for LPTIM_ICR register  *******************/
#define LPTIM_ICR_CC1CF_Pos            (0U)
#define LPTIM_ICR_CC1CF_Msk            (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
#define LPTIM_ICR_CC1CF                LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
#define LPTIM_ICR_ARRMCF_Pos           (1U)
#define LPTIM_ICR_ARRMCF_Msk           (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF               LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
#define LPTIM_ICR_EXTTRIGCF_Pos        (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk        (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF            LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
#define LPTIM_ICR_CMP1OKCF_Pos         (3U)
#define LPTIM_ICR_CMP1OKCF_Msk         (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
#define LPTIM_ICR_CMP1OKCF             LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
#define LPTIM_ICR_ARROKCF_Pos          (4U)
#define LPTIM_ICR_ARROKCF_Msk          (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF              LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
#define LPTIM_ICR_UPCF_Pos             (5U)
#define LPTIM_ICR_UPCF_Msk             (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
#define LPTIM_ICR_UPCF                 LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
#define LPTIM_ICR_DOWNCF_Pos           (6U)
#define LPTIM_ICR_DOWNCF_Msk           (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF               LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
#define LPTIM_ICR_UECF_Pos             (7U)
#define LPTIM_ICR_UECF_Msk             (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
#define LPTIM_ICR_UECF                 LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
#define LPTIM_ICR_REPOKCF_Pos          (8U)
#define LPTIM_ICR_REPOKCF_Msk          (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
#define LPTIM_ICR_REPOKCF              LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
#define LPTIM_ICR_CC2CF_Pos            (9U)
#define LPTIM_ICR_CC2CF_Msk            (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
#define LPTIM_ICR_CC2CF                LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
#define LPTIM_ICR_CC1OCF_Pos           (12U)
#define LPTIM_ICR_CC1OCF_Msk           (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
#define LPTIM_ICR_CC1OCF               LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
#define LPTIM_ICR_CC2OCF_Pos           (13U)
#define LPTIM_ICR_CC2OCF_Msk           (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
#define LPTIM_ICR_CC2OCF               LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
#define LPTIM_ICR_CMP2OKCF_Pos         (19U)
#define LPTIM_ICR_CMP2OKCF_Msk         (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
#define LPTIM_ICR_CMP2OKCF             LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
#define LPTIM_ICR_DIEROKCF_Pos         (24U)
#define LPTIM_ICR_DIEROKCF_Msk         (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
#define LPTIM_ICR_DIEROKCF             LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */

/******************  Bit definition for LPTIM_DIER register *******************/
#define LPTIM_DIER_CC1IE_Pos           (0U)
#define LPTIM_DIER_CC1IE_Msk           (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
#define LPTIM_DIER_CC1IE               LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare 1 interrupt enable */
#define LPTIM_DIER_ARRMIE_Pos          (1U)
#define LPTIM_DIER_ARRMIE_Msk          (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
#define LPTIM_DIER_ARRMIE              LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
#define LPTIM_DIER_EXTTRIGIE_Pos       (2U)
#define LPTIM_DIER_EXTTRIGIE_Msk       (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
#define LPTIM_DIER_EXTTRIGIE           LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
#define LPTIM_DIER_CMP1OKIE_Pos        (3U)
#define LPTIM_DIER_CMP1OKIE_Msk        (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
#define LPTIM_DIER_CMP1OKIE            LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
#define LPTIM_DIER_ARROKIE_Pos         (4U)
#define LPTIM_DIER_ARROKIE_Msk         (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
#define LPTIM_DIER_ARROKIE             LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
#define LPTIM_DIER_UPIE_Pos            (5U)
#define LPTIM_DIER_UPIE_Msk            (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
#define LPTIM_DIER_UPIE                LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
#define LPTIM_DIER_DOWNIE_Pos          (6U)
#define LPTIM_DIER_DOWNIE_Msk          (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
#define LPTIM_DIER_DOWNIE              LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
#define LPTIM_DIER_UEIE_Pos            (7U)
#define LPTIM_DIER_UEIE_Msk            (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
#define LPTIM_DIER_UEIE                LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
#define LPTIM_DIER_REPOKIE_Pos         (8U)
#define LPTIM_DIER_REPOKIE_Msk         (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
#define LPTIM_DIER_REPOKIE             LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
#define LPTIM_DIER_CC2IE_Pos           (9U)
#define LPTIM_DIER_CC2IE_Msk           (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
#define LPTIM_DIER_CC2IE               LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
#define LPTIM_DIER_CC1OIE_Pos          (12U)
#define LPTIM_DIER_CC1OIE_Msk          (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
#define LPTIM_DIER_CC1OIE              LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
#define LPTIM_DIER_CC2OIE_Pos          (13U)
#define LPTIM_DIER_CC2OIE_Msk          (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
#define LPTIM_DIER_CC2OIE              LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
#define LPTIM_DIER_CC1DE_Pos           (16U)
#define LPTIM_DIER_CC1DE_Msk           (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
#define LPTIM_DIER_CC1DE               LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
#define LPTIM_DIER_CMP2OKIE_Pos        (19U)
#define LPTIM_DIER_CMP2OKIE_Msk        (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
#define LPTIM_DIER_CMP2OKIE            LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
#define LPTIM_DIER_UEDE_Pos            (23U)
#define LPTIM_DIER_UEDE_Msk            (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
#define LPTIM_DIER_UEDE                LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
#define LPTIM_DIER_CC2DE_Pos           (25U)
#define LPTIM_DIER_CC2DE_Msk           (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
#define LPTIM_DIER_CC2DE               LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */

/******************  Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos           (0U)
#define LPTIM_CFGR_CKSEL_Msk           (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL               LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos           (1U)
#define LPTIM_CFGR_CKPOL_Msk           (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL               LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0             (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1             (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos           (3U)
#define LPTIM_CFGR_CKFLT_Msk           (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT               LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0             (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1             (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos          (6U)
#define LPTIM_CFGR_TRGFLT_Msk          (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT              LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0            (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1            (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos           (9U)
#define LPTIM_CFGR_PRESC_Msk           (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC               LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0             (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1             (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2             (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos         (13U)
#define LPTIM_CFGR_TRIGSEL_Msk         (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL             LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0           (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1           (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2           (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos          (17U)
#define LPTIM_CFGR_TRIGEN_Msk          (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN              LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0            (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1            (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos          (19U)
#define LPTIM_CFGR_TIMOUT_Msk          (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT              LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos            (20U)
#define LPTIM_CFGR_WAVE_Msk            (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE                LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos          (21U)
#define LPTIM_CFGR_WAVPOL_Msk          (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL              LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
#define LPTIM_CFGR_PRELOAD_Pos         (22U)
#define LPTIM_CFGR_PRELOAD_Msk         (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD             LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos       (23U)
#define LPTIM_CFGR_COUNTMODE_Msk       (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE           LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos             (24U)
#define LPTIM_CFGR_ENC_Msk             (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
#define LPTIM_CFGR_ENC                 LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */

/******************  Bit definition for LPTIM_CR register  ********************/
#define LPTIM_CR_ENABLE_Pos            (0U)
#define LPTIM_CR_ENABLE_Msk            (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
#define LPTIM_CR_ENABLE                LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos           (1U)
#define LPTIM_CR_SNGSTRT_Msk           (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT               LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos           (2U)
#define LPTIM_CR_CNTSTRT_Msk           (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT               LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos          (3U)
#define LPTIM_CR_COUNTRST_Msk          (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST              LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
#define LPTIM_CR_RSTARE_Pos            (4U)
#define LPTIM_CR_RSTARE_Msk            (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
#define LPTIM_CR_RSTARE                LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/

/******************  Bit definition for LPTIM_CCR1 register  ******************/
#define LPTIM_CCR1_CCR1_Pos            (0U)
#define LPTIM_CCR1_CCR1_Msk            (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
#define LPTIM_CCR1_CCR1                LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */

/******************  Bit definition for LPTIM_ARR register  *******************/
#define LPTIM_ARR_ARR_Pos              (0U)
#define LPTIM_ARR_ARR_Msk              (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR                  LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */

/******************  Bit definition for LPTIM_CNT register  *******************/
#define LPTIM_CNT_CNT_Pos              (0U)
#define LPTIM_CNT_CNT_Msk              (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT                  LPTIM_CNT_CNT_Msk                       /*!< Counter register */

/******************  Bit definition for LPTIM_CFGR2 register  *****************/
#define LPTIM_CFGR2_IN1SEL_Pos         (0U)
#define LPTIM_CFGR2_IN1SEL_Msk         (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
#define LPTIM_CFGR2_IN1SEL             LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
#define LPTIM_CFGR2_IN1SEL_0           (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
#define LPTIM_CFGR2_IN1SEL_1           (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
#define LPTIM_CFGR2_IN2SEL_Pos         (4U)
#define LPTIM_CFGR2_IN2SEL_Msk         (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
#define LPTIM_CFGR2_IN2SEL             LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
#define LPTIM_CFGR2_IN2SEL_0           (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
#define LPTIM_CFGR2_IN2SEL_1           (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
#define LPTIM_CFGR2_IC1SEL_Pos         (16U)
#define LPTIM_CFGR2_IC1SEL_Msk         (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
#define LPTIM_CFGR2_IC1SEL             LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
#define LPTIM_CFGR2_IC1SEL_0           (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
#define LPTIM_CFGR2_IC1SEL_1           (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
#define LPTIM_CFGR2_IC2SEL_Pos         (20U)
#define LPTIM_CFGR2_IC2SEL_Msk         (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
#define LPTIM_CFGR2_IC2SEL             LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
#define LPTIM_CFGR2_IC2SEL_0           (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
#define LPTIM_CFGR2_IC2SEL_1           (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */

/******************  Bit definition for LPTIM_RCR register  *******************/
#define LPTIM_RCR_REP_Pos              (0U)
#define LPTIM_RCR_REP_Msk              (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
#define LPTIM_RCR_REP                  LPTIM_RCR_REP_Msk                       /*!< Repetition register value */

/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
#define LPTIM_CCMR1_CC1SEL_Pos         (0U)
#define LPTIM_CCMR1_CC1SEL_Msk         (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
#define LPTIM_CCMR1_CC1SEL             LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
#define LPTIM_CCMR1_CC1E_Pos           (1U)
#define LPTIM_CCMR1_CC1E_Msk           (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
#define LPTIM_CCMR1_CC1E               LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
#define LPTIM_CCMR1_CC1P_Pos           (2U)
#define LPTIM_CCMR1_CC1P_Msk           (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
#define LPTIM_CCMR1_CC1P               LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
#define LPTIM_CCMR1_CC1P_0             (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
#define LPTIM_CCMR1_CC1P_1             (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
#define LPTIM_CCMR1_IC1PSC_Pos         (8U)
#define LPTIM_CCMR1_IC1PSC_Msk         (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
#define LPTIM_CCMR1_IC1PSC             LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
#define LPTIM_CCMR1_IC1PSC_0           (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
#define LPTIM_CCMR1_IC1PSC_1           (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
#define LPTIM_CCMR1_IC1F_Pos           (12U)
#define LPTIM_CCMR1_IC1F_Msk           (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
#define LPTIM_CCMR1_IC1F               LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
#define LPTIM_CCMR1_IC1F_0             (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
#define LPTIM_CCMR1_IC1F_1             (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
#define LPTIM_CCMR1_CC2SEL_Pos         (16U)
#define LPTIM_CCMR1_CC2SEL_Msk         (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
#define LPTIM_CCMR1_CC2SEL             LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
#define LPTIM_CCMR1_CC2E_Pos           (17U)
#define LPTIM_CCMR1_CC2E_Msk           (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
#define LPTIM_CCMR1_CC2E               LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
#define LPTIM_CCMR1_CC2P_Pos           (18U)
#define LPTIM_CCMR1_CC2P_Msk           (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
#define LPTIM_CCMR1_CC2P               LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
#define LPTIM_CCMR1_CC2P_0             (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
#define LPTIM_CCMR1_CC2P_1             (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
#define LPTIM_CCMR1_IC2PSC_Pos         (24U)
#define LPTIM_CCMR1_IC2PSC_Msk         (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
#define LPTIM_CCMR1_IC2PSC             LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
#define LPTIM_CCMR1_IC2PSC_0           (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
#define LPTIM_CCMR1_IC2PSC_1           (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
#define LPTIM_CCMR1_IC2F_Pos           (28U)
#define LPTIM_CCMR1_IC2F_Msk           (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
#define LPTIM_CCMR1_IC2F               LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
#define LPTIM_CCMR1_IC2F_0             (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
#define LPTIM_CCMR1_IC2F_1             (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */

/******************  Bit definition for LPTIM_CCR2 register  ******************/
#define LPTIM_CCR2_CCR2_Pos            (0U)
#define LPTIM_CCR2_CCR2_Msk            (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
#define LPTIM_CCR2_CCR2                LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */


/******************************************************************************/
/*                                                                            */
/*                       Memory Cipher Engine (MCE)                           */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for MCE_CR register  ********************/
#define MCE_CR_GLOCK_Pos               (0U)
#define MCE_CR_GLOCK_Msk               (0x1UL << MCE_CR_GLOCK_Pos)             /*!< 0x00000001 */
#define MCE_CR_GLOCK                   MCE_CR_GLOCK_Msk                        /*!< MCE global lock */
#define MCE_CR_MKLOCK_Pos              (1U)
#define MCE_CR_MKLOCK_Msk              (0x1UL << MCE_CR_MKLOCK_Pos)            /*!< 0x00000002 */
#define MCE_CR_MKLOCK                  MCE_CR_MKLOCK_Msk                       /*!< MCE master and fast master keys lock */

/********************  Bit definition for MCE_SR register  ********************/
#define MCE_SR_MKVALID_Pos             (0U)
#define MCE_SR_MKVALID_Msk             (0x1UL << MCE_SR_MKVALID_Pos)           /*!< 0x00000001 */
#define MCE_SR_MKVALID                 MCE_SR_MKVALID_Msk                      /*!< MCE master key valid flag */
#define MCE_SR_FMKVALID_Pos            (2U)
#define MCE_SR_FMKVALID_Msk            (0x1UL << MCE_SR_FMKVALID_Pos)          /*!< 0x00000004 */
#define MCE_SR_FMKVALID                 MCE_SR_FMKVALID_Msk                    /*!< MCE fast master key valid flag */
#define MCE_SR_ENCDIS_Pos              (4U)
#define MCE_SR_ENCDIS_Msk              (0x1UL << MCE_SR_ENCDIS_Pos)            /*!< 0x00000010 */
#define MCE_SR_ENCDIS                  MCE_SR_ENCDIS_Msk                       /*!< MCE encryption disabled flag */

/********************  Bit definition for MCE_IASR register  ******************/
#define MCE_IASR_CAEF_Pos              (0U)
#define MCE_IASR_CAEF_Msk              (0x1UL << MCE_IASR_CAEF_Pos)             /*!< 0x00000001 */
#define MCE_IASR_CAEF                  MCE_IASR_CAEF_Msk                        /*!< MCE configuration access error flag */
#define MCE_IASR_IAEF_Pos              (1U)
#define MCE_IASR_IAEF_Msk              (0x1UL << MCE_IASR_IAEF_Pos)             /*!< 0x00000002 */
#define MCE_IASR_IAEF                  MCE_IASR_IAEF_Msk                        /*!< MCE illegal access error flag */

/********************  Bit definition for MCE_IACR register  ******************/
#define MCE_IACR_CAEF_Pos              (0U)
#define MCE_IACR_CAEF_Msk              (0x1UL << MCE_IACR_CAEF_Pos)             /*!< 0x00000001 */
#define MCE_IACR_CAEF                  MCE_IACR_CAEF_Msk                        /*!< MCE configuration access error clear bit */
#define MCE_IACR_IAEF_Pos              (1U)
#define MCE_IACR_IAEF_Msk              (0x1UL << MCE_IACR_IAEF_Pos)             /*!< 0x00000002 */
#define MCE_IACR_IAEF                  MCE_IACR_IAEF_Msk                        /*!< MCE illegal access error clear bit */

/********************  Bit definition for MCE_IAIER register  *****************/
#define MCE_IAIER_CAEIE_Pos            (0U)
#define MCE_IAIER_CAEIE_Msk            (0x1UL << MCE_IAIER_CAEIE_Pos)           /*!< 0x00000001 */
#define MCE_IAIER_CAEIE                MCE_IAIER_CAEIE_Msk                      /*!< MCE configuration access error interrupt enable */
#define MCE_IAIER_IAEIE_Pos            (1U)
#define MCE_IAIER_IAEIE_Msk            (0x1UL << MCE_IAIER_IAEIE_Pos)           /*!< 0x00000002 */
#define MCE_IAIER_IAEIE                MCE_IAIER_IAEIE_Msk                      /*!< MCE illegal access error interrupt enable */

/********************  Bit definition for MCE_PRIVCFGR register  **************/
#define MCE_PRIVCFGR_PRIV_Pos          (0U)
#define MCE_PRIVCFGR_PRIV_Msk          (0x1UL << MCE_PRIVCFGR_PRIV_Pos)         /*!< 0x00000001 */
#define MCE_PRIVCFGR_PRIV              MCE_PRIVCFGR_PRIV_Msk                    /*!< MCE privileged configuration */

/********************  Bit definition for MCE_IAESR register  *****************/
#define MCE_IAESR_IAPRIV_Pos           (4U)
#define MCE_IAESR_IAPRIV_Msk           (0x1UL << MCE_IAESR_IAPRIV_Pos)          /*!< 0x00000010 */
#define MCE_IAESR_IAPRIV               MCE_IAESR_IAPRIV_Msk                     /*!< MCE illegal access privilege */
#define MCE_IAESR_IANRW_Pos            (7U)
#define MCE_IAESR_IANRW_Msk            (0x1UL << MCE_IAESR_IANRW_Pos)           /*!< 0x00000080 */
#define MCE_IAESR_IANRW                MCE_IAESR_IANRW_Msk                      /*!< MCE illegal access read/write */

/********************  Bit definition for MCE_IADDR register  *****************/
#define MCE_IADDR_IADD_Pos             (0U)
#define MCE_IADDR_IADD_Msk             (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos)     /*!< 0xFFFFFFFF */
#define MCE_IADDR_IADD                 MCE_IADDR_IADD_Msk                       /*!< MCE illegal address */

/********************  Bit definition for MCE_REGCR register  *****************/
#define MCE_REGCR_BREN_Pos             (0U)
#define MCE_REGCR_BREN_Msk             (0x1UL << MCE_REGCR_BREN_Pos)            /*!< 0x00000001 */
#define MCE_REGCR_BREN                 MCE_REGCR_BREN_Msk                       /*!< MCE base region enable */
#define MCE_REGCR_CTXID_Pos            (9U)
#define MCE_REGCR_CTXID_Msk            (0x3UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000600 */
#define MCE_REGCR_CTXID                MCE_REGCR_CTXID_Msk                      /*!< MCE context ID */
#define MCE_REGCR_CTXID_0              (0x1UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000200 */
#define MCE_REGCR_CTXID_1              (0x2UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000400 */
#define MCE_REGCR_ENC_Pos              (14U)
#define MCE_REGCR_ENC_Msk              (0x3UL << MCE_REGCR_ENC_Pos)             /*!< 0x0000C000 */
#define MCE_REGCR_ENC                  MCE_REGCR_ENC_Msk                        /*!< MCE encrypted region */
#define MCE_REGCR_ENC_0                (0x1UL << MCE_REGCR_ENC_Pos)             /*!< 0x00004000 */
#define MCE_REGCR_ENC_1                (0x2UL << MCE_REGCR_ENC_Pos)             /*!< 0x00008000 */
#define MCE_REGCR_PRIV_Pos             (16U)
#define MCE_REGCR_PRIV_Msk             (0x1UL << MCE_REGCR_PRIV_Pos)            /*!< 0x00010000 */
#define MCE_REGCR_PRIV                 MCE_REGCR_PRIV_Msk                       /*!< MCE privileged region */

/********************  Bit definition for MCE_SADDR register  *****************/
#define MCE_SADDR_BADDSTART_Pos        (12U)
#define MCE_SADDR_BADDSTART_Msk        (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos)   /*!< 0xFFFFF000 */
#define MCE_SADDR_BADDSTART            MCE_SADDR_BADDSTART_Msk                  /*!< MCE region address start */

/********************  Bit definition for MCE_EADDR register  *****************/
#define MCE_EADDR_BADDEND_Pos          (12U)
#define MCE_EADDR_BADDEND_Msk          (0xFFFFFUL << MCE_EADDR_BADDEND_Pos)     /*!< 0xFFFFF000 */
#define MCE_EADDR_BADDEND              MCE_EADDR_BADDEND_Msk                    /*!< MCE region address end */

/********************  Bit definition for MCE_ATTR register  ******************/
#define MCE_ATTR_WREN_Pos              (16U)
#define MCE_ATTR_WREN_Msk              (0x1UL << MCE_ATTR_WREN_Pos)             /*!< 0x00010000 */
#define MCE_ATTR_WREN                  MCE_ATTR_WREN_Msk                        /*!< MCE region write enable */

/********************  Bit definition for MCE_MKEYR0 register  ****************/
#define MCE_MKEYR0_MKEY_Pos            (0U)
#define MCE_MKEYR0_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_MKEYR0_MKEY                MCE_MKEYR0_MKEY_Msk                      /*!< MCE master key, bits [31:0] */

/********************  Bit definition for MCE_MKEYR1 register  ****************/
#define MCE_MKEYR1_MKEY_Pos            (0U)
#define MCE_MKEYR1_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_MKEYR1_MKEY                MCE_MKEYR1_MKEY_Msk                      /*!< MCE master key, bits [63:32] */

/********************  Bit definition for MCE_MKEYR2 register  ****************/
#define MCE_MKEYR2_MKEY_Pos            (0U)
#define MCE_MKEYR2_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_MKEYR2_MKEY                MCE_MKEYR2_MKEY_Msk                      /*!< MCE master key, bits [95:64] */

/********************  Bit definition for MCE_MKEYR3 register  ****************/
#define MCE_MKEYR3_MKEY_Pos            (0U)
#define MCE_MKEYR3_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_MKEYR3_MKEY                MCE_MKEYR3_MKEY_Msk                      /*!< MCE master key, bits [127:96] */

/********************  Bit definition for MCE_FMKEYR0 register  ***************/
#define MCE_FMKEYR0_FMKEY_Pos          (0U)
#define MCE_FMKEYR0_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos)  /*!< 0xFFFFFFFF */
#define MCE_FMKEYR0_FMKEY              MCE_FMKEYR0_FMKEY_Msk                    /*!< MCE fast master key, bits [31:0] */

/********************  Bit definition for MCE_FMKEYR1 register  ***************/
#define MCE_FMKEYR1_FMKEY_Pos          (0U)
#define MCE_FMKEYR1_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos)  /*!< 0xFFFFFFFF */
#define MCE_FMKEYR1_FMKEY              MCE_FMKEYR1_FMKEY_Msk                    /*!< MCE fast master key, bits [63:32] */

/********************  Bit definition for MCE_FMKEYR2 register  ***************/
#define MCE_FMKEYR2_FMKEY_Pos          (0U)
#define MCE_FMKEYR2_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos)  /*!< 0xFFFFFFFF */
#define MCE_FMKEYR2_FMKEY              MCE_FMKEYR2_FMKEY_Msk                    /*!< MCE fast master key, bits [95:64] */

/********************  Bit definition for MCE_FMKEYR3 register  ***************/
#define MCE_FMKEYR3_FMKEY_Pos          (0U)
#define MCE_FMKEYR3_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos)  /*!< 0xFFFFFFFF */
#define MCE_FMKEYR3_FMKEY              MCE_FMKEYR3_FMKEY_Msk                    /*!< MCE fast master key, bits [127:96] */

/********************  Bit definition for MCE_CCCFGR register  ****************/
#define MCE_CCCFGR_CCEN_Pos             (0U)
#define MCE_CCCFGR_CCEN_Msk             (0x1UL << MCE_CCCFGR_CCEN_Pos)          /*!< 0x00000001 */
#define MCE_CCCFGR_CCEN                 MCE_CCCFGR_CCEN_Msk                     /*!< MCE cipher context enable */
#define MCE_CCCFGR_CCLOCK_Pos           (1U)
#define MCE_CCCFGR_CCLOCK_Msk           (0x1UL << MCE_CCCFGR_CCLOCK_Pos)        /*!< 0x00000002 */
#define MCE_CCCFGR_CCLOCK               MCE_CCCFGR_CCLOCK_Msk                   /*!< MCE cipher context lock */
#define MCE_CCCFGR_KEYLOCK_Pos          (2U)
#define MCE_CCCFGR_KEYLOCK_Msk          (0x1UL << MCE_CCCFGR_KEYLOCK_Pos)       /*!< 0x00000004 */
#define MCE_CCCFGR_KEYLOCK              MCE_CCCFGR_KEYLOCK_Msk                  /*!< MCE cipher context key lock */
#define MCE_CCCFGR_KEYCRC_Pos           (8U)
#define MCE_CCCFGR_KEYCRC_Msk           (0xFFUL << MCE_CCCFGR_KEYCRC_Pos)       /*!< 0x0000FF00 */
#define MCE_CCCFGR_KEYCRC               MCE_CCCFGR_KEYCRC_Msk                   /*!< MCE cipher context key CRC */
#define MCE_CCCFGR_VERSION_Pos          (16U)
#define MCE_CCCFGR_VERSION_Msk          (0xFFFFUL << MCE_CCCFGR_VERSION_Pos)    /*!< 0xFFFF0000 */
#define MCE_CCCFGR_VERSION              MCE_CCCFGR_VERSION_Msk                  /*!< MCE cipher context version */

/********************  Bit definition for MCE_CCNR0 register  *****************/
#define MCE_CCNR0_SCNONCE_Pos          (0U)
#define MCE_CCNR0_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
#define MCE_CCNR0_SCNONCE              MCE_CCNR0_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [31:0] */

/********************  Bit definition for MCE_CCNR1 register  ****************/
#define MCE_CCNR1_SCNONCE_Pos          (0U)
#define MCE_CCNR1_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
#define MCE_CCNR1_SCNONCE              MCE_CCNR1_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [63:32] */

/********************  Bit definition for MCE_CCKEYR0 register  ***************/
#define MCE_CCKEYR0_KEY_Pos            (0U)
#define MCE_CCKEYR0_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_CCKEYR0_KEY                MCE_CCKEYR0_KEY_Msk                      /*!< MCE cipher context key, bits [31:0] */

/********************  Bit definition for MCE_CCKEYR1 register  ***************/
#define MCE_CCKEYR1_KEY_Pos            (0U)
#define MCE_CCKEYR1_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_CCKEYR1_KEY                MCE_CCKEYR1_KEY_Msk                      /*!< MCE fast master key, bits [63:32] */

/********************  Bit definition for MCE_CCKEYR2 register  ***************/
#define MCE_CCKEYR2_KEY_Pos            (0U)
#define MCE_CCKEYR2_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_CCKEYR2_KEY                MCE_CCKEYR2_KEY_Msk                      /*!< MCE fast master key, bits [95:64] */

/********************  Bit definition for MCE_CCKEYR3 register  ***************/
#define MCE_CCKEYR3_KEY_Pos            (0U)
#define MCE_CCKEYR3_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos)    /*!< 0xFFFFFFFF */
#define MCE_CCKEYR3_KEY                MCE_CCKEYR3_KEY_Msk                      /*!< MCE fast master key, bits [127:96] */


/******************************************************************************/
/*                                                                            */
/*                                MDIOS                                       */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for MDIOS_CR register  ******************/
#define MDIOS_CR_EN_Pos                (0U)
#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
#define MDIOS_CR_WRIE_Pos              (1U)
#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
#define MDIOS_CR_RDIE_Pos              (2U)
#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
#define MDIOS_CR_EIE_Pos               (3U)
#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
#define MDIOS_CR_DPC_Pos               (7U)
#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

/********************  Bit definition for MDIOS_SR register  *******************/
#define MDIOS_SR_PERF_Pos              (0U)
#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
#define MDIOS_SR_SERF_Pos              (1U)
#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
#define MDIOS_SR_TERF_Pos              (2U)
#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

/********************  Bit definition for MDIOS_CLRFR register  ****************/
#define MDIOS_CLRFR_CPERF_Pos          (0U)
#define MDIOS_CLRFR_CPERF_Msk          (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
#define MDIOS_CLRFR_CPERF              MDIOS_CLRFR_CPERF_Msk                   /*!<  MDIOS slave Clear the turnaround error flag */
#define MDIOS_CLRFR_CSERF_Pos          (1U)
#define MDIOS_CLRFR_CSERF_Msk          (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
#define MDIOS_CLRFR_CSERF              MDIOS_CLRFR_CSERF_Msk                   /*!<  MDIOS slave Clear the start error flag */
#define MDIOS_CLRFR_CTERF_Pos          (2U)
#define MDIOS_CLRFR_CTERF_Msk          (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
#define MDIOS_CLRFR_CTERF              MDIOS_CLRFR_CTERF_Msk                   /*!<  MDIOS slave Clear the preamble error flag */

/******************************************************************************/
/*                                                                            */
/*                                 MDF/ADF                                    */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for MDF/ADF_GCR register  ****************/
#define MDF_GCR_TRGO_Pos                    (0U)
#define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
#define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!< Trigger output control */

/*******************  Bit definition for MDF/ADF_CKGCR register  **************/
#define MDF_CKGCR_CKGDEN_Pos                (0U)
#define MDF_CKGCR_CKGDEN_Msk                (0x1UL << MDF_CKGCR_CKGDEN_Pos)         /*!< 0x00000001 */
#define MDF_CKGCR_CKGDEN                    MDF_CKGCR_CKGDEN_Msk                    /*!< CKGDEN dividers enable */
#define MDF_CKGCR_CCK0EN_Pos                (1U)
#define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
#define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!< CCK0 clock enable */
#define MDF_CKGCR_CCK1EN_Pos                (2U)
#define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
#define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!< CCK1 clock enable */
#define MDF_CKGCR_CKGMOD_Pos                (4U)
#define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
#define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!< Clock genartor mode */
#define MDF_CKGCR_CCK0DIR_Pos               (5U)
#define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
#define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!< CCK0 clock direction */
#define MDF_CKGCR_CCK1DIR_Pos               (6U)
#define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
#define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!< CCK1 clock direction */
#define MDF_CKGCR_TRGSENS_Pos               (8U)
#define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
#define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!< CKGEN trigger sensitivity selection */
#define MDF_CKGCR_TRGSRC_Pos                (12U)
#define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
#define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!< Digital Filter trigger signal selection */
#define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
#define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
#define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
#define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
#define MDF_CKGCR_CCKDIV_Pos                (16U)
#define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
#define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!< Divider to control the MDF_CCK clock */
#define MDF_CKGCR_PROCDIV_Pos               (24U)
#define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
#define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!< Divider to control the serial interface clock */
#define MDF_CKGCR_CKGACTIVE_Pos             (31U)
#define MDF_CKGCR_CKGACTIVE_Msk             (0x1UL << MDF_CKGCR_CKGACTIVE_Pos)      /*!< 0x80000000 */
#define MDF_CKGCR_CKGACTIVE                 MDF_CKGCR_CKGACTIVE_Msk                 /*!< Clock generator active flag */

/*******************  Bit definition for MDF/ADF_SITFxCR register  ************/
#define MDF_SITFCR_SITFEN_Pos               (0U)
#define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
#define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!< Serial interface enable */
#define MDF_SITFCR_SCKSRC_Pos               (1U)
#define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
#define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!< Serial clock source */
#define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
#define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
#define MDF_SITFCR_SITFMOD_Pos              (4U)
#define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
#define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!< Serial interface type */
#define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
#define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
#define MDF_SITFCR_STH_Pos                  (8U)
#define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
#define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!< Manchester Symbol threshold / SPI threshold */
#define MDF_SITFCR_SITFACTIVE_Pos           (31U)
#define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
#define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!< Serial interface active flag */

/*******************  Bit definition for MDF/ADF_BSMXxCR register  ************/
#define MDF_BSMXCR_BSSEL_Pos                (0U)
#define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
#define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!< Bit Streal selection */
#define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
#define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
#define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
#define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
#define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
#define MDF_BSMXCR_BSMXACTIVE_Pos           (31U)
#define MDF_BSMXCR_BSMXACTIVE_Msk           (0x1UL << MDF_BSMXCR_BSMXACTIVE_Pos)    /*!< 0x80000000 */
#define MDF_BSMXCR_BSMXACTIVE               MDF_BSMXCR_BSMXACTIVE_Msk               /*!< Bit Streal activation flag */

/*******************  Bit definition for MDF/ADF_DFLTxCR register  ************/
#define MDF_DFLTCR_DFLTEN_Pos               (0U)
#define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
#define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!< Digital filter enable */
#define MDF_DFLTCR_DMAEN_Pos                (1U)
#define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
#define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!< DMA request enable */
#define MDF_DFLTCR_FTH_Pos                  (2U)
#define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
#define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!< RXFIFO Threshold selection */
#define MDF_DFLTCR_ACQMOD_Pos               (4U)
#define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
#define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!< Digital filter trigger mode */
#define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
#define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
#define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
#define MDF_DFLTCR_TRGSENS_Pos              (8U)
#define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
#define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!< Digital filter trigger sensitivity selection */
#define MDF_DFLTCR_TRGSRC_Pos               (12U)
#define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
#define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!< Digital filter trigger signal selection */
#define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
#define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
#define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
#define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
#define MDF_DFLTCR_NBDIS_Pos                (20U)
#define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
#define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!< Number of samples to be discard */
#define MDF_DFLTCR_DFLTRUN_Pos              (30U)
#define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
#define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!< Digital filter run status flag */
#define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
#define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
#define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!< Digital filter active flag */

/*******************  Bit definition for MDF/ADF_DFLTxCICR register  **********/
#define MDF_DFLTCICR_DATSRC_Pos             (0U)
#define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
#define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!< Source Data for the digital filter */
#define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
#define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
#define MDF_DFLTCICR_CICMOD_Pos             (4U)
#define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
#define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!< Select the CIC Mode*/
#define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
#define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
#define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
#define MDF_DFLTCICR_MCICD_Pos              (8U)
#define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
#define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!< CIC decimation ratio selection*/
#define MDF_DFLTCICR_SCALE_Pos              (20U)
#define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
#define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!< Scaling factor selection*/

/*******************  Bit definition for MDF/ADF_DFLTxRSFR register  **********/
#define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
#define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
#define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!< Reshape filter bypass*/
#define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
#define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
#define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!< Reshape filter decimation ratio*/
#define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
#define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
#define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!< High-pass filter bypass*/
#define MDF_DFLTRSFR_HPFC_Pos               (8U)
#define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
#define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!< High-pass filter cut-off frequency*/
#define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
#define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)

/*******************  Bit definition for MDF/ADF_DLYxCR register  *************/
#define MDF_DLYCR_SKPDLY_Pos                (0U)
#define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
#define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!< Delay to apply to a bitstream*/
#define MDF_DLYCR_SKPBF_Pos                 (31U)
#define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
#define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!< DSkip Busy Flag*/

/*******************  Bit definition for MDF/ADF_DFLTIER register  ************/
#define MDF_DFLTIER_FTHIE_Pos               (0U)
#define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
#define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!< RXFIFO threshold interrupt enable*/
#define MDF_DFLTIER_DOVRIE_Pos              (1U)
#define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
#define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!< Data overflow interrupt enable*/
#define MDF_DFLTIER_SATIE_Pos               (9U)
#define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
#define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!< Saturation detection interrupt enable*/
#define MDF_DFLTIER_CKABIE_Pos              (10U)
#define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
#define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!< Clock absence detection interrupt enable*/
#define MDF_DFLTIER_RFOVRIE_Pos             (11U)
#define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
#define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!< Reshape filter overrun interrupt enable*/
#define MDF_DFLTIER_SDDETIE_Pos             (12U)
#define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
#define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!< SAD interrupt enable*/
#define MDF_DFLTIER_SDLVLIE_Pos             (13U)
#define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
#define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!< Sound level value ready interrupt enable*/

/*******************  Bit definition for MDF/ADF_DFLTISR register  ************/
#define MDF_DFLTISR_FTHF_Pos                (0U)
#define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
#define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!< RXFIFO threshold interrupt flag*/
#define MDF_DFLTISR_DOVRF_Pos               (1U)
#define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
#define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!< Data overflow interrupt flag*/
#define MDF_DFLTISR_RXNEF_Pos               (3U)
#define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
#define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!< RXFIFO not empty flag*/
#define MDF_DFLTISR_SATF_Pos                (9U)
#define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
#define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!< Saturation detection interrupt flag*/
#define MDF_DFLTISR_CKABF_Pos               (10U)
#define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
#define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!< Clock absence detection interrupt flag*/
#define MDF_DFLTISR_RFOVRF_Pos              (11U)
#define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
#define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!< Reshape filter overrun interrupt flag*/
#define MDF_DFLTISR_SDDETF_Pos              (12U)
#define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
#define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!< SAD interrupt flag*/
#define MDF_DFLTISR_SDLVLF_Pos              (13U)
#define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
#define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!< Sound level value ready interrupt flag*/

/*******************  Bit definition for MDF/ADF_SADCR register  **************/
#define MDF_SADCR_SADEN_Pos                 (0U)
#define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
#define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!< SAD enable*/
#define MDF_SADCR_DATCAP_Pos                (1U)
#define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
#define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!< SAD data capture mode*/
#define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
#define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
#define MDF_SADCR_DETCFG_Pos                (3U)
#define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
#define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!< SAD trigger event configuration*/
#define MDF_SADCR_SADST_Pos                 (4U)
#define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
#define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!< SAD state*/
#define MDF_SADCR_HYSTEN_Pos                (7U)
#define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
#define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!< Hysteresis enable*/
#define MDF_SADCR_FRSIZE_Pos                (8U)
#define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
#define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!< Frame size*/
#define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
#define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
#define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
#define MDF_SADCR_SADMOD_Pos                (12U)
#define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
#define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!< SAD working mode*/
#define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
#define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
#define MDF_SADCR_SADACTIVE_Pos             (31U)
#define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
#define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!< SAD active flag*/

/*******************  Bit definition for MDF/ADF_SADCFGR register  ************/
#define MDF_SADCFGR_SNTHR_Pos               (0U)
#define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
#define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!< Signal to noise threshold*/
#define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
#define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
#define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
#define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
#define MDF_SADCFGR_ANSLP_Pos               (4U)
#define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
#define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!< Ambiant noise slope control*/
#define MDF_SADCFGR_LFRNB_Pos               (8U)
#define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
#define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!< Number of learning frames*/
#define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
#define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
#define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
#define MDF_SADCFGR_HGOVR_Pos               (12U)
#define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
#define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!< Hangover time window*/
#define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
#define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
#define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
#define MDF_SADCFGR_ANMIN_Pos               (16U)
#define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
#define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!< Hangover time window*/

/*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
#define MDF_SADSDLVR_SDLVL_Pos              (0U)
#define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
#define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!< Short term sound level*/

/*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
#define MDF_SADANLVR_ANLVL_Pos              (0U)
#define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
#define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!< Ambiant noise level estimation*/

/*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
#define MDF_DFLTDR_DR_Pos                   (8U)
#define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
#define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!< MCIC decimation counter*/


/******************************************************************************/
/*                                                                            */
/*                                    XSPI                                 */
/*                                                                            */
/******************************************************************************/
/*****************  Bit definition for XSPI_CR register  *******************/
#define XSPI_CR_EN_Pos                   (0U)
#define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)            /*!< 0x00000001 */
#define XSPI_CR_EN                       XSPI_CR_EN_Msk                       /*!< Enable */
#define XSPI_CR_ABORT_Pos                (1U)
#define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
#define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                    /*!< Abort request */
#define XSPI_CR_DMAEN_Pos                (2U)
#define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
#define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
#define XSPI_CR_TCEN_Pos                 (3U)
#define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
#define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
#define XSPI_CR_DMM_Pos                  (6U)
#define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)           /*!< 0x00000040 */
#define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                      /*!< Dual Memory Mode */
#define XSPI_CR_FTHRES_Pos               (8U)
#define XSPI_CR_FTHRES_Msk               (0x1FUL << XSPI_CR_FTHRES_Pos)       /*!< 0x00001F00 */
#define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
#define XSPI_CR_TEIE_Pos                 (16U)
#define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
#define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
#define XSPI_CR_TCIE_Pos                 (17U)
#define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
#define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
#define XSPI_CR_FTIE_Pos                 (18U)
#define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
#define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
#define XSPI_CR_SMIE_Pos                 (19U)
#define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
#define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
#define XSPI_CR_TOIE_Pos                 (20U)
#define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
#define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
#define XSPI_CR_APMS_Pos                 (22U)
#define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)          /*!< 0x00400000 */
#define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
#define XSPI_CR_PMM_Pos                  (23U)
#define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)           /*!< 0x00800000 */
#define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
#define XSPI_CR_CSSEL_Pos                (24U)
#define XSPI_CR_CSSEL_Msk                (0x1UL << XSPI_CR_CSSEL_Pos)         /*!< 0x01000000 */
#define XSPI_CR_CSSEL                    XSPI_CR_CSSEL_Msk                    /*!< Chip Select Selection */
#define XSPI_CR_FMODE_Pos                (28U)
#define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)         /*!< 0x30000000 */
#define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                    /*!< Functional Mode */
#define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)         /*!< 0x10000000 */
#define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)         /*!< 0x20000000 */
#define XSPI_CR_MSEL_Pos                 (30U)
#define XSPI_CR_MSEL_Msk                 (0x3UL << XSPI_CR_MSEL_Pos)          /*!< 0xC0000000 */
#define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                     /*!< Memory Select */
#define XSPI_CR_MSEL_0                   (0x1UL << XSPI_CR_MSEL_Pos)          /*!< 0x40000000 */
#define XSPI_CR_MSEL_1                   (0x2UL << XSPI_CR_MSEL_Pos)          /*!< 0x80000000 */

/****************  Bit definition for XSPI_DCR1 register  ******************/
#define XSPI_DCR1_CKMODE_Pos             (0U)
#define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)      /*!< 0x00000001 */
#define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
#define XSPI_DCR1_FRCK_Pos               (1U)
#define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)        /*!< 0x00000002 */
#define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
#define XSPI_DCR1_CSHT_Pos               (8U)
#define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)       /*!< 0x00003F00 */
#define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
#define XSPI_DCR1_DEVSIZE_Pos            (16U)
#define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)    /*!< 0x001F0000 */
#define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
#define XSPI_DCR1_MTYP_Pos               (24U)
#define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x07000000 */
#define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
#define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x01000000 */
#define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x02000000 */
#define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x04000000 */

/****************  Bit definition for XSPI_DCR2 register  ******************/
#define XSPI_DCR2_PRESCALER_Pos          (0U)
#define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)  /*!< 0x000000FF */
#define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
#define XSPI_DCR2_WRAPSIZE_Pos           (16U)
#define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00070000 */
#define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
#define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00010000 */
#define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00020000 */
#define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00040000 */

/****************  Bit definition for XSPI_DCR3 register  ******************/
#define XSPI_DCR3_CSBOUND_Pos            (16U)
#define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)    /*!< 0x001F0000 */
#define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                /*!< Maximum transfer */
#define XSPI_DCR3_MAXTRAN_Pos            (0U)
#define XSPI_DCR3_MAXTRAN_Msk            (0xFFUL << XSPI_DCR3_MAXTRAN_Pos)    /*!< 0x000000FF */
#define XSPI_DCR3_MAXTRAN                XSPI_DCR3_MAXTRAN_Msk                /*!< Maximum transfer */

/****************  Bit definition for XSPI_DCR4 register  ******************/
#define XSPI_DCR4_REFRESH_Pos            (0U)
#define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
#define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

/*****************  Bit definition for XSPI_SR register  *******************/
#define XSPI_SR_TEF_Pos                  (0U)
#define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)           /*!< 0x00000001 */
#define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
#define XSPI_SR_TCF_Pos                  (1U)
#define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)           /*!< 0x00000002 */
#define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
#define XSPI_SR_FTF_Pos                  (2U)
#define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)           /*!< 0x00000004 */
#define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
#define XSPI_SR_SMF_Pos                  (3U)
#define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)           /*!< 0x00000008 */
#define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                      /*!< Status Match Flag */
#define XSPI_SR_TOF_Pos                  (4U)
#define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)           /*!< 0x00000010 */
#define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                      /*!< Timeout Flag */
#define XSPI_SR_BUSY_Pos                 (5U)
#define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
#define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                     /*!< Busy */
#define XSPI_SR_FLEVEL_Pos               (8U)
#define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)       /*!< 0x00007F00 */
#define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

/****************  Bit definition for XSPI_FCR register  *******************/
#define XSPI_FCR_CTEF_Pos                (0U)
#define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
#define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
#define XSPI_FCR_CTCF_Pos                (1U)
#define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
#define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
#define XSPI_FCR_CSMF_Pos                (3U)
#define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
#define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
#define XSPI_FCR_CTOF_Pos                (4U)
#define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
#define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

/****************  Bit definition for XSPI_DLR register  *******************/
#define XSPI_DLR_DL_Pos                  (0U)
#define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
#define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                      /*!< Data Length */

/*****************  Bit definition for XSPI_AR register  *******************/
#define XSPI_AR_ADDRESS_Pos              (0U)
#define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
#define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                  /*!< Address */

/*****************  Bit definition for XSPI_DR register  *******************/
#define XSPI_DR_DATA_Pos                 (0U)
#define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
#define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                     /*!< Data */

/***************  Bit definition for XSPI_PSMKR register  ******************/
#define XSPI_PSMKR_MASK_Pos              (0U)
#define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
#define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                  /*!< Status mask */

/***************  Bit definition for XSPI_PSMAR register  ******************/
#define XSPI_PSMAR_MATCH_Pos             (0U)
#define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
#define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                 /*!< Status match */

/****************  Bit definition for XSPI_PIR register  *******************/
#define XSPI_PIR_INTERVAL_Pos            (0U)
#define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
#define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

/****************  Bit definition for XSPI_CCR register  *******************/
#define XSPI_CCR_IMODE_Pos               (0U)
#define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000007 */
#define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
#define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000001 */
#define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000002 */
#define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000004 */
#define XSPI_CCR_IDTR_Pos                (3U)
#define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)         /*!< 0x00000008 */
#define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
#define XSPI_CCR_ISIZE_Pos               (4U)
#define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000030 */
#define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
#define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000010 */
#define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000020 */
#define XSPI_CCR_ADMODE_Pos              (8U)
#define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000700 */
#define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
#define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000100 */
#define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000200 */
#define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
#define XSPI_CCR_ADDTR_Pos               (11U)
#define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)        /*!< 0x00000800 */
#define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
#define XSPI_CCR_ADSIZE_Pos              (12U)
#define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
#define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
#define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
#define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
#define XSPI_CCR_ABMODE_Pos              (16U)
#define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00070000 */
#define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
#define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00010000 */
#define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00020000 */
#define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00040000 */
#define XSPI_CCR_ABDTR_Pos               (19U)
#define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)        /*!< 0x00080000 */
#define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_CCR_ABSIZE_Pos              (20U)
#define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00300000 */
#define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
#define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00100000 */
#define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00200000 */
#define XSPI_CCR_DMODE_Pos               (24U)
#define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)        /*!< 0x07000000 */
#define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                   /*!< Data Mode */
#define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
#define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
#define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)        /*!< 0x04000000 */
#define XSPI_CCR_DDTR_Pos                (27U)
#define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)         /*!< 0x08000000 */
#define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
#define XSPI_CCR_DQSE_Pos                (29U)
#define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)         /*!< 0x20000000 */
#define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

/****************  Bit definition for XSPI_TCR register  *******************/
#define XSPI_TCR_DCYC_Pos                (0U)
#define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)        /*!< 0x0000001F */
#define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
#define XSPI_TCR_DHQC_Pos                (28U)
#define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)         /*!< 0x10000000 */
#define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
#define XSPI_TCR_SSHIFT_Pos              (30U)
#define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)       /*!< 0x40000000 */
#define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

/*****************  Bit definition for XSPI_IR register  *******************/
#define XSPI_IR_INSTRUCTION_Pos          (0U)
#define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
#define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

/****************  Bit definition for XSPI_ABR register  *******************/
#define XSPI_ABR_ALTERNATE_Pos           (0U)
#define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

/****************  Bit definition for XSPI_LPTR register  ******************/
#define XSPI_LPTR_TIMEOUT_Pos            (0U)
#define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
#define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

/****************  Bit definition for XSPI_WPCCR register  *******************/
#define XSPI_WPCCR_IMODE_Pos             (0U)
#define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000007 */
#define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
#define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000001 */
#define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000002 */
#define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000004 */
#define XSPI_WPCCR_IDTR_Pos              (3U)
#define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)       /*!< 0x00000008 */
#define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
#define XSPI_WPCCR_ISIZE_Pos             (4U)
#define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000030 */
#define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
#define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000010 */
#define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000020 */
#define XSPI_WPCCR_ADMODE_Pos            (8U)
#define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000700 */
#define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
#define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000100 */
#define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000200 */
#define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000400 */
#define XSPI_WPCCR_ADDTR_Pos             (11U)
#define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)      /*!< 0x00000800 */
#define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
#define XSPI_WPCCR_ADSIZE_Pos            (12U)
#define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00003000 */
#define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
#define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00001000 */
#define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00002000 */
#define XSPI_WPCCR_ABMODE_Pos            (16U)
#define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00070000 */
#define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
#define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00010000 */
#define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00020000 */
#define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00040000 */
#define XSPI_WPCCR_ABDTR_Pos             (19U)
#define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)      /*!< 0x00080000 */
#define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_WPCCR_ABSIZE_Pos            (20U)
#define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00300000 */
#define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
#define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00100000 */
#define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00200000 */
#define XSPI_WPCCR_DMODE_Pos             (24U)
#define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x07000000 */
#define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
#define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x01000000 */
#define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x02000000 */
#define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x04000000 */
#define XSPI_WPCCR_DDTR_Pos              (27U)
#define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)       /*!< 0x08000000 */
#define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
#define XSPI_WPCCR_DQSE_Pos              (29U)
#define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)       /*!< 0x20000000 */
#define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

/****************  Bit definition for XSPI_WPTCR register  *******************/
#define XSPI_WPTCR_DCYC_Pos              (0U)
#define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)      /*!< 0x0000001F */
#define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
#define XSPI_WPTCR_DHQC_Pos              (28U)
#define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)       /*!< 0x10000000 */
#define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
#define XSPI_WPTCR_SSHIFT_Pos            (30U)
#define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)     /*!< 0x40000000 */
#define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

/*****************  Bit definition for XSPI_WPIR register  *******************/
#define XSPI_WPIR_INSTRUCTION_Pos        (0U)
#define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

/****************  Bit definition for XSPI_WPABR register  *******************/
#define XSPI_WPABR_ALTERNATE_Pos         (0U)
#define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

/****************  Bit definition for XSPI_WCCR register  ******************/
#define XSPI_WCCR_IMODE_Pos              (0U)
#define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000007 */
#define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
#define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000001 */
#define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000002 */
#define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000004 */
#define XSPI_WCCR_IDTR_Pos               (3U)
#define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)        /*!< 0x00000008 */
#define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
#define XSPI_WCCR_ISIZE_Pos              (4U)
#define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000030 */
#define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
#define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000010 */
#define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000020 */
#define XSPI_WCCR_ADMODE_Pos             (8U)
#define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000700 */
#define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
#define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000100 */
#define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000200 */
#define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000400 */
#define XSPI_WCCR_ADDTR_Pos              (11U)
#define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)       /*!< 0x00000800 */
#define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
#define XSPI_WCCR_ADSIZE_Pos             (12U)
#define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00003000 */
#define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
#define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00001000 */
#define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00002000 */
#define XSPI_WCCR_ABMODE_Pos             (16U)
#define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00070000 */
#define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
#define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00010000 */
#define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00020000 */
#define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00040000 */
#define XSPI_WCCR_ABDTR_Pos              (19U)
#define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)       /*!< 0x00080000 */
#define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_WCCR_ABSIZE_Pos             (20U)
#define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00300000 */
#define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
#define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00100000 */
#define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00200000 */
#define XSPI_WCCR_DMODE_Pos              (24U)
#define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x07000000 */
#define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
#define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x01000000 */
#define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x02000000 */
#define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x04000000 */
#define XSPI_WCCR_DDTR_Pos               (27U)
#define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)        /*!< 0x08000000 */
#define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
#define XSPI_WCCR_DQSE_Pos               (29U)
#define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)        /*!< 0x20000000 */
#define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

/****************  Bit definition for XSPI_WTCR register  ******************/
#define XSPI_WTCR_DCYC_Pos               (0U)
#define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)       /*!< 0x0000001F */
#define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

/****************  Bit definition for XSPI_WIR register  *******************/
#define XSPI_WIR_INSTRUCTION_Pos         (0U)
#define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

/****************  Bit definition for XSPI_WABR register  ******************/
#define XSPI_WABR_ALTERNATE_Pos          (0U)
#define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

/****************  Bit definition for XSPI_HLCR register  ******************/
#define XSPI_HLCR_LM_Pos                 (0U)
#define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)          /*!< 0x00000001 */
#define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                     /*!< Latency Mode */
#define XSPI_HLCR_WZL_Pos                (1U)
#define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)         /*!< 0x00000002 */
#define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
#define XSPI_HLCR_TACC_Pos               (8U)
#define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)       /*!< 0x0000FF00 */
#define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                   /*!< Access Time */
#define XSPI_HLCR_TRWR_Pos               (16U)
#define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)       /*!< 0x00FF0000 */
#define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

/****************  Bit definition for XSPI_CALFCR register  ****************/
#define XSPI_CALFCR_FINE_Pos             (0U)
#define XSPI_CALFCR_FINE_Msk             (0x7FUL << XSPI_CALFCR_FINE_Pos)     /*!< 0x0000007F */
#define XSPI_CALFCR_FINE                 XSPI_CALFCR_FINE_Msk                 /*!< Fine Calibration */
#define XSPI_CALFCR_COARSE_Pos           (16U)
#define XSPI_CALFCR_COARSE_Msk           (0x1FUL << XSPI_CALFCR_COARSE_Pos)   /*!< 0x001F0000 */
#define XSPI_CALFCR_COARSE               XSPI_CALFCR_COARSE_Msk               /*!< Coarse Calibration */
#define XSPI_CALFCR_CALMAX_Pos           (31U)
#define XSPI_CALFCR_CALMAX_Msk           (0x1UL << XSPI_CALFCR_CALMAX_Pos)    /*!< 0x80000000 */
#define XSPI_CALFCR_CALMAX               XSPI_CALFCR_CALMAX_Msk               /*!< Max Value */

/****************  Bit definition for XSPI_CALMR register  *****************/
#define XSPI_CALMR_FINE_Pos              (0U)
#define XSPI_CALMR_FINE_Msk              (0x7FUL << XSPI_CALMR_FINE_Pos)      /*!< 0x0000007F */
#define XSPI_CALMR_FINE                  XSPI_CALMR_FINE_Msk                  /*!< Fine Calibration */
#define XSPI_CALMR_COARSE_Pos            (16U)
#define XSPI_CALMR_COARSE_Msk            (0x1FUL << XSPI_CALMR_COARSE_Pos)    /*!< 0x001F0000 */
#define XSPI_CALMR_COARSE                XSPI_CALMR_COARSE_Msk                /*!< Coarse Calibration */

/****************  Bit definition for XSPI_CALSOR register  ****************/
#define XSPI_CALSOR_FINE_Pos             (0U)
#define XSPI_CALSOR_FINE_Msk             (0x7FUL << XSPI_CALSOR_FINE_Pos)     /*!< 0x0000007F */
#define XSPI_CALSOR_FINE                 XSPI_CALSOR_FINE_Msk                 /*!< Fine Calibration */
#define XSPI_CALSOR_COARSE_Pos           (16U)
#define XSPI_CALSOR_COARSE_Msk           (0x1FUL << XSPI_CALSOR_COARSE_Pos)   /*!< 0x001F0000 */
#define XSPI_CALSOR_COARSE               XSPI_CALSOR_COARSE_Msk               /*!< Coarse Calibration */

/****************  Bit definition for XSPI_CALSIR register  ****************/
#define XSPI_CALSIR_FINE_Pos             (0U)
#define XSPI_CALSIR_FINE_Msk             (0x7FUL << XSPI_CALSIR_FINE_Pos)     /*!< 0x0000007F */
#define XSPI_CALSIR_FINE                 XSPI_CALSIR_FINE_Msk                 /*!< Fine Calibration */
#define XSPI_CALSIR_COARSE_Pos           (16U)
#define XSPI_CALSIR_COARSE_Msk           (0x1FUL << XSPI_CALSIR_COARSE_Pos)   /*!< 0x001F0000 */
#define XSPI_CALSIR_COARSE               XSPI_CALSIR_COARSE_Msk               /*!< Coarse Calibration */


/******************************************************************************/
/*                                                                            */
/*                                  XSPIM                                  */
/*                                                                            */
/******************************************************************************/
/***************  Bit definition for XSPIM_CR register  ********************/
#define XSPIM_CR_MUXEN_Pos               (0U)
#define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
#define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                   /*!< Multiplexed Mode Enable */
#define XSPIM_CR_MODE_Pos                (1U)
#define XSPIM_CR_MODE_Msk                (0x1UL << XSPIM_CR_MODE_Pos)         /*!< 0x00000002 */
#define XSPIM_CR_MODE                    XSPIM_CR_MODE_Msk                    /*!< Multiplexing Mode */
#define XSPIM_CR_CSSEL_OVR_EN_Pos        (4U)
#define XSPIM_CR_CSSEL_OVR_EN_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
#define XSPIM_CR_CSSEL_OVR_EN            XSPIM_CR_CSSEL_OVR_EN_Msk            /*!< Chip select selector override enable */
#define XSPIM_CR_CSSEL_OVR_O1_Pos        (5U)
#define XSPIM_CR_CSSEL_OVR_O1_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
#define XSPIM_CR_CSSEL_OVR_O1            XSPIM_CR_CSSEL_OVR_O1_Msk            /*!< Chip select selector override setting for XSPI1 */
#define XSPIM_CR_CSSEL_OVR_O2_Pos        (6U)
#define XSPIM_CR_CSSEL_OVR_O2_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
#define XSPIM_CR_CSSEL_OVR_O2            XSPIM_CR_CSSEL_OVR_O2_Msk            /*!< Chip select selector override setting for XSPI2 */
#define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
#define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK Time */

/******************************************************************************/
/*                                                                            */
/*                       Public Key Accelerator (PKA)                         */
/*                                                                            */
/******************************************************************************/
/******************************* PKA Version **********************************/
#define PKA2_V1

/*******************  Bit definition for PKA_CR register  *********************/
#define PKA_CR_EN_Pos                       (0U)
#define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
#define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
#define PKA_CR_START_Pos                    (1U)
#define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
#define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
#define PKA_CR_MODE_Pos                     (8U)
#define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
#define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
#define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
#define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
#define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
#define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
#define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
#define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
#define PKA_CR_PROCENDIE_Pos                (17U)
#define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
#define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
#define PKA_CR_RAMERRIE_Pos                 (19U)
#define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
#define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
#define PKA_CR_ADDRERRIE_Pos                (20U)
#define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
#define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
#define PKA_CR_OPERRIE_Pos                  (21U)
#define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
#define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */

/*******************  Bit definition for PKA_SR register  *********************/
#define PKA_SR_INITOK_Pos                   (0U)
#define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
#define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
#define PKA_SR_LMF_Pos                      (1U)
#define PKA_SR_LMF_Msk                      (0x1UL << PKA_SR_LMF_Pos)               /*!< 0x00000002 */
#define PKA_SR_LMF                          PKA_SR_LMF_Msk                          /*!< Limited mode flag */
#define PKA_SR_BUSY_Pos                     (16U)
#define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
#define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
#define PKA_SR_PROCENDF_Pos                 (17U)
#define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
#define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
#define PKA_SR_RAMERRF_Pos                  (19U)
#define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
#define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
#define PKA_SR_ADDRERRF_Pos                 (20U)
#define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
#define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
#define PKA_SR_OPERRF_Pos                   (21U)
#define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
#define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/

/*******************  Bit definition for PKA_CLRFR register  ******************/
#define PKA_CLRFR_PROCENDFC_Pos             (17U)
#define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
#define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
#define PKA_CLRFR_RAMERRFC_Pos              (19U)
#define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
#define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
#define PKA_CLRFR_ADDRERRFC_Pos             (20U)
#define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
#define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
#define PKA_CLRFR_OPERRFC_Pos               (21U)
#define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
#define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/

/*******************  Bits definition for PKA RAM  *************************/
#define PKA_RAM_OFFSET                                 (0x0400UL)                   /*!< PKA RAM address offset */

/* Compute Montgomery parameter input data */
#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */

/* Compute Montgomery parameter output data */
#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */

/* Compute modular exponentiation input data */
#define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
#define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
#define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
#define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
#define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
#define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */

/* Compute modular exponentiation output data */
#define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
#define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */

/* Compute ECC scalar multiplication input data */
#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */

/* Compute ECC scalar multiplication output data */
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
#define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */

/* Point check input data */
#define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
#define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */

/* Point check output data */
#define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */

/* ECDSA signature input data */
#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
#define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
#define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */

/* ECDSA signature output data */
#define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */

/* ECDSA verification input data */
#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
#define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
#define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
#define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
#define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */

/* ECDSA verification output data */
#define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* RSA CRT exponentiation input data */
#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
#define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
#define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
#define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
#define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
#define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */

/* RSA CRT exponentiation output data */
#define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular reduction input data */
#define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
#define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
#define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
#define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */

/* Modular reduction output data */
#define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Arithmetic addition input data */
#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Arithmetic multiplication input data */
#define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Arithmetic multiplication output data */
#define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Comparison input data */
#define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Comparison output data */
#define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular addition input data */
#define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */

/* Modular addition output data */
#define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular inversion input data */
#define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */

/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular subtraction input data */
#define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */

/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Montgomery multiplication input data */
#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */

/* Montgomery multiplication output data */
#define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Generic Arithmetic input data */
#define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */

/* Generic Arithmetic output data */
#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */

/* Compute ECC complete addition input data */
#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
#define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */

/* Compute ECC complete addition output data */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */

/* Compute ECC double base ladder input data */
#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */

/* Compute ECC double base ladder output data */
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate (affine coordinate) */
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate (affine coordinate) */
#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */

/* Compute ECC projective to affine conversion input data */
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P X coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P Y coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P Z coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */

/* Compute ECC projective to affine conversion output data */
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result x affine coordinate */
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result y affine coordinate */
#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */


/******************************************************************************/
/*                                                                            */
/*                Parallel Synchronous Slave Interface (PSSI )                */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for PSSI_CR register  *******************/
#define PSSI_CR_CKPOL_Pos              (5U)
#define PSSI_CR_CKPOL_Msk              (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
#define PSSI_CR_CKPOL                  PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
#define PSSI_CR_DEPOL_Pos              (6U)
#define PSSI_CR_DEPOL_Msk              (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
#define PSSI_CR_DEPOL                  PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
#define PSSI_CR_RDYPOL_Pos             (8U)
#define PSSI_CR_RDYPOL_Msk             (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
#define PSSI_CR_RDYPOL                 PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
#define PSSI_CR_EDM_Pos                (10U)
#define PSSI_CR_EDM_Msk                (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
#define PSSI_CR_EDM                    PSSI_CR_EDM_Msk                         /*!< Extended data mode */
#define PSSI_CR_ENABLE_Pos             (14U)
#define PSSI_CR_ENABLE_Msk             (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
#define PSSI_CR_ENABLE                 PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
#define PSSI_CR_DERDYCFG_Pos           (18U)
#define PSSI_CR_DERDYCFG_Msk           (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
#define PSSI_CR_DERDYCFG               PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
#define PSSI_CR_CKSRC_Pos              (29U)
#define PSSI_CR_CKSRC_Msk              (0x1UL << PSSI_CR_CKSRC_Pos)            /*!< 0x20000000 */
#define PSSI_CR_CKSRC                  PSSI_CR_CKSRC_Msk                       /*!< Clock source */
#define PSSI_CR_DMAEN_Pos              (30U)
#define PSSI_CR_DMAEN_Msk              (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
#define PSSI_CR_DMAEN                  PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
#define PSSI_CR_OUTEN_Pos              (31U)
#define PSSI_CR_OUTEN_Msk              (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
#define PSSI_CR_OUTEN                  PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */

/********************  Bit definition for PSSI_SR register  *******************/
#define PSSI_SR_RTT4B_Pos              (2U)
#define PSSI_SR_RTT4B_Msk              (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
#define PSSI_SR_RTT4B                  PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
#define PSSI_SR_RTT1B_Pos              (3U)
#define PSSI_SR_RTT1B_Msk              (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
#define PSSI_SR_RTT1B                  PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */

/********************  Bit definition for PSSI_RIS register  ******************/
#define PSSI_RIS_OVR_RIS_Pos           (1U)
#define PSSI_RIS_OVR_RIS_Msk           (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
#define PSSI_RIS_OVR_RIS               PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */

/********************  Bit definition for PSSI_IER register  ******************/
#define PSSI_IER_OVR_IE_Pos            (1U)
#define PSSI_IER_OVR_IE_Msk            (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
#define PSSI_IER_OVR_IE                PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */

/********************  Bit definition for PSSI_MIS register  ******************/
#define PSSI_MIS_OVR_MIS_Pos           (1U)
#define PSSI_MIS_OVR_MIS_Msk           (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
#define PSSI_MIS_OVR_MIS               PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */

/********************  Bit definition for PSSI_ICR register  ******************/
#define PSSI_ICR_OVR_ISC_Pos           (1U)
#define PSSI_ICR_OVR_ISC_Msk           (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
#define PSSI_ICR_OVR_ISC               PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */

/********************  Bit definition for PSSI_DR register  *******************/
#define PSSI_DR_DR_Pos                 (0U)
#define PSSI_DR_DR_Msk                 (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
#define PSSI_DR_DR                     PSSI_DR_DR_Msk                          /*!< Data register  */


/******************************************************************************/
/*                                                                            */
/*                             Power Control                                  */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for PWR_CR1 register  *******************/
#define PWR_CR1_SVOS_Pos               (0U)
#define PWR_CR1_SVOS_Msk               (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00000001 */
#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection. */

#define PWR_CR1_PVDE_Pos               (4U)
#define PWR_CR1_PVDE_Msk               (0x1UL << PWR_CR1_PVDE_Pos)             /*!< 0x00000010 */
#define PWR_CR1_PVDE                   PWR_CR1_PVDE_Msk                        /*!< Programmable Voltage detector enable. */

#define PWR_CR1_PLS_Pos                (5U)
#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

#define PWR_CR1_DBP_Pos                (8U)
#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

#define PWR_CR1_FLPS_Pos               (9U)
#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in STOP */

#define PWR_CR1_BOOSTE_Pos             (11U)
#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00000800 */
#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control. */

#define PWR_CR1_AVDREADY_Pos           (12)
#define PWR_CR1_AVDREADY_Msk           (0x1UL << PWR_CR1_AVDREADY_Pos)         /*!< 0x00001000 */
#define PWR_CR1_AVDREADY               PWR_CR1_AVDREADY_Msk                    /*!< Analog Voltage Ready. */

#define PWR_CR1_AVDEN_Pos              (13U)
#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00002000 */
#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable       */

#define PWR_CR1_ALS_Pos                (14U)
#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x0000A000 */
#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00004000 */
#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00008000 */

/********************  Bit definition for PWR_SR1 register  ********************/
#define PWR_SR1_ACTVOS_Pos             (0U)
#define PWR_SR1_ACTVOS_Msk             (0x1UL << PWR_SR1_ACTVOS_Pos)              /*!< 0x00000001 */
#define PWR_SR1_ACTVOS                 PWR_SR1_ACTVOS_Msk                         /*!< VOS currently applied for VCORE voltage scaling selection */

#define PWR_SR1_ACTVOSRDY_Pos          (1U)
#define PWR_SR1_ACTVOSRDY_Msk          (0x1UL << PWR_SR1_ACTVOSRDY_Pos)         /*!< 0x00000002 */
#define PWR_SR1_ACTVOSRDY              PWR_SR1_ACTVOSRDY_Msk                    /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

#define PWR_SR1_PVDO_Pos               (4U)
#define PWR_SR1_PVDO_Msk               (0x1UL << PWR_SR1_PVDO_Pos)              /*!< 0x00000010 */
#define PWR_SR1_PVDO                   PWR_SR1_PVDO_Msk                         /*!< Programmable Voltage Detect Output */

#define PWR_SR1_AVDO_Pos               (13U)
#define PWR_SR1_AVDO_Msk               (0x1UL << PWR_SR1_AVDO_Pos)              /*!< 0x00002000 */
#define PWR_SR1_AVDO                   PWR_SR1_AVDO_Msk                         /*!< Analog Voltage Detect Output on VDDA */

/********************  Bit definition for PWR_CSR1 register  ********************/
#define PWR_CSR1_BREN_Pos              (0U)
#define PWR_CSR1_BREN_Msk              (0x1UL << PWR_CSR1_BREN_Pos)            /*!< 0x00000001 */
#define PWR_CSR1_BREN                  PWR_CSR1_BREN_Msk                       /*!< Backup regulator enable */

#define PWR_CSR1_MONEN_Pos             (4U)
#define PWR_CSR1_MONEN_Msk             (0x1UL << PWR_CSR1_MONEN_Pos)           /*!< 0x00000010 */
#define PWR_CSR1_MONEN                 PWR_CSR1_MONEN_Msk                      /*!< VBAT and temperature monitoring enable */

#define PWR_CSR1_BRRDY_Pos             (16U)
#define PWR_CSR1_BRRDY_Msk             (0x1UL << PWR_CSR1_BRRDY_Pos)            /*!< 0x00010000 */
#define PWR_CSR1_BRRDY                 PWR_CSR1_BRRDY_Msk                       /*!< Backup regulator ready */

#define PWR_CSR1_VBATL_Pos             (20U)
#define PWR_CSR1_VBATL_Msk             (0x1UL << PWR_CSR1_VBATL_Pos)           /*!< 0x00100000 */
#define PWR_CSR1_VBATL                 PWR_CSR1_VBATL_Msk                      /*!< Monitored VBAT level above low threshold */

#define PWR_CSR1_VBATH_Pos             (21U)
#define PWR_CSR1_VBATH_Msk             (0x1UL << PWR_CSR1_VBATH_Pos)           /*!< 0x00200000 */
#define PWR_CSR1_VBATH                 PWR_CSR1_VBATH_Msk                      /*!< Monitored VBAT level above high threshold */

#define PWR_CSR1_TEMPL_Pos             (22U)
#define PWR_CSR1_TEMPL_Msk             (0x1UL << PWR_CSR1_TEMPL_Pos)           /*!< 0x00400000 */
#define PWR_CSR1_TEMPL                 PWR_CSR1_TEMPL_Msk                      /*!< Monitored temperature level above low threshold */

#define PWR_CSR1_TEMPH_Pos             (23U)
#define PWR_CSR1_TEMPH_Msk             (0x1UL << PWR_CSR1_TEMPH_Pos)           /*!< 0x00800000 */
#define PWR_CSR1_TEMPH                 PWR_CSR1_TEMPH_Msk                      /*!< Monitored temperature level above high threshold */

/********************  Bit definition for PWR_CSR2 register  ********************/
#define PWR_CSR2_BYPASS_Pos            (0U)
#define PWR_CSR2_BYPASS_Msk            (0x1UL << PWR_CSR2_BYPASS_Pos)           /*!< 0x00000001 */
#define PWR_CSR2_BYPASS                PWR_CSR2_BYPASS_Msk                      /*!< Power Management Unit bypass */

#define PWR_CSR2_LDOEN_Pos             (1U)
#define PWR_CSR2_LDOEN_Msk             (0x1UL << PWR_CSR2_LDOEN_Pos)            /*!< 0x00000002 */
#define PWR_CSR2_LDOEN                 PWR_CSR2_LDOEN_Msk                       /*!< Low Drop-Out regulator enable */

#define PWR_CSR2_SDEN_Pos              (2U)
#define PWR_CSR2_SDEN_Msk              (0x1UL << PWR_CSR2_SDEN_Pos)            /*!< 0x00000004 */
#define PWR_CSR2_SDEN                  PWR_CSR2_SDEN_Msk                       /*!< SMPS Step-down converter enable */

#define PWR_CSR2_SMPSEXTHP_Pos         (3U)
#define PWR_CSR2_SMPSEXTHP_Msk         (0x1UL << PWR_CSR2_SMPSEXTHP_Pos)        /*!< 0x00000008 */
#define PWR_CSR2_SMPSEXTHP             PWR_CSR2_SMPSEXTHP_Msk                   /*!< SMPS external power delivery selection */

#define PWR_CSR2_SDHILEVEL_Pos         (4U)
#define PWR_CSR2_SDHILEVEL_Msk         (0x1UL << PWR_CSR2_SDHILEVEL_Pos)        /*!< 0x00000030 */
#define PWR_CSR2_SDHILEVEL             PWR_CSR2_SDHILEVEL_Msk                   /*!< SMPS step-down converter voltage output for LDO or external supply */

#define PWR_CSR2_VBE_Pos               (8U)
#define PWR_CSR2_VBE_Msk               (0x1UL << PWR_CSR2_VBE_Pos)              /*!< 0x00000100 */
#define PWR_CSR2_VBE                   PWR_CSR2_VBE_Msk                         /*!< VBAT charging enable */

#define PWR_CSR2_VBRS_Pos              (9U)
#define PWR_CSR2_VBRS_Msk              (0x1UL << PWR_CSR2_VBRS_Pos)             /*!< 0x00000200 */
#define PWR_CSR2_VBRS                  PWR_CSR2_VBRS_Msk                        /*!< VBAT charging resistor selection */

#define PWR_CSR2_XSPICAP1_Pos          (10U)
#define PWR_CSR2_XSPICAP1_Msk          (0x3UL << PWR_CSR2_XSPICAP1_Pos)         /*!< 0x00000C00 */
#define PWR_CSR2_XSPICAP1              PWR_CSR2_XSPICAP1_Msk                    /*!< XSPI port 1 capacitor control bits */
#define PWR_CSR2_XSPICAP1_0            (0x1UL << PWR_CSR2_XSPICAP1_Pos)         /*!< 0x00000400 */
#define PWR_CSR2_XSPICAP1_1            (0x2UL << PWR_CSR2_XSPICAP1_Pos)         /*!< 0x00000800 */

#define PWR_CSR2_XSPICAP2_Pos          (12U)
#define PWR_CSR2_XSPICAP2_Msk          (0x3UL << PWR_CSR2_XSPICAP2_Pos)         /*!< 0x00003000 */
#define PWR_CSR2_XSPICAP2              PWR_CSR2_XSPICAP2_Msk                    /*!< XSPI port 2 capacitor control bits */
#define PWR_CSR2_XSPICAP2_0            (0x1UL << PWR_CSR2_XSPICAP2_Pos)         /*!< 0x00001000 */
#define PWR_CSR2_XSPICAP2_1            (0x2UL << PWR_CSR2_XSPICAP2_Pos)         /*!< 0x00002000 */

#define PWR_CSR2_EN_XSPIM1_Pos         (14U)
#define PWR_CSR2_EN_XSPIM1_Msk         (0x1UL << PWR_CSR2_EN_XSPIM1_Pos)        /*!< 0x00004000 */
#define PWR_CSR2_EN_XSPIM1             PWR_CSR2_EN_XSPIM1_Msk                   /*!< XSPIM1 external supply enable */

#define PWR_CSR2_EN_XSPIM2_Pos         (15U)
#define PWR_CSR2_EN_XSPIM2_Msk         (0x1UL << PWR_CSR2_EN_XSPIM2_Pos)         /*!< 0x00008000 */
#define PWR_CSR2_EN_XSPIM2             PWR_CSR2_EN_XSPIM2_Msk                    /*!< XSPIM2 external supply enable */

#define PWR_CSR2_SDEXTRDY_Pos          (16U)
#define PWR_CSR2_SDEXTRDY_Msk          (0x1UL << PWR_CSR2_SDEXTRDY_Pos)         /*!< 0x00010000 */
#define PWR_CSR2_SDEXTRDY              PWR_CSR2_SDEXTRDY_Msk                    /*!< SMPS External supply ready */

#define PWR_CSR2_USB33DEN_Pos          (24U)
#define PWR_CSR2_USB33DEN_Msk          (0x1UL << PWR_CSR2_USB33DEN_Pos)         /*!< 0x01000000 */
#define PWR_CSR2_USB33DEN              PWR_CSR2_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

#define PWR_CSR2_USBREGEN_Pos          (25U)
#define PWR_CSR2_USBREGEN_Msk          (0x1UL << PWR_CSR2_USBREGEN_Pos)         /*!< 0x02000000 */
#define PWR_CSR2_USBREGEN              PWR_CSR2_USBREGEN_Msk                    /*!< USB regulator enable */

#define PWR_CSR2_USB33RDY_Pos          (26U)
#define PWR_CSR2_USB33RDY_Msk          (0x1UL << PWR_CSR2_USB33RDY_Pos)         /*!< 0x04000000 */
#define PWR_CSR2_USB33RDY              PWR_CSR2_USB33RDY_Msk                    /*!< USB supply ready */

#define PWR_CSR2_USBHSREGEN_Pos        (27U)
#define PWR_CSR2_USBHSREGEN_Msk        (0x1UL << PWR_CSR2_USBHSREGEN_Pos)       /*!< 0x08000000 */
#define PWR_CSR2_USBHSREGEN            PWR_CSR2_USBHSREGEN_Msk                  /*!< USB HS regulator enable */

/********************  Bit definition for PWR_CSR3 register  ********************/
#define PWR_CSR3_PDDS_Pos              (0U)
#define PWR_CSR3_PDDS_Msk              (0x1UL << PWR_CSR3_PDDS_Pos)            /*!< 0x00000001 */
#define PWR_CSR3_PDDS                  PWR_CSR3_PDDS_Msk                       /*!< D1 domain Power Down Deepsleep  */

#define PWR_CSR3_CSSF_Pos              (1U)
#define PWR_CSR3_CSSF_Msk              (0x1UL << PWR_CSR3_CSSF_Pos)            /*!< 0x00000002 */
#define PWR_CSR3_CSSF                  PWR_CSR3_CSSF_Msk                       /*!< Clear Standby and Stop flag */

#define PWR_CSR3_STOPF_Pos             (8U)
#define PWR_CSR3_STOPF_Msk             (0x1UL << PWR_CSR3_STOPF_Pos)            /*!< 0x00000080 */
#define PWR_CSR3_STOPF                 PWR_CSR3_STOPF_Msk                       /*!< STOP Flag */

#define PWR_CSR3_SBF_Pos               (9U)
#define PWR_CSR3_SBF_Msk               (0x1UL << PWR_CSR3_SBF_Pos)              /*!< 0x00000100 */
#define PWR_CSR3_SBF                   PWR_CSR3_SBF_Msk                         /*!< System STANDBY Flag */

/********************  Bit definition for PWR_CSR4 register  ********************/
#define PWR_CSR4_VOS_Pos               (0U)
#define PWR_CSR4_VOS_Msk               (0x1UL << PWR_CSR4_VOS_Pos)            /*!< 0x00000001 */
#define PWR_CSR4_VOS                   PWR_CSR4_VOS_Msk                       /*!< Voltage Scaling selection according performance */

#define PWR_CSR4_VOSRDY_Pos            (1U)
#define PWR_CSR4_VOSRDY_Msk            (0x1UL << PWR_CSR4_VOSRDY_Pos)         /*!< 0x00000002 */
#define PWR_CSR4_VOSRDY                PWR_CSR4_VOSRDY_Msk                    /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */

/********************  Bit definition for PWR_WKUPCR register  ********************/
#define PWR_WKUPCR_WKUPC_Pos           (0U)
#define PWR_WKUPCR_WKUPC_Msk           (0xFUL << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000000F */
#define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Clear Wakeup Pin Flag 1 to 4 */
#define PWR_WKUPCR_WKUPC1_Pos          (0U)
#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
#define PWR_WKUPCR_WKUPC2_Pos          (1U)
#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
#define PWR_WKUPCR_WKUPC3_Pos          (2U)
#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
#define PWR_WKUPCR_WKUPC4_Pos          (3U)
#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

/********************  Bit definition for PWR_WKUPFR register  ********************/
#define PWR_WKUPFR_WKUPF1_Pos          (0U)
#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
#define PWR_WKUPFR_WKUPF2_Pos          (1U)
#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
#define PWR_WKUPFR_WKUPF3_Pos          (2U)
#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
#define PWR_WKUPFR_WKUPF4_Pos          (3U)
#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

/********************  Bit definition for PWR_WKUPEPR register  ********************/
#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
#define PWR_WKUPEPR_WKUPEN_Msk         (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000000F */
#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

#define PWR_WKUPEPR_WKUPP_Pos          (8U)
#define PWR_WKUPEPR_WKUPP_Msk          (0x0FUL << PWR_WKUPEPR_WKUPP_Pos)        /*!< 0x0000F00 */
#define PWR_WKUPEPR_WKUPP              PWR_WKUPEPR_WKUPP_Msk                    /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00010000 */
#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00020000 */
#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00040000 */
#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00080000 */
#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00100000 */
#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00200000 */
#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00400000 */
#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00800000 */

/********************  Bit definition for PWR_UCPDRR register   ********************/
#define PWR_UCPDR_UCPD_DBDIS_Pos       (0U)
#define PWR_UCPDR_UCPD_DBDIS_Msk       (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos)     /*!< 0x00000001 */
#define PWR_UCPDR_UCPD_DBDIS           PWR_UCPDR_UCPD_DBDIS_Msk                /*!< UCPD dead battery disable */

#define PWR_UCPDR_UCPD_STBY_Pos        (1U)
#define PWR_UCPDR_UCPD_STBY_Msk        (0x1UL << PWR_UCPDR_UCPD_STBY_Pos)      /*!< 0x00000002 */
#define PWR_UCPDR_UCPD_STBY            PWR_UCPDR_UCPD_STBY_Msk                 /*!< UCPD Standby mode */

/********************  Bit definition for PWR_APCR  register  ********************/
#define PWR_APCR_APC_Pos               (0U)
#define PWR_APCR_APC_Msk               (0x1UL << PWR_APCR_APC_Pos)             /*!< 0x00000001 */
#define PWR_APCR_APC                   PWR_APCR_APC_Msk                        /*!< Apply pull configuration register */

#define PWR_APCR_PN7_PUPD_Pos          (16U)
#define PWR_APCR_PN7_PUPD_Msk          (0x1UL << PWR_APCR_PN7_PUPD_Pos)        /*!< 0x00010000 */
#define PWR_APCR_PN7_PUPD              PWR_APCR_PN7_PUPD_Msk                   /*!< Port N bit 7 pull-up/down configuration */

#define PWR_APCR_PO5_PUPD_Pos          (17)
#define PWR_APCR_PO5_PUPD_Msk          (0x1UL << PWR_APCR_PO5_PUPD_Pos)        /*!< 0x00020000 */
#define PWR_APCR_PO5_PUPD              PWR_APCR_PO5_PUPD_Msk                   /*!< Port O bit 5 pull-up/down configuration */

#define PWR_APCR_I3CPB6_PU_Pos         (28U)
#define PWR_APCR_I3CPB6_PU_Msk         (0x1UL << PWR_APCR_I3CPB6_PU_Pos)      /*!< 0x10000000 */
#define PWR_APCR_I3CPB6_PU             PWR_APCR_I3CPB6_PU_Msk                 /*!< Port PB6 I3C pull-up bit configuration */

#define PWR_APCR_I3CPB7_PU_Pos         (29U)
#define PWR_APCR_I3CPB7_PU_Msk         (0x1UL << PWR_APCR_I3CPB7_PU_Pos)      /*!< 0x20000000 */
#define PWR_APCR_I3CPB7_PU             PWR_APCR_I3CPB7_PU_Msk                 /*!< Port PB7 I3C pull-up bit configuration */

#define PWR_APCR_I3CPB8_PU_Pos         (30U)
#define PWR_APCR_I3CPB8_PU_Msk         (0x1UL << PWR_APCR_I3CPB8_PU_Pos)      /*!< 0x40000000 */
#define PWR_APCR_I3CPB8_PU             PWR_APCR_I3CPB8_PU_Msk                 /*!< Port PB8 I3C pull-up bit configuration */

#define PWR_APCR_I3CPB9_PU_Pos         (31U)
#define PWR_APCR_I3CPB9_PU_Msk         (0x1UL << PWR_APCR_I3CPB9_PU_Pos)      /*!< 0x80000000 */
#define PWR_APCR_I3CPB9_PU             PWR_APCR_I3CPB9_PU_Msk                 /*!< Port PB9 I3C pull-up bit configuration */

/********************  Bit definition for PWR_PUCRN  register  ********************/
#define PWR_PUCRN_PUN1_Pos             (1U)
#define PWR_PUCRN_PUN1_Msk             (0x1UL << PWR_PUCRN_PUN1_Pos)           /*!< 0x00000002 */
#define PWR_PUCRN_PUN1                 PWR_PUCRN_PUN1_Msk                      /*!< PUN1: Port N pull-up */

#define PWR_PUCRN_PUN6_Pos             (6U)
#define PWR_PUCRN_PUN6_Msk             (0x1UL << PWR_PUCRN_PUN6_Pos)           /*!< 0x00000040 */
#define PWR_PUCRN_PUN6                 PWR_PUCRN_PUN6_Msk                      /*!< PUN6: Port N pull-up */

#define PWR_PUCRN_PUN12_Pos            (12U)
#define PWR_PUCRN_PUN12_Msk            (0x1UL << PWR_PUCRN_PUN12_Pos)          /*!< 0x00001000 */
#define PWR_PUCRN_PUN12                PWR_PUCRN_PUN12_Msk                     /*!< PUN12: Port N pull-up */

/********************  Bit definition for PWR_PDCRN  register  ********************/
#define PWR_PDCRN_PDN0_Pos             (0U)
#define PWR_PDCRN_PDN0_Msk             (0x1UL << PWR_PDCRN_PDN0_Pos)           /*!< 0x00000001 */
#define PWR_PDCRN_PDN0                 PWR_PDCRN_PDN0_Msk                      /*!< PDN0: Port N pull-down */

#define PWR_PDCRN_PDN1_Pos             (1U)
#define PWR_PDCRN_PDN1_Msk             (0x1UL << PWR_PDCRN_PDN1_Pos)           /*!< 0x00000002 */
#define PWR_PDCRN_PDN1                 PWR_PDCRN_PDN1_Msk                      /*!< PDN1: Port N pull-down */

#define PWR_PDCRN_PDN2N5_Pos           (2U)
#define PWR_PDCRN_PDN2N5_Msk           (0x1UL << PWR_PDCRN_PDN2N5_Pos)         /*!< 0x00000004 */
#define PWR_PDCRN_PDN2N5               PWR_PDCRN_PDN2N5_Msk                    /*!< PDN2 to PDN5: Port N pull-down */

#define PWR_PDCRN_PDN6_Pos             (6U)
#define PWR_PDCRN_PDN6_Msk             (0x1UL << PWR_PDCRN_PDN6_Pos)           /*!< 0x00000040 */
#define PWR_PDCRN_PDN6                 PWR_PDCRN_PDN6_Msk                      /*!< PDN6: Port N pull-down */

#define PWR_PDCRN_PDN8N11_Pos          (8U)
#define PWR_PDCRN_PDN8N11_Msk          (0x1UL << PWR_PDCRN_PDN8N11_Pos)        /*!< 0x00000100 */
#define PWR_PDCRN_PDN8N11              PWR_PDCRN_PDN8N11_Msk                   /*!< PDN8 to PDN11: Port N pull-down */

#define PWR_PDCRN_PDN12_Pos            (12U)
#define PWR_PDCRN_PDN12_Msk            (0x1UL << PWR_PDCRN_PDN12_Pos)          /*!< 0x00001000 */
#define PWR_PDCRN_PDN12                PWR_PDCRN_PDN12_Msk                     /*!< PDN12: Port N pull-down */

/********************  Bit definition for PWR_PUCRO  register  ********************/
#define PWR_PUCRO_PUO0_Pos             (0U)
#define PWR_PUCRO_PUO0_Msk             (0x1UL << PWR_PUCRO_PUO0_Pos)           /*!< 0x00000001 */
#define PWR_PUCRO_PUO0                 PWR_PUCRO_PUO0_Msk                      /*!< PUO0: Port O pull-up */

#define PWR_PUCRO_PUO1_Pos             (1U)
#define PWR_PUCRO_PUO1_Msk             (0x1UL << PWR_PUCRO_PUO1_Pos)           /*!< 0x00000002 */
#define PWR_PUCRO_PUO1                 PWR_PUCRO_PUO1_Msk                      /*!< PUO1: Port O pull-up */

#define PWR_PUCRO_PUO4_Pos             (4U)
#define PWR_PUCRO_PUO4_Msk             (0x1UL << PWR_PUCRO_PUO4_Pos)           /*!< 0x00000010 */
#define PWR_PUCRO_PUO4                 PWR_PUCRO_PUO4_Msk                      /*!< PUO4: Port O pull-up */

/********************  Bit definition for PWR_PDCRO  register  ********************/
#define PWR_PDCRO_PDO0_Pos             (0U)
#define PWR_PDCRO_PDO0_Msk             (0x1UL << PWR_PDCRO_PDO0_Pos)           /*!< 0x00000001 */
#define PWR_PDCRO_PDO0                 PWR_PDCRO_PDO0_Msk                      /*!< PDO0: Port O pull-down */

#define PWR_PDCRO_PDO1_Pos             (1U)
#define PWR_PDCRO_PDO1_Msk             (0x1UL << PWR_PDCRO_PDO1_Pos)           /*!< 0x00000002 */
#define PWR_PDCRO_PDO1                 PWR_PDCRO_PDO1_Msk                      /*!< PDO1: Port O pull-down */

#define PWR_PDCRO_PDO2_Pos             (2U)
#define PWR_PDCRO_PDO2_Msk             (0x1UL << PWR_PDCRO_PDO2_Pos)           /*!< 0x00000004 */
#define PWR_PDCRO_PDO2                 PWR_PDCRO_PDO2_Msk                      /*!< PDO2: Port O pull-down */

#define PWR_PDCRO_PDO3_Pos             (3U)
#define PWR_PDCRO_PDO3_Msk             (0x1UL << PWR_PDCRO_PDO3_Pos)           /*!< 0x00000008 */
#define PWR_PDCRO_PDO3                 PWR_PDCRO_PDO3_Msk                      /*!< PDO3: Port O pull-down */

#define PWR_PDCRO_PDO4_Pos             (4U)
#define PWR_PDCRO_PDO4_Msk             (0x1UL << PWR_PDCRO_PDO4_Pos)           /*!< 0x00000010 */
#define PWR_PDCRO_PDO4                 PWR_PDCRO_PDO4_Msk                      /*!< PDO4: Port O pull-down */

/********************  Bit definition for PWR_PDCRP  register  ********************/
#define PWR_PDCRP_PDP0P3_Pos           (0U)
#define PWR_PDCRP_PDP0P3_Msk           (0x1UL << PWR_PDCRP_PDP0P3_Pos)         /*!< 0x00000001 */
#define PWR_PDCRP_PDP0P3               PWR_PDCRP_PDP0P3_Msk                    /*!< PPO0 to PP03 : Port P pull-down */

#define PWR_PDCRP_PDP4P7_Pos           (4U)
#define PWR_PDCRP_PDP4P7_Msk           (0x1UL << PWR_PDCRP_PDP4P7_Pos)         /*!< 0x00000010 */
#define PWR_PDCRP_PDP4P7               PWR_PDCRP_PDP4P7_Msk                    /*!< PPO4 to PP07 : Port P pull-down */

#define PWR_PDCRP_PDP8P11_Pos          (8U)
#define PWR_PDCRP_PDP8P11_Msk          (0x1UL << PWR_PDCRP_PDP8P11_Pos)         /*!< 0x00000100 */
#define PWR_PDCRP_PDP8P11              PWR_PDCRP_PDP8P11_Msk                    /*!< PPO8 to PP11 : Port P pull-down */

#define PWR_PDCRP_PDP12P15_Pos         (12U)
#define PWR_PDCRP_PDP12P15_Msk         (0x1UL << PWR_PDCRP_PDP12P15_Pos)       /*!< 0x00001000 */
#define PWR_PDCRP_PDP12P15             PWR_PDCRP_PDP12P15_Msk                  /*!< PP12 to PP15 : Port P pull-down */


/******************************************************************************/
/*                                                                            */
/*                             RAM ECC monitoring                             */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for RAMECC_IER register  ******************/
#define RAMECC_IER_GIE_Pos             (0U)
#define RAMECC_IER_GIE_Msk             (0x1UL << RAMECC_IER_GIE_Pos)           /*!< 0x00000001 */
#define RAMECC_IER_GIE                 RAMECC_IER_GIE_Msk                      /*!< Global interrupt enable */
#define RAMECC_IER_GECCSEIE_Pos        (1U)
#define RAMECC_IER_GECCSEIE_Msk        (0x1UL << RAMECC_IER_GECCSEIE_Pos)      /*!< 0x00000002 */
#define RAMECC_IER_GECCSEIE            RAMECC_IER_GECCSEIE_Msk                 /*!< Global ECC single error interrupt enable */
#define RAMECC_IER_GECCDEIE_Pos        (2U)
#define RAMECC_IER_GECCDEIE_Msk        (0x1UL << RAMECC_IER_GECCDEIE_Pos)      /*!< 0x00000004 */
#define RAMECC_IER_GECCDEIE            RAMECC_IER_GECCDEIE_Msk                 /*!< Global ECC double error interrupt enable */
#define RAMECC_IER_GECCDEBWIE_Pos      (3U)
#define RAMECC_IER_GECCDEBWIE_Msk      (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)    /*!< 0x00000008 */
#define RAMECC_IER_GECCDEBWIE          RAMECC_IER_GECCDEBWIE_Msk               /*!< Global ECC double error on byte write (BW) interrupt enable */

/*******************  Bit definition for RAMECC_CR register  ******************/
#define RAMECC_CR_ECCSEIE_Pos          (2U)
#define RAMECC_CR_ECCSEIE_Msk          (0x1UL << RAMECC_CR_ECCSEIE_Pos)        /*!< 0x00000004 */
#define RAMECC_CR_ECCSEIE              RAMECC_CR_ECCSEIE_Msk                   /*!< ECC single error interrupt enable */
#define RAMECC_CR_ECCDEIE_Pos          (3U)
#define RAMECC_CR_ECCDEIE_Msk          (0x1UL << RAMECC_CR_ECCDEIE_Pos)        /*!< 0x00000008 */
#define RAMECC_CR_ECCDEIE              RAMECC_CR_ECCDEIE_Msk                   /*!< ECC double error interrupt enable */
#define RAMECC_CR_ECCDEBWIE_Pos        (4U)
#define RAMECC_CR_ECCDEBWIE_Msk        (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)      /*!< 0x00000010 */
#define RAMECC_CR_ECCDEBWIE            RAMECC_CR_ECCDEBWIE_Msk                 /*!< ECC double error on byte write (BW) interrupt enable */
#define RAMECC_CR_ECCELEN_Pos          (5U)
#define RAMECC_CR_ECCELEN_Msk          (0x1UL << RAMECC_CR_ECCELEN_Pos)        /*!< 0x00000020 */
#define RAMECC_CR_ECCELEN              RAMECC_CR_ECCELEN_Msk                   /*!< ECC error latching enable */

/*******************  Bit definition for RAMECC_SR register  ******************/
#define RAMECC_SR_SEDCF_Pos            (0U)
#define RAMECC_SR_SEDCF_Msk            (0x1UL << RAMECC_SR_SEDCF_Pos)           /*!< 0x00000001 */
#define RAMECC_SR_SEDCF                RAMECC_SR_SEDCF_Msk                      /*!< ECC single error detected and corrected flag */
#define RAMECC_SR_DEDF_Pos             (1U)
#define RAMECC_SR_DEDF_Msk             (0x1UL << RAMECC_SR_DEDF_Pos)            /*!< 0x00000002 */
#define RAMECC_SR_DEDF                 RAMECC_SR_DEDF_Msk                       /*!< ECC double error detected flag */
#define RAMECC_SR_DEBWDF_Pos           (2U)
#define RAMECC_SR_DEBWDF_Msk           (0x1UL << RAMECC_SR_DEBWDF_Pos)          /*!< 0x00000004 */
#define RAMECC_SR_DEBWDF               RAMECC_SR_DEBWDF_Msk                     /*!< ECC double error on byte write (BW) detected flag */

/******************  Bit definition for RAMECC_FAR register  ******************/
#define RAMECC_FAR_FADD_Pos            (0U)
#define RAMECC_FAR_FADD_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)    /*!< 0xFFFFFFFF */
#define RAMECC_FAR_FADD                RAMECC_FAR_FADD_Msk                      /*!< ECC error failing address */

/******************  Bit definition for RAMECC_FDRL register  *****************/
#define RAMECC_FDRL_FDATAL_Pos         (0U)
#define RAMECC_FDRL_FDATAL_Msk         (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */
#define RAMECC_FDRL_FDATAL             RAMECC_FDRL_FDATAL_Msk                   /*!< Failing data low */

/******************  Bit definition for RAMECC_FDRH register  *****************/
#define RAMECC_FDRH_FDATAH_Pos         (0U)
#define RAMECC_FDRH_FDATAH_Msk         (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */
#define RAMECC_FDRH_FDATAH             RAMECC_FDRH_FDATAH_Msk                   /* Failing data high (64-bit memory) */

/*****************  Bit definition for RAMECC_FECR register  ******************/
#define RAMECC_FECR_FEC_Pos            (0U)
#define RAMECC_FECR_FEC_Msk            (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)   /*!< 0xFFFFFFFF */
#define RAMECC_FECR_FEC                RAMECC_FECR_FEC_Msk                     /*!< Failing error code */


/******************************************************************************/
/*                                                                            */
/*                         Reset and Clock Control                            */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for RCC_CR register  ********************/
#define RCC_CR_HSION_Pos               (0U)
#define RCC_CR_HSION_Msk               (0x1UL << RCC_CR_HSION_Pos)             /*!< 0x00000001 */
#define RCC_CR_HSION                   RCC_CR_HSION_Msk                        /*!< Internal High Speed clock enable */
#define RCC_CR_HSIKERON_Pos            (1U)
#define RCC_CR_HSIKERON_Msk            (0x1UL << RCC_CR_HSIKERON_Pos)          /*!< 0x00000002 */
#define RCC_CR_HSIKERON                RCC_CR_HSIKERON_Msk                     /*!< Internal High Speed clock enable in Stop mode */
#define RCC_CR_HSIRDY_Pos              (2U)
#define RCC_CR_HSIRDY_Msk              (0x1UL << RCC_CR_HSIRDY_Pos)            /*!< 0x00000004 */
#define RCC_CR_HSIRDY                  RCC_CR_HSIRDY_Msk                       /*!< Internal High Speed clock ready flag */
#define RCC_CR_HSIDIV_Pos              (3U)
#define RCC_CR_HSIDIV_Msk              (0x3UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000018 */
#define RCC_CR_HSIDIV                  RCC_CR_HSIDIV_Msk                       /*!< Internal High Speed clock divider selection */
#define RCC_CR_HSIDIV_0                (0x1UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000008 */
#define RCC_CR_HSIDIV_1                (0x2UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000010 */

#define RCC_CR_HSIDIVF_Pos             (5U)
#define RCC_CR_HSIDIVF_Msk             (0x1UL << RCC_CR_HSIDIVF_Pos)           /*!< 0x00000020 */
#define RCC_CR_HSIDIVF                 RCC_CR_HSIDIVF_Msk                      /*!< HSI Divider flag */
#define RCC_CR_CSION_Pos               (7U)
#define RCC_CR_CSION_Msk               (0x1UL << RCC_CR_CSION_Pos)             /*!< 0x00000080 */
#define RCC_CR_CSION                   RCC_CR_CSION_Msk                        /*!< The Internal RC 4MHz oscillator clock enable */
#define RCC_CR_CSIRDY_Pos              (8U)
#define RCC_CR_CSIRDY_Msk              (0x1UL << RCC_CR_CSIRDY_Pos)            /*!< 0x00000100 */
#define RCC_CR_CSIRDY                  RCC_CR_CSIRDY_Msk                       /*!< The Internal RC 4MHz oscillator clock ready */
#define RCC_CR_CSIKERON_Pos            (9U)
#define RCC_CR_CSIKERON_Msk            (0x1UL << RCC_CR_CSIKERON_Pos)          /*!< 0x00000200 */
#define RCC_CR_CSIKERON                RCC_CR_CSIKERON_Msk                     /*!< Internal RC 4MHz oscillator clock enable in Stop mode */
#define RCC_CR_HSI48ON_Pos             (12U)
#define RCC_CR_HSI48ON_Msk             (0x1UL << RCC_CR_HSI48ON_Pos)           /*!< 0x00001000 */
#define RCC_CR_HSI48ON                 RCC_CR_HSI48ON_Msk                      /*!< HSI48 clock enable clock enable  */
#define RCC_CR_HSI48RDY_Pos            (13U)
#define RCC_CR_HSI48RDY_Msk            (0x1UL << RCC_CR_HSI48RDY_Pos)          /*!< 0x00002000 */
#define RCC_CR_HSI48RDY                RCC_CR_HSI48RDY_Msk                     /*!< HSI48 clock ready flag */
#define RCC_CR_HSEON_Pos               (16U)
#define RCC_CR_HSEON_Msk               (0x1UL << RCC_CR_HSEON_Pos)             /*!< 0x00010000 */
#define RCC_CR_HSEON                   RCC_CR_HSEON_Msk                        /*!< External High Speed clock enable */
#define RCC_CR_HSERDY_Pos              (17U)
#define RCC_CR_HSERDY_Msk              (0x1UL << RCC_CR_HSERDY_Pos)            /*!< 0x00020000 */
#define RCC_CR_HSERDY                  RCC_CR_HSERDY_Msk                       /*!< External High Speed clock ready flag */
#define RCC_CR_HSEBYP_Pos              (18U)
#define RCC_CR_HSEBYP_Msk              (0x1UL << RCC_CR_HSEBYP_Pos)            /*!< 0x00040000 */
#define RCC_CR_HSEBYP                  RCC_CR_HSEBYP_Msk                       /*!< External High Speed clock bypass */
#define RCC_CR_HSEEXT_Pos              (19U)
#define RCC_CR_HSEEXT_Msk              (0x1UL << RCC_CR_HSEEXT_Pos)            /*!< 0x00100000 */
#define RCC_CR_HSEEXT                  RCC_CR_HSEEXT_Msk                       /*!< External High Speed clock type in bypass mode */
#define RCC_CR_HSECSSON_Pos            (20U)
#define RCC_CR_HSECSSON_Msk            (0x1UL << RCC_CR_HSECSSON_Pos)          /*!< 0x00080000 */
#define RCC_CR_HSECSSON                RCC_CR_HSECSSON_Msk                     /*!< HSE Clock security System enable */
#define RCC_CR_PLL1ON_Pos              (24U)
#define RCC_CR_PLL1ON_Msk              (0x1UL << RCC_CR_PLL1ON_Pos)            /*!< 0x01000000 */
#define RCC_CR_PLL1ON                  RCC_CR_PLL1ON_Msk                       /*!< System PLL1 clock enable */
#define RCC_CR_PLL1RDY_Pos             (25U)
#define RCC_CR_PLL1RDY_Msk             (0x1UL << RCC_CR_PLL1RDY_Pos)           /*!< 0x02000000 */
#define RCC_CR_PLL1RDY                 RCC_CR_PLL1RDY_Msk                      /*!< System PLL1 clock ready flag */
#define RCC_CR_PLL2ON_Pos              (26U)
#define RCC_CR_PLL2ON_Msk              (0x1UL << RCC_CR_PLL2ON_Pos)            /*!< 0x04000000 */
#define RCC_CR_PLL2ON                  RCC_CR_PLL2ON_Msk                       /*!< System PLL2 clock enable */
#define RCC_CR_PLL2RDY_Pos             (27U)
#define RCC_CR_PLL2RDY_Msk             (0x1UL << RCC_CR_PLL2RDY_Pos)           /*!< 0x08000000 */
#define RCC_CR_PLL2RDY                 RCC_CR_PLL2RDY_Msk                      /*!< System PLL2 clock ready flag */
#define RCC_CR_PLL3ON_Pos              (28U)
#define RCC_CR_PLL3ON_Msk              (0x1UL << RCC_CR_PLL3ON_Pos)            /*!< 0x10000000 */
#define RCC_CR_PLL3ON                  RCC_CR_PLL3ON_Msk                       /*!< System PLL3 clock enable */
#define RCC_CR_PLL3RDY_Pos             (29U)
#define RCC_CR_PLL3RDY_Msk             (0x1UL << RCC_CR_PLL3RDY_Pos)           /*!< 0x20000000 */
#define RCC_CR_PLL3RDY                 RCC_CR_PLL3RDY_Msk                      /*!< System PLL3 clock ready flag */

/********************  Bit definition for RCC_HSICFGR register  ***************/
/*!< HSICAL configuration */
#define RCC_HSICFGR_HSICAL_Pos         (0U)
#define RCC_HSICFGR_HSICAL_Msk         (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000FFF */
#define RCC_HSICFGR_HSICAL             RCC_HSICFGR_HSICAL_Msk                  /*!< HSICAL[11:0] bits */
#define RCC_HSICFGR_HSICAL_0           (0x001UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000001 */
#define RCC_HSICFGR_HSICAL_1           (0x002UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000002 */
#define RCC_HSICFGR_HSICAL_2           (0x004UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000004 */
#define RCC_HSICFGR_HSICAL_3           (0x008UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000008 */
#define RCC_HSICFGR_HSICAL_4           (0x010UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000010 */
#define RCC_HSICFGR_HSICAL_5           (0x020UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000020 */
#define RCC_HSICFGR_HSICAL_6           (0x040UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000040 */
#define RCC_HSICFGR_HSICAL_7           (0x080UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000080 */
#define RCC_HSICFGR_HSICAL_8           (0x100UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000100 */
#define RCC_HSICFGR_HSICAL_9           (0x200UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000200 */
#define RCC_HSICFGR_HSICAL_10          (0x400UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000400 */
#define RCC_HSICFGR_HSICAL_11          (0x800UL << RCC_HSICFGR_HSICAL_Pos)     /*!< 0x00000800 */

/*!< HSITRIM configuration */
#define RCC_HSICFGR_HSITRIM_Pos        (24U)
#define RCC_HSICFGR_HSITRIM_Msk        (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x7F000000 */
#define RCC_HSICFGR_HSITRIM            RCC_HSICFGR_HSITRIM_Msk                 /*!< HSITRIM[6:0] bits */
#define RCC_HSICFGR_HSITRIM_0          (0x01UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x01000000 */
#define RCC_HSICFGR_HSITRIM_1          (0x02UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x02000000 */
#define RCC_HSICFGR_HSITRIM_2          (0x04UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x04000000 */
#define RCC_HSICFGR_HSITRIM_3          (0x08UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x08000000 */
#define RCC_HSICFGR_HSITRIM_4          (0x10UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x10000000 */
#define RCC_HSICFGR_HSITRIM_5          (0x20UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x20000000 */
#define RCC_HSICFGR_HSITRIM_6          (0x40UL << RCC_HSICFGR_HSITRIM_Pos)     /*!< 0x40000000 */

/********************  Bit definition for RCC_CRRCR register  *****************/
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos         (0U)
#define RCC_CRRCR_HSI48CAL_Msk         (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x000003FF */
#define RCC_CRRCR_HSI48CAL             RCC_CRRCR_HSI48CAL_Msk                  /*!< HSI48CAL[9:0] bits */
#define RCC_CRRCR_HSI48CAL_0           (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000001 */
#define RCC_CRRCR_HSI48CAL_1           (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000002 */
#define RCC_CRRCR_HSI48CAL_2           (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000004 */
#define RCC_CRRCR_HSI48CAL_3           (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000008 */
#define RCC_CRRCR_HSI48CAL_4           (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000010 */
#define RCC_CRRCR_HSI48CAL_5           (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000020 */
#define RCC_CRRCR_HSI48CAL_6           (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000040 */
#define RCC_CRRCR_HSI48CAL_7           (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_8           (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_9           (0x200UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000200 */

/********************  Bit definition for RCC_CSICFGR register  ***************/
/*!< CSICAL configuration */
#define RCC_CSICFGR_CSICAL_Pos         (0U)
#define RCC_CSICFGR_CSICAL_Msk         (0xFFUL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x000000FF */
#define RCC_CSICFGR_CSICAL             RCC_CSICFGR_CSICAL_Msk                  /*!< CSICAL[7:0] bits */
#define RCC_CSICFGR_CSICAL_0           (0x01UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000001 */
#define RCC_CSICFGR_CSICAL_1           (0x02UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000002 */
#define RCC_CSICFGR_CSICAL_2           (0x04UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000004 */
#define RCC_CSICFGR_CSICAL_3           (0x08UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000008 */
#define RCC_CSICFGR_CSICAL_4           (0x10UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000010 */
#define RCC_CSICFGR_CSICAL_5           (0x20UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000020 */
#define RCC_CSICFGR_CSICAL_6           (0x40UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000040 */
#define RCC_CSICFGR_CSICAL_7           (0x80UL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x00000080 */

/*!< CSITRIM configuration */
#define RCC_CSICFGR_CSITRIM_Pos        (24U)
#define RCC_CSICFGR_CSITRIM_Msk        (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x3F000000 */
#define RCC_CSICFGR_CSITRIM            RCC_CSICFGR_CSITRIM_Msk                 /*!< CSITRIM[5:0] bits */
#define RCC_CSICFGR_CSITRIM_0          (0x01UL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x01000000 */
#define RCC_CSICFGR_CSITRIM_1          (0x02UL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x02000000 */
#define RCC_CSICFGR_CSITRIM_2          (0x04UL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x04000000 */
#define RCC_CSICFGR_CSITRIM_3          (0x08UL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x08000000 */
#define RCC_CSICFGR_CSITRIM_4          (0x10UL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x10000000 */
#define RCC_CSICFGR_CSITRIM_5          (0x20UL << RCC_CSICFGR_CSITRIM_Pos)     /*!< 0x20000000 */

/********************  Bit definition for RCC_CFGR register  ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos                (0U)
#define RCC_CFGR_SW_Msk                (0x7UL << RCC_CFGR_SW_Pos)              /*!< 0x00000007 */
#define RCC_CFGR_SW                    RCC_CFGR_SW_Msk                         /*!< SW[2:0] bits (System clock switch) */
#define RCC_CFGR_SW_0                  (0x1UL << RCC_CFGR_SW_Pos)              /*!< 0x00000001 */
#define RCC_CFGR_SW_1                  (0x2UL << RCC_CFGR_SW_Pos)              /*!< 0x00000002 */
#define RCC_CFGR_SW_2                  (0x4UL << RCC_CFGR_SW_Pos)              /*!< 0x00000004 */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos               (3U)
#define RCC_CFGR_SWS_Msk               (0x7UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000038 */
#define RCC_CFGR_SWS                   RCC_CFGR_SWS_Msk                        /*!< SWS[2:0] bits (System clock switch status) */
#define RCC_CFGR_SWS_0                 (0x1UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000008 */
#define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
#define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */

#define RCC_CFGR_STOPWUCK_Pos          (6U)
#define RCC_CFGR_STOPWUCK_Msk          (0x1UL << RCC_CFGR_STOPWUCK_Pos)        /*!< 0x00000040 */
#define RCC_CFGR_STOPWUCK              RCC_CFGR_STOPWUCK_Msk                   /*!< Wake Up from stop and CSS backup clock selection */
#define RCC_CFGR_STOPKERWUCK_Pos       (7U)
#define RCC_CFGR_STOPKERWUCK_Msk       (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)     /*!< 0x00000080 */
#define RCC_CFGR_STOPKERWUCK           RCC_CFGR_STOPKERWUCK_Msk                /*!< Kernel Clock Selection after a Wake Up from Stop */

/*!< RTCPRE configuration */
#define RCC_CFGR_RTCPRE_Pos            (8U)
#define RCC_CFGR_RTCPRE_Msk            (0x3FUL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00003F00 */
#define RCC_CFGR_RTCPRE                RCC_CFGR_RTCPRE_Msk                     /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */
#define RCC_CFGR_RTCPRE_0              (0x01UL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00000100 */
#define RCC_CFGR_RTCPRE_1              (0x02UL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00000200 */
#define RCC_CFGR_RTCPRE_2              (0x04UL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00000400 */
#define RCC_CFGR_RTCPRE_3              (0x08UL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00000800 */
#define RCC_CFGR_RTCPRE_4              (0x10UL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00001000 */
#define RCC_CFGR_RTCPRE_5              (0x20UL << RCC_CFGR_RTCPRE_Pos)         /*!< 0x00002000 */

#define RCC_CFGR_TIMPRE_Pos            (15U)
#define RCC_CFGR_TIMPRE_Msk            (0x1UL << RCC_CFGR_TIMPRE_Pos)          /*!< 0x00008000 */
#define RCC_CFGR_TIMPRE                RCC_CFGR_TIMPRE_Msk                     /*!< TIMPRE configuration */

#define RCC_CFGR_MCO1PRE_Pos           (18U)
#define RCC_CFGR_MCO1PRE_Msk           (0xFUL << RCC_CFGR_MCO1PRE_Pos)         /*!< 0x003C0000 */
#define RCC_CFGR_MCO1PRE               RCC_CFGR_MCO1PRE_Msk                    /*!< MCO1 configuration */
#define RCC_CFGR_MCO1PRE_0             (0x1UL << RCC_CFGR_MCO1PRE_Pos)         /*!< 0x00040000 */
#define RCC_CFGR_MCO1PRE_1             (0x2UL << RCC_CFGR_MCO1PRE_Pos)         /*!< 0x00080000 */
#define RCC_CFGR_MCO1PRE_2             (0x4UL << RCC_CFGR_MCO1PRE_Pos)         /*!< 0x00100000 */
#define RCC_CFGR_MCO1PRE_3             (0x8UL << RCC_CFGR_MCO1PRE_Pos)         /*!< 0x00200000 */

#define RCC_CFGR_MCO1SEL_Pos           (22U)
#define RCC_CFGR_MCO1SEL_Msk           (0x7UL << RCC_CFGR_MCO1SEL_Pos)         /*!< 0x01C00000 */
#define RCC_CFGR_MCO1SEL               RCC_CFGR_MCO1SEL_Msk                    /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */
#define RCC_CFGR_MCO1SEL_0             (0x1UL <<  RCC_CFGR_MCO1SEL_Pos)        /*!< 0x00400000 */
#define RCC_CFGR_MCO1SEL_1             (0x2UL <<  RCC_CFGR_MCO1SEL_Pos)        /*!< 0x00800000 */
#define RCC_CFGR_MCO1SEL_2             (0x4UL <<  RCC_CFGR_MCO1SEL_Pos)        /*!< 0x01000000 */

#define RCC_CFGR_MCO2PRE_Pos           (25U)
#define RCC_CFGR_MCO2PRE_Msk           (0xFUL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x1E000000 */
#define RCC_CFGR_MCO2PRE               RCC_CFGR_MCO2PRE_Msk                    /*!< MCO2 configuration */
#define RCC_CFGR_MCO2PRE_0             (0x1UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x02000000 */
#define RCC_CFGR_MCO2PRE_1             (0x2UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x04000000 */
#define RCC_CFGR_MCO2PRE_2             (0x4UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x08000000 */
#define RCC_CFGR_MCO2PRE_3             (0x8UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x10000000 */

#define RCC_CFGR_MCO2SEL_Pos           (29U)
#define RCC_CFGR_MCO2SEL_Msk           (0x7UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0xE0000000 */
#define RCC_CFGR_MCO2SEL               RCC_CFGR_MCO2SEL_Msk                    /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */
#define RCC_CFGR_MCO2SEL_0             (0x1UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x20000000 */
#define RCC_CFGR_MCO2SEL_1             (0x2UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x40000000 */
#define RCC_CFGR_MCO2SEL_2             (0x4UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x80000000 */

/********************  Bit definition for RCC_CDCFGR register  ****************/
/*!< CPRE configuration */
#define RCC_CDCFGR_CPRE_Pos            (0U)
#define RCC_CDCFGR_CPRE_Msk            (0xFUL << RCC_CDCFGR_CPRE_Pos)          /*!< 0x0000000F */
#define RCC_CDCFGR_CPRE                RCC_CDCFGR_CPRE_Msk                     /*!< CPRE[3:0] bits */
#define RCC_CDCFGR_CPRE_0              (0x1UL << RCC_CDCFGR_CPRE_Pos)          /*!< 0x00000001 */
#define RCC_CDCFGR_CPRE_1              (0x2UL << RCC_CDCFGR_CPRE_Pos)          /*!< 0x00000002 */
#define RCC_CDCFGR_CPRE_2              (0x4UL << RCC_CDCFGR_CPRE_Pos)          /*!< 0x00000004 */
#define RCC_CDCFGR_CPRE_3              (0x8UL << RCC_CDCFGR_CPRE_Pos)          /*!< 0x00000008 */

/********************  Bit definition for RCC_BMCFGR register  ****************/
/*!< BMPRE configuration */
#define RCC_BMCFGR_BMPRE_Pos           (0U)
#define RCC_BMCFGR_BMPRE_Msk           (0xFUL << RCC_BMCFGR_BMPRE_Pos)         /*!< 0x0000000F */
#define RCC_BMCFGR_BMPRE               RCC_BMCFGR_BMPRE_Msk                    /*!< BMPRE[3:0] bits */
#define RCC_BMCFGR_BMPRE_0             (0x1UL << RCC_BMCFGR_BMPRE_Pos)         /*!< 0x00000001 */
#define RCC_BMCFGR_BMPRE_1             (0x2UL << RCC_BMCFGR_BMPRE_Pos)         /*!< 0x00000002 */
#define RCC_BMCFGR_BMPRE_2             (0x4UL << RCC_BMCFGR_BMPRE_Pos)         /*!< 0x00000004 */
#define RCC_BMCFGR_BMPRE_3             (0x8UL << RCC_BMCFGR_BMPRE_Pos)         /*!< 0x00000008 */

/********************  Bit definition for RCC_APBCFGR register  ***************/
/*!< APB1 prescaler configuration */
#define RCC_APBCFGR_PPRE1_Pos          (0U)
#define RCC_APBCFGR_PPRE1_Msk          (0x7UL << RCC_APBCFGR_PPRE1_Pos)        /*!< 0x00000007 */
#define RCC_APBCFGR_PPRE1              RCC_APBCFGR_PPRE1_Msk                   /*!< PPRE1[2:0] bits */
#define RCC_APBCFGR_PPRE1_0            (0x1UL << RCC_APBCFGR_PPRE1_Pos)        /*!< 0x00000001 */
#define RCC_APBCFGR_PPRE1_1            (0x2UL << RCC_APBCFGR_PPRE1_Pos)        /*!< 0x00000002 */
#define RCC_APBCFGR_PPRE1_2            (0x4UL << RCC_APBCFGR_PPRE1_Pos)        /*!< 0x00000004 */

/*!< APB2 prescaler configuration */
#define RCC_APBCFGR_PPRE2_Pos          (4U)
#define RCC_APBCFGR_PPRE2_Msk          (0x7UL << RCC_APBCFGR_PPRE2_Pos)        /*!< 0x00000070 */
#define RCC_APBCFGR_PPRE2              RCC_APBCFGR_PPRE2_Msk                   /*!< PPRE2[2:0] bits */
#define RCC_APBCFGR_PPRE2_0            (0x1UL << RCC_APBCFGR_PPRE2_Pos)        /*!< 0x00000010 */
#define RCC_APBCFGR_PPRE2_1            (0x2UL << RCC_APBCFGR_PPRE2_Pos)        /*!< 0x00000020 */
#define RCC_APBCFGR_PPRE2_2            (0x4UL << RCC_APBCFGR_PPRE2_Pos)        /*!< 0x00000040 */

/*!< APB4 prescaler configuration */
#define RCC_APBCFGR_PPRE4_Pos          (8U)
#define RCC_APBCFGR_PPRE4_Msk          (0x7UL << RCC_APBCFGR_PPRE4_Pos)        /*!< 0x00000700 */
#define RCC_APBCFGR_PPRE4              RCC_APBCFGR_PPRE4_Msk                   /*!< PPRE4[2:0] bits */
#define RCC_APBCFGR_PPRE4_0            (0x1UL << RCC_APBCFGR_PPRE4_Pos)        /*!< 0x00000100 */
#define RCC_APBCFGR_PPRE4_1            (0x2UL << RCC_APBCFGR_PPRE4_Pos)        /*!< 0x00000200 */
#define RCC_APBCFGR_PPRE4_2            (0x4UL << RCC_APBCFGR_PPRE4_Pos)        /*!< 0x00000400 */

/*!< APB5 prescaler configuration */
#define RCC_APBCFGR_PPRE5_Pos          (12U)
#define RCC_APBCFGR_PPRE5_Msk          (0x7UL << RCC_APBCFGR_PPRE5_Pos)        /*!< 0x00007000 */
#define RCC_APBCFGR_PPRE5              RCC_APBCFGR_PPRE5_Msk                   /*!< PPRE5[2:0] bits */
#define RCC_APBCFGR_PPRE5_0            (0x1UL << RCC_APBCFGR_PPRE5_Pos)        /*!< 0x00001000 */
#define RCC_APBCFGR_PPRE5_1            (0x2UL << RCC_APBCFGR_PPRE5_Pos)        /*!< 0x00002000 */
#define RCC_APBCFGR_PPRE5_2            (0x4UL << RCC_APBCFGR_PPRE5_Pos)        /*!< 0x00004000 */

/********************  Bit definition for RCC_PLLCKSELR register  *************/
#define RCC_PLLCKSELR_PLLSRC_Pos       (0U)
#define RCC_PLLCKSELR_PLLSRC_Msk       (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)     /*!< 0x00000003 */
#define RCC_PLLCKSELR_PLLSRC           RCC_PLLCKSELR_PLLSRC_Msk                /*!< DIVMx and PLLs clock source selection */
#define RCC_PLLCKSELR_PLLSRC_0         (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos)    /*!< 0x00000010 */
#define RCC_PLLCKSELR_PLLSRC_1         (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos)    /*!< 0x00000020 */

#define RCC_PLLCKSELR_DIVM1_Pos        (4U)
#define RCC_PLLCKSELR_DIVM1_Msk        (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x000003F0 */
#define RCC_PLLCKSELR_DIVM1            RCC_PLLCKSELR_DIVM1_Msk                 /*!< DIVM1[5:0] bits */
#define RCC_PLLCKSELR_DIVM1_0          (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x00000010 */
#define RCC_PLLCKSELR_DIVM1_1          (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x00000020 */
#define RCC_PLLCKSELR_DIVM1_2          (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x00000040 */
#define RCC_PLLCKSELR_DIVM1_3          (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x00000080 */
#define RCC_PLLCKSELR_DIVM1_4          (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x00000100 */
#define RCC_PLLCKSELR_DIVM1_5          (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)     /*!< 0x00000200 */

#define RCC_PLLCKSELR_DIVM2_Pos        (12U)
#define RCC_PLLCKSELR_DIVM2_Msk        (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x0003F000 */
#define RCC_PLLCKSELR_DIVM2            RCC_PLLCKSELR_DIVM2_Msk                 /*!< DIVM2[5:0] bits */
#define RCC_PLLCKSELR_DIVM2_0          (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x00001000 */
#define RCC_PLLCKSELR_DIVM2_1          (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x00002000 */
#define RCC_PLLCKSELR_DIVM2_2          (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x00004000 */
#define RCC_PLLCKSELR_DIVM2_3          (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x00008000 */
#define RCC_PLLCKSELR_DIVM2_4          (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x00010000 */
#define RCC_PLLCKSELR_DIVM2_5          (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)     /*!< 0x00020000 */

#define RCC_PLLCKSELR_DIVM3_Pos        (20U)
#define RCC_PLLCKSELR_DIVM3_Msk        (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x03F00000 */
#define RCC_PLLCKSELR_DIVM3            RCC_PLLCKSELR_DIVM3_Msk                 /*!< DIVM3[5:0] bits */
#define RCC_PLLCKSELR_DIVM3_0          (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x00100000 */
#define RCC_PLLCKSELR_DIVM3_1          (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x00200000 */
#define RCC_PLLCKSELR_DIVM3_2          (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x00400000 */
#define RCC_PLLCKSELR_DIVM3_3          (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x00800000 */
#define RCC_PLLCKSELR_DIVM3_4          (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x01000000 */
#define RCC_PLLCKSELR_DIVM3_5          (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)     /*!< 0x02000000 */

/********************  Bit definition for RCC_PLLCFGR register  ***************/
#define RCC_PLLCFGR_PLL1FRACEN_Pos     (0U)
#define RCC_PLLCFGR_PLL1FRACEN_Msk     (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)   /*!< 0x00000001 */
#define RCC_PLLCFGR_PLL1FRACEN         RCC_PLLCFGR_PLL1FRACEN_Msk              /*!< PLL1 fractional latch enable */
#define RCC_PLLCFGR_PLL1VCOSEL_Pos     (1U)
#define RCC_PLLCFGR_PLL1VCOSEL_Msk     (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)   /*!< 0x00000002 */
#define RCC_PLLCFGR_PLL1VCOSEL         RCC_PLLCFGR_PLL1VCOSEL_Msk              /*!< PLL1 VCO selection */
#define RCC_PLLCFGR_PLL1SSCGEN_Pos     (2U)
#define RCC_PLLCFGR_PLL1SSCGEN_Msk     (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos)   /*!< 0x00000004 */
#define RCC_PLLCFGR_PLL1SSCGEN         RCC_PLLCFGR_PLL1SSCGEN_Msk              /*!< PLL1 Spread Spectrum Clock Generator enable */
#define RCC_PLLCFGR_PLL1RGE_Pos        (3U)
#define RCC_PLLCFGR_PLL1RGE_Msk        (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)      /*!< 0x00000018 */
#define RCC_PLLCFGR_PLL1RGE            RCC_PLLCFGR_PLL1RGE_Msk                 /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */
#define RCC_PLLCFGR_PLL1RGE_0          (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)      /*!< 0x00000008 */
#define RCC_PLLCFGR_PLL1RGE_1          (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)      /*!< 0x00000010 */

#define RCC_PLLCFGR_PLL1PEN_Pos        (5U)
#define RCC_PLLCFGR_PLL1PEN_Msk        (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos)      /*!< 0x00000020 */
#define RCC_PLLCFGR_PLL1PEN            RCC_PLLCFGR_PLL1PEN_Msk                 /*!< PLL1 DIVP divider output enable */
#define RCC_PLLCFGR_PLL1QEN_Pos        (6U)
#define RCC_PLLCFGR_PLL1QEN_Msk        (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos)      /*!< 0x00000040 */
#define RCC_PLLCFGR_PLL1QEN            RCC_PLLCFGR_PLL1QEN_Msk                 /*!< PLL1 DIVQ divider output enable */
#define RCC_PLLCFGR_PLL1REN_Pos        (7U)
#define RCC_PLLCFGR_PLL1REN_Msk        (0x1UL << RCC_PLLCFGR_PLL1REN_Pos)      /*!< 0x00000080 */
#define RCC_PLLCFGR_PLL1REN            RCC_PLLCFGR_PLL1REN_Msk                 /*!< PLL1 DIVR divider output enable */
#define RCC_PLLCFGR_PLL1SEN_Pos        (8U)
#define RCC_PLLCFGR_PLL1SEN_Msk        (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos)      /*!< 0x00000100 */
#define RCC_PLLCFGR_PLL1SEN            RCC_PLLCFGR_PLL1SEN_Msk                 /*!< PLL1 DIVS divider output enable */

#define RCC_PLLCFGR_PLL2FRACEN_Pos     (11U)
#define RCC_PLLCFGR_PLL2FRACEN_Msk     (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)   /*!< 0x00000800 */
#define RCC_PLLCFGR_PLL2FRACEN         RCC_PLLCFGR_PLL2FRACEN_Msk              /*!< PLL2 fractional latch enable */
#define RCC_PLLCFGR_PLL2VCOSEL_Pos     (12U)
#define RCC_PLLCFGR_PLL2VCOSEL_Msk     (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)   /*!< 0x00001000 */
#define RCC_PLLCFGR_PLL2VCOSEL         RCC_PLLCFGR_PLL2VCOSEL_Msk              /*!< PLL2 VCO selection */
#define RCC_PLLCFGR_PLL2SSCGEN_Pos     (13U)
#define RCC_PLLCFGR_PLL2SSCGEN_Msk     (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos)   /*!< 0x00002000 */
#define RCC_PLLCFGR_PLL2SSCGEN         RCC_PLLCFGR_PLL2SSCGEN_Msk              /*!< PLL2 Spread Spectrum Clock Generator enable */
#define RCC_PLLCFGR_PLL2RGE_Pos        (14U)
#define RCC_PLLCFGR_PLL2RGE_Msk        (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)      /*!< 0x0000C000 */
#define RCC_PLLCFGR_PLL2RGE            RCC_PLLCFGR_PLL2RGE_Msk                 /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */
#define RCC_PLLCFGR_PLL2RGE_0          (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)      /*!< 0x00004000 */
#define RCC_PLLCFGR_PLL2RGE_1          (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)      /*!< 0x00008000 */

#define RCC_PLLCFGR_PLL2PEN_Pos        (16U)
#define RCC_PLLCFGR_PLL2PEN_Msk        (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos)      /*!< 0x00010000 */
#define RCC_PLLCFGR_PLL2PEN            RCC_PLLCFGR_PLL2PEN_Msk                 /*!< PLL2 DIVP divider output enable */
#define RCC_PLLCFGR_PLL2QEN_Pos        (17U)
#define RCC_PLLCFGR_PLL2QEN_Msk        (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos)      /*!< 0x00020000 */
#define RCC_PLLCFGR_PLL2QEN            RCC_PLLCFGR_PLL2QEN_Msk                 /*!< PLL2 DIVQ divider output enable */
#define RCC_PLLCFGR_PLL2REN_Pos        (18U)
#define RCC_PLLCFGR_PLL2REN_Msk        (0x1UL << RCC_PLLCFGR_PLL2REN_Pos)      /*!< 0x00040000 */
#define RCC_PLLCFGR_PLL2REN            RCC_PLLCFGR_PLL2REN_Msk                 /*!< PLL2 DIVR divider output enable */
#define RCC_PLLCFGR_PLL2SEN_Pos        (19U)
#define RCC_PLLCFGR_PLL2SEN_Msk        (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos)      /*!< 0x00080000 */
#define RCC_PLLCFGR_PLL2SEN            RCC_PLLCFGR_PLL2SEN_Msk                 /*!< PLL2 DIVS divider output enable */
#define RCC_PLLCFGR_PLL2TEN_Pos        (20U)
#define RCC_PLLCFGR_PLL2TEN_Msk        (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos)      /*!< 0x00100000 */
#define RCC_PLLCFGR_PLL2TEN            RCC_PLLCFGR_PLL2TEN_Msk                 /*!< PLL2 DIVT divider output enable */

#define RCC_PLLCFGR_PLL3FRACEN_Pos     (22U)
#define RCC_PLLCFGR_PLL3FRACEN_Msk     (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)   /*!< 0x00400000 */
#define RCC_PLLCFGR_PLL3FRACEN         RCC_PLLCFGR_PLL3FRACEN_Msk              /*!< PLL3 fractional latch enable */
#define RCC_PLLCFGR_PLL3VCOSEL_Pos     (23U)
#define RCC_PLLCFGR_PLL3VCOSEL_Msk     (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)   /*!< 0x00800000 */
#define RCC_PLLCFGR_PLL3VCOSEL         RCC_PLLCFGR_PLL3VCOSEL_Msk              /*!< PLL3 VCO selection */
#define RCC_PLLCFGR_PLL3SSCGEN_Pos     (24U)
#define RCC_PLLCFGR_PLL3SSCGEN_Msk     (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos)   /*!< 0x01000000 */
#define RCC_PLLCFGR_PLL3SSCGEN         RCC_PLLCFGR_PLL3SSCGEN_Msk              /*!< PLL3 Spread Spectrum Clock Generator enable */
#define RCC_PLLCFGR_PLL3RGE_Pos        (25U)
#define RCC_PLLCFGR_PLL3RGE_Msk        (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)      /*!< 0x06000000 */
#define RCC_PLLCFGR_PLL3RGE            RCC_PLLCFGR_PLL3RGE_Msk                 /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */
#define RCC_PLLCFGR_PLL3RGE_0          (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)      /*!< 0x02000000 */
#define RCC_PLLCFGR_PLL3RGE_1          (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)      /*!< 0x04000000 */

#define RCC_PLLCFGR_PLL3PEN_Pos        (27U)
#define RCC_PLLCFGR_PLL3PEN_Msk        (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos)      /*!< 0x08000000 */
#define RCC_PLLCFGR_PLL3PEN            RCC_PLLCFGR_PLL3PEN_Msk                 /*!< PLL3 DIVP divider output enable */
#define RCC_PLLCFGR_PLL3QEN_Pos        (28U)
#define RCC_PLLCFGR_PLL3QEN_Msk        (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos)      /*!< 0x10000000 */
#define RCC_PLLCFGR_PLL3QEN            RCC_PLLCFGR_PLL3QEN_Msk                 /*!< PLL3 DIVQ divider output enable */
#define RCC_PLLCFGR_PLL3REN_Pos        (29U)
#define RCC_PLLCFGR_PLL3REN_Msk        (0x1UL << RCC_PLLCFGR_PLL3REN_Pos)      /*!< 0x20000000 */
#define RCC_PLLCFGR_PLL3REN            RCC_PLLCFGR_PLL3REN_Msk                 /*!< PLL3 DIVR divider output enable */
#define RCC_PLLCFGR_PLL3SEN_Pos        (30U)
#define RCC_PLLCFGR_PLL3SEN_Msk        (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos)      /*!< 0x40000000 */
#define RCC_PLLCFGR_PLL3SEN            RCC_PLLCFGR_PLL3SEN_Msk                 /*!< PLL3 DIVS divider output enable */

/********************  Bit definition for RCC_PLL1DIVR1 register  *************/
#define RCC_PLL1DIVR1_DIVN_Pos        (0U)
#define RCC_PLL1DIVR1_DIVN_Msk        (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x000001FF */
#define RCC_PLL1DIVR1_DIVN            RCC_PLL1DIVR1_DIVN_Msk                 /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */
#define RCC_PLL1DIVR1_DIVN_0          (0x001UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000001 */
#define RCC_PLL1DIVR1_DIVN_1          (0x002UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000002 */
#define RCC_PLL1DIVR1_DIVN_2          (0x004UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000004 */
#define RCC_PLL1DIVR1_DIVN_3          (0x008UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000008 */
#define RCC_PLL1DIVR1_DIVN_4          (0x010UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000010 */
#define RCC_PLL1DIVR1_DIVN_5          (0x020UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000020 */
#define RCC_PLL1DIVR1_DIVN_6          (0x040UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000040 */
#define RCC_PLL1DIVR1_DIVN_7          (0x080UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000080 */
#define RCC_PLL1DIVR1_DIVN_8          (0x100UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000100 */

#define RCC_PLL1DIVR1_DIVP_Pos        (9U)
#define RCC_PLL1DIVR1_DIVP_Msk        (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos)     /*!< 0x0000FE00 */
#define RCC_PLL1DIVR1_DIVP            RCC_PLL1DIVR1_DIVP_Msk                 /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */
#define RCC_PLL1DIVR1_DIVP_0          (0x001UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00000200 */
#define RCC_PLL1DIVR1_DIVP_1          (0x002UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00000400 */
#define RCC_PLL1DIVR1_DIVP_2          (0x004UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00000800 */
#define RCC_PLL1DIVR1_DIVP_3          (0x008UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00001000 */
#define RCC_PLL1DIVR1_DIVP_4          (0x010UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00002000 */
#define RCC_PLL1DIVR1_DIVP_5          (0x020UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00004000 */
#define RCC_PLL1DIVR1_DIVP_6          (0x040UL << RCC_PLL1DIVR1_DIVP_Pos)    /*!< 0x00008000 */

#define RCC_PLL1DIVR1_DIVQ_Pos        (16U)
#define RCC_PLL1DIVR1_DIVQ_Msk        (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos)     /*!< 0x007F0000 */
#define RCC_PLL1DIVR1_DIVQ            RCC_PLL1DIVR1_DIVQ_Msk                 /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */
#define RCC_PLL1DIVR1_DIVQ_0          (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00010000 */
#define RCC_PLL1DIVR1_DIVQ_1          (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00020000 */
#define RCC_PLL1DIVR1_DIVQ_2          (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00040000 */
#define RCC_PLL1DIVR1_DIVQ_3          (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00080000 */
#define RCC_PLL1DIVR1_DIVQ_4          (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00100000 */
#define RCC_PLL1DIVR1_DIVQ_5          (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00200000 */
#define RCC_PLL1DIVR1_DIVQ_6          (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos)    /*!< 0x00400000 */

#define RCC_PLL1DIVR1_DIVR_Pos        (24U)
#define RCC_PLL1DIVR1_DIVR_Msk        (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos)     /*!< 0x7F000000 */
#define RCC_PLL1DIVR1_DIVR            RCC_PLL1DIVR1_DIVR_Msk                 /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */
#define RCC_PLL1DIVR1_DIVR_0          (0x001UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x01000000 */
#define RCC_PLL1DIVR1_DIVR_1          (0x002UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x02000000 */
#define RCC_PLL1DIVR1_DIVR_2          (0x004UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x04000000 */
#define RCC_PLL1DIVR1_DIVR_3          (0x008UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x08000000 */
#define RCC_PLL1DIVR1_DIVR_4          (0x010UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x10000000 */
#define RCC_PLL1DIVR1_DIVR_5          (0x020UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x20000000 */
#define RCC_PLL1DIVR1_DIVR_6          (0x040UL << RCC_PLL1DIVR1_DIVR_Pos)    /*!< 0x40000000 */

/********************  Bit definition for RCC_PLL1FRACR register  *************/
#define RCC_PLL1FRACR_FRACN_Pos        (3U)
#define RCC_PLL1FRACR_FRACN_Msk        (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL1FRACR_FRACN            RCC_PLL1FRACR_FRACN_Msk               /*!< FRACN[12:0] bits */

/********************  Bit definition for RCC_PLL2DIVR1 register  *************/
#define RCC_PLL2DIVR1_DIVN_Pos        (0U)
#define RCC_PLL2DIVR1_DIVN_Msk        (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x000001FF */
#define RCC_PLL2DIVR1_DIVN            RCC_PLL2DIVR1_DIVN_Msk                 /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */
#define RCC_PLL2DIVR1_DIVN_0          (0x001UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000001 */
#define RCC_PLL2DIVR1_DIVN_1          (0x002UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000002 */
#define RCC_PLL2DIVR1_DIVN_2          (0x004UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000004 */
#define RCC_PLL2DIVR1_DIVN_3          (0x008UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000008 */
#define RCC_PLL2DIVR1_DIVN_4          (0x010UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000010 */
#define RCC_PLL2DIVR1_DIVN_5          (0x020UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000020 */
#define RCC_PLL2DIVR1_DIVN_6          (0x040UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000040 */
#define RCC_PLL2DIVR1_DIVN_7          (0x080UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000080 */
#define RCC_PLL2DIVR1_DIVN_8          (0x100UL << RCC_PLL2DIVR1_DIVN_Pos)    /*!< 0x00000100 */

#define RCC_PLL2DIVR1_DIVP_Pos        (9U)
#define RCC_PLL2DIVR1_DIVP_Msk        (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos)     /*!< 0x0000FE00 */
#define RCC_PLL2DIVR1_DIVP            RCC_PLL2DIVR1_DIVP_Msk                 /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */
#define RCC_PLL2DIVR1_DIVP_0          (0x001UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00000200 */
#define RCC_PLL2DIVR1_DIVP_1          (0x002UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00000400 */
#define RCC_PLL2DIVR1_DIVP_2          (0x004UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00000800 */
#define RCC_PLL2DIVR1_DIVP_3          (0x008UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00001000 */
#define RCC_PLL2DIVR1_DIVP_4          (0x010UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00002000 */
#define RCC_PLL2DIVR1_DIVP_5          (0x020UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00004000 */
#define RCC_PLL2DIVR1_DIVP_6          (0x040UL << RCC_PLL2DIVR1_DIVP_Pos)    /*!< 0x00008000 */

#define RCC_PLL2DIVR1_DIVQ_Pos        (16U)
#define RCC_PLL2DIVR1_DIVQ_Msk        (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos)     /*!< 0x007F0000 */
#define RCC_PLL2DIVR1_DIVQ            RCC_PLL2DIVR1_DIVQ_Msk                 /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */
#define RCC_PLL2DIVR1_DIVQ_0          (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00010000 */
#define RCC_PLL2DIVR1_DIVQ_1          (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00020000 */
#define RCC_PLL2DIVR1_DIVQ_2          (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00040000 */
#define RCC_PLL2DIVR1_DIVQ_3          (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00080000 */
#define RCC_PLL2DIVR1_DIVQ_4          (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00100000 */
#define RCC_PLL2DIVR1_DIVQ_5          (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00200000 */
#define RCC_PLL2DIVR1_DIVQ_6          (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos)    /*!< 0x00400000 */

#define RCC_PLL2DIVR1_DIVR_Pos        (24U)
#define RCC_PLL2DIVR1_DIVR_Msk        (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos)     /*!< 0x7F000000 */
#define RCC_PLL2DIVR1_DIVR            RCC_PLL2DIVR1_DIVR_Msk                 /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */
#define RCC_PLL2DIVR1_DIVR_0          (0x001UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x01000000 */
#define RCC_PLL2DIVR1_DIVR_1          (0x002UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x02000000 */
#define RCC_PLL2DIVR1_DIVR_2          (0x004UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x04000000 */
#define RCC_PLL2DIVR1_DIVR_3          (0x008UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x08000000 */
#define RCC_PLL2DIVR1_DIVR_4          (0x010UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x10000000 */
#define RCC_PLL2DIVR1_DIVR_5          (0x020UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x20000000 */
#define RCC_PLL2DIVR1_DIVR_6          (0x040UL << RCC_PLL2DIVR1_DIVR_Pos)    /*!< 0x40000000 */

/********************  Bit definition for RCC_PLL2FRACR register  *************/
#define RCC_PLL2FRACR_FRACN_Pos        (3U)
#define RCC_PLL2FRACR_FRACN_Msk        (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL2FRACR_FRACN            RCC_PLL2FRACR_FRACN_Msk               /*!< FRACN[12:0] bits */

/********************  Bit definition for RCC_PLL3DIVR1 register  *************/
#define RCC_PLL3DIVR1_DIVN_Pos        (0U)
#define RCC_PLL3DIVR1_DIVN_Msk        (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x000001FF */
#define RCC_PLL3DIVR1_DIVN            RCC_PLL3DIVR1_DIVN_Msk                 /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */
#define RCC_PLL3DIVR1_DIVN_0          (0x001UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000001 */
#define RCC_PLL3DIVR1_DIVN_1          (0x002UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000002 */
#define RCC_PLL3DIVR1_DIVN_2          (0x004UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000004 */
#define RCC_PLL3DIVR1_DIVN_3          (0x008UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000008 */
#define RCC_PLL3DIVR1_DIVN_4          (0x010UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000010 */
#define RCC_PLL3DIVR1_DIVN_5          (0x020UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000020 */
#define RCC_PLL3DIVR1_DIVN_6          (0x040UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000040 */
#define RCC_PLL3DIVR1_DIVN_7          (0x080UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000080 */
#define RCC_PLL3DIVR1_DIVN_8          (0x100UL << RCC_PLL3DIVR1_DIVN_Pos)    /*!< 0x00000100 */

#define RCC_PLL3DIVR1_DIVP_Pos        (9U)
#define RCC_PLL3DIVR1_DIVP_Msk        (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos)     /*!< 0x0000FE00 */
#define RCC_PLL3DIVR1_DIVP            RCC_PLL3DIVR1_DIVP_Msk                 /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */
#define RCC_PLL3DIVR1_DIVP_0          (0x001UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00000200 */
#define RCC_PLL3DIVR1_DIVP_1          (0x002UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00000400 */
#define RCC_PLL3DIVR1_DIVP_2          (0x004UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00000800 */
#define RCC_PLL3DIVR1_DIVP_3          (0x008UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00001000 */
#define RCC_PLL3DIVR1_DIVP_4          (0x010UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00002000 */
#define RCC_PLL3DIVR1_DIVP_5          (0x020UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00004000 */
#define RCC_PLL3DIVR1_DIVP_6          (0x040UL << RCC_PLL3DIVR1_DIVP_Pos)    /*!< 0x00008000 */

#define RCC_PLL3DIVR1_DIVQ_Pos        (16U)
#define RCC_PLL3DIVR1_DIVQ_Msk        (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos)     /*!< 0x007F0000 */
#define RCC_PLL3DIVR1_DIVQ            RCC_PLL3DIVR1_DIVQ_Msk                 /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */
#define RCC_PLL3DIVR1_DIVQ_0          (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00010000 */
#define RCC_PLL3DIVR1_DIVQ_1          (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00020000 */
#define RCC_PLL3DIVR1_DIVQ_2          (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00040000 */
#define RCC_PLL3DIVR1_DIVQ_3          (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00080000 */
#define RCC_PLL3DIVR1_DIVQ_4          (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00100000 */
#define RCC_PLL3DIVR1_DIVQ_5          (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00200000 */
#define RCC_PLL3DIVR1_DIVQ_6          (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos)    /*!< 0x00400000 */

#define RCC_PLL3DIVR1_DIVR_Pos        (24U)
#define RCC_PLL3DIVR1_DIVR_Msk        (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos)     /*!< 0x7F000000 */
#define RCC_PLL3DIVR1_DIVR            RCC_PLL3DIVR1_DIVR_Msk                 /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */
#define RCC_PLL3DIVR1_DIVR_0          (0x001UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x01000000 */
#define RCC_PLL3DIVR1_DIVR_1          (0x002UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x02000000 */
#define RCC_PLL3DIVR1_DIVR_2          (0x004UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x04000000 */
#define RCC_PLL3DIVR1_DIVR_3          (0x008UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x08000000 */
#define RCC_PLL3DIVR1_DIVR_4          (0x010UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x10000000 */
#define RCC_PLL3DIVR1_DIVR_5          (0x020UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x20000000 */
#define RCC_PLL3DIVR1_DIVR_6          (0x040UL << RCC_PLL3DIVR1_DIVR_Pos)    /*!< 0x40000000 */

/********************  Bit definition for RCC_PLL3FRACR register  *************/
#define RCC_PLL3FRACR_FRACN_Pos        (3U)
#define RCC_PLL3FRACR_FRACN_Msk        (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL3FRACR_FRACN            RCC_PLL3FRACR_FRACN_Msk               /*!< FRACN[12:0] bits */

/********************  Bit definition for RCC_CCIPR1 register  **************/
#define RCC_CCIPR1_FMCSEL_Pos        (0U)
#define RCC_CCIPR1_FMCSEL_Msk        (0x3UL << RCC_CCIPR1_FMCSEL_Pos)        /*!< 0x00000003 */
#define RCC_CCIPR1_FMCSEL            RCC_CCIPR1_FMCSEL_Msk
#define RCC_CCIPR1_FMCSEL_0          (0x1UL << RCC_CCIPR1_FMCSEL_Pos)        /*!< 0x00000001 */
#define RCC_CCIPR1_FMCSEL_1          (0x2UL << RCC_CCIPR1_FMCSEL_Pos)        /*!< 0x00000002 */

#define RCC_CCIPR1_SDMMC12SEL_Pos    (2U)
#define RCC_CCIPR1_SDMMC12SEL_Msk    (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos)      /*!< 0x00000004 */
#define RCC_CCIPR1_SDMMC12SEL        RCC_CCIPR1_SDMMC12SEL_Msk

#define RCC_CCIPR1_XSPI1SEL_Pos      (4U)
#define RCC_CCIPR1_XSPI1SEL_Msk      (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos)      /*!< 0x00000030 */
#define RCC_CCIPR1_XSPI1SEL          RCC_CCIPR1_XSPI1SEL_Msk
#define RCC_CCIPR1_XSPI1SEL_0        (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos)      /*!< 0x00000010 */
#define RCC_CCIPR1_XSPI1SEL_1        (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos)      /*!< 0x00000020 */

#define RCC_CCIPR1_XSPI2SEL_Pos      (6U)
#define RCC_CCIPR1_XSPI2SEL_Msk      (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos)      /*!< 0x000000C0 */
#define RCC_CCIPR1_XSPI2SEL          RCC_CCIPR1_XSPI2SEL_Msk
#define RCC_CCIPR1_XSPI2SEL_0        (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos)      /*!< 0x00000040 */
#define RCC_CCIPR1_XSPI2SEL_1        (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos)      /*!< 0x00000080 */

#define RCC_CCIPR1_USBREFCKSEL_Pos   (8U)
#define RCC_CCIPR1_USBREFCKSEL_Msk   (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos)   /*!< 0x00000F00 */
#define RCC_CCIPR1_USBREFCKSEL       RCC_CCIPR1_USBREFCKSEL_Msk
#define RCC_CCIPR1_USBREFCKSEL_0     (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos)   /*!< 0x00000100 */
#define RCC_CCIPR1_USBREFCKSEL_1     (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos)   /*!< 0x00000200 */
#define RCC_CCIPR1_USBREFCKSEL_2     (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos)   /*!< 0x00000400 */
#define RCC_CCIPR1_USBREFCKSEL_3     (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos)   /*!< 0x00000800 */

#define RCC_CCIPR1_USBPHYCSEL_Pos    (12U)
#define RCC_CCIPR1_USBPHYCSEL_Msk    (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos)    /*!< 0x00003000 */
#define RCC_CCIPR1_USBPHYCSEL        RCC_CCIPR1_USBPHYCSEL_Msk
#define RCC_CCIPR1_USBPHYCSEL_0      (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos)    /*!< 0x00001000 */
#define RCC_CCIPR1_USBPHYCSEL_1      (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos)    /*!< 0x00002000 */

#define RCC_CCIPR1_OTGFSSEL_Pos      (14U)
#define RCC_CCIPR1_OTGFSSEL_Msk      (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos)      /*!< 0x0000C000 */
#define RCC_CCIPR1_OTGFSSEL          RCC_CCIPR1_OTGFSSEL_Msk
#define RCC_CCIPR1_OTGFSSEL_0        (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos)      /*!< 0x00004000 */
#define RCC_CCIPR1_OTGFSSEL_1        (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos)      /*!< 0x00008000 */

#define RCC_CCIPR1_ETH1REFCKSEL_Pos  (16U)
#define RCC_CCIPR1_ETH1REFCKSEL_Msk  (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos)  /*!< 0x00030000 */
#define RCC_CCIPR1_ETH1REFCKSEL       RCC_CCIPR1_ETH1REFCKSEL_Msk
#define RCC_CCIPR1_ETH1REFCKSEL_0    (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos)  /*!< 0x00010000 */
#define RCC_CCIPR1_ETH1REFCKSEL_1    (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos)  /*!< 0x00020000 */

#define RCC_CCIPR1_ETH1PHYCKSEL_Pos  (18U)
#define RCC_CCIPR1_ETH1PHYCKSEL_Msk  (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos)  /*!< 0x00040000 */
#define RCC_CCIPR1_ETH1PHYCKSEL      RCC_CCIPR1_ETH1PHYCKSEL_Msk

#define RCC_CCIPR1_ADF1SEL_Pos       (20U)
#define RCC_CCIPR1_ADF1SEL_Msk       (0x7UL << RCC_CCIPR1_ADF1SEL_Pos)       /*!< 0x00700000 */
#define RCC_CCIPR1_ADF1SEL           RCC_CCIPR1_ADF1SEL_Msk
#define RCC_CCIPR1_ADF1SEL_0         (0x1UL << RCC_CCIPR1_ADF1SEL_Pos)       /*!< 0x00100000 */
#define RCC_CCIPR1_ADF1SEL_1         (0x2UL << RCC_CCIPR1_ADF1SEL_Pos)       /*!< 0x00200000 */
#define RCC_CCIPR1_ADF1SEL_2         (0x4UL << RCC_CCIPR1_ADF1SEL_Pos)       /*!< 0x00400000 */

#define RCC_CCIPR1_ADCSEL_Pos        (24U)
#define RCC_CCIPR1_ADCSEL_Msk        (0x3UL << RCC_CCIPR1_ADCSEL_Pos)        /*!< 0x03000000 */
#define RCC_CCIPR1_ADCSEL            RCC_CCIPR1_ADCSEL_Msk
#define RCC_CCIPR1_ADCSEL_0          (0x1UL << RCC_CCIPR1_ADCSEL_Pos)        /*!< 0x01000000 */
#define RCC_CCIPR1_ADCSEL_1          (0x2UL << RCC_CCIPR1_ADCSEL_Pos)        /*!< 0x02000000 */

#define RCC_CCIPR1_PSSISEL_Pos       (27U)
#define RCC_CCIPR1_PSSISEL_Msk       (0x1UL << RCC_CCIPR1_PSSISEL_Pos)       /*!< 0x08000000 */
#define RCC_CCIPR1_PSSISEL           RCC_CCIPR1_PSSISEL_Msk

#define RCC_CCIPR1_CKPERSEL_Pos      (28U)
#define RCC_CCIPR1_CKPERSEL_Msk      (0x3UL << RCC_CCIPR1_CKPERSEL_Pos)      /*!< 0x30000000 */
#define RCC_CCIPR1_CKPERSEL          RCC_CCIPR1_CKPERSEL_Msk
#define RCC_CCIPR1_CKPERSEL_0        (0x1UL << RCC_CCIPR1_CKPERSEL_Pos)      /*!< 0x10000000 */
#define RCC_CCIPR1_CKPERSEL_1        (0x2UL << RCC_CCIPR1_CKPERSEL_Pos)      /*!< 0x20000000 */

/********************  Bit definition for RCC_CCIPR2 register  *************/
#define RCC_CCIPR2_UART234578SEL_Pos (0U)
#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR2_UART234578SEL     RCC_CCIPR2_UART234578SEL_Msk
#define RCC_CCIPR2_UART234578SEL_0   (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR2_UART234578SEL_1   (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR2_UART234578SEL_2   (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */

#define RCC_CCIPR2_SPI23SEL_Pos      (4U)
#define RCC_CCIPR2_SPI23SEL_Msk      (0x7UL << RCC_CCIPR2_SPI23SEL_Pos)      /*!< 0x00000070 */
#define RCC_CCIPR2_SPI23SEL          RCC_CCIPR2_SPI23SEL_Msk
#define RCC_CCIPR2_SPI23SEL_0        (0x1UL << RCC_CCIPR2_SPI23SEL_Pos)      /*!< 0x00000010 */
#define RCC_CCIPR2_SPI23SEL_1        (0x2UL << RCC_CCIPR2_SPI23SEL_Pos)      /*!< 0x00000020 */
#define RCC_CCIPR2_SPI23SEL_2        (0x4UL << RCC_CCIPR2_SPI23SEL_Pos)      /*!< 0x00000040 */

#define RCC_CCIPR2_I2C23SEL_Pos      (8U)
#define RCC_CCIPR2_I2C23SEL_Msk      (0x3UL << RCC_CCIPR2_I2C23SEL_Pos)      /*!< 0x00000300 */
#define RCC_CCIPR2_I2C23SEL          RCC_CCIPR2_I2C23SEL_Msk
#define RCC_CCIPR2_I2C23SEL_0        (0x1UL << RCC_CCIPR2_I2C23SEL_Pos)      /*!< 0x00000100 */
#define RCC_CCIPR2_I2C23SEL_1        (0x2UL << RCC_CCIPR2_I2C23SEL_Pos)      /*!< 0x00000200 */

#define RCC_CCIPR2_I2C1_I3C1SEL_Pos  (12U)
#define RCC_CCIPR2_I2C1_I3C1SEL_Msk  (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos)  /*!< 0x00003000 */
#define RCC_CCIPR2_I2C1_I3C1SEL      RCC_CCIPR2_I2C1_I3C1SEL_Msk
#define RCC_CCIPR2_I2C1_I3C1SEL_0    (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos)  /*!< 0x00001000 */
#define RCC_CCIPR2_I2C1_I3C1SEL_1    (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos)  /*!< 0x00002000 */

#define RCC_CCIPR2_LPTIM1SEL_Pos     (16U)
#define RCC_CCIPR2_LPTIM1SEL_Msk     (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00070000 */
#define RCC_CCIPR2_LPTIM1SEL         RCC_CCIPR2_LPTIM1SEL_Msk
#define RCC_CCIPR2_LPTIM1SEL_0       (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00010000 */
#define RCC_CCIPR2_LPTIM1SEL_1       (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00020000 */
#define RCC_CCIPR2_LPTIM1SEL_2       (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00040000 */

#define RCC_CCIPR2_FDCANSEL_Pos      (22U)
#define RCC_CCIPR2_FDCANSEL_Msk      (0x3UL << RCC_CCIPR2_FDCANSEL_Pos)     /*!< 0x00C00000 */
#define RCC_CCIPR2_FDCANSEL          RCC_CCIPR2_FDCANSEL_Msk
#define RCC_CCIPR2_FDCANSEL_0        (0x1UL << RCC_CCIPR2_FDCANSEL_Pos)     /*!< 0x00400000 */
#define RCC_CCIPR2_FDCANSEL_1        (0x2UL << RCC_CCIPR2_FDCANSEL_Pos)     /*!< 0x00800000 */

#define RCC_CCIPR2_SPDIFRXSEL_Pos    (24U)
#define RCC_CCIPR2_SPDIFRXSEL_Msk    (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos)   /*!< 0x03000000 */
#define RCC_CCIPR2_SPDIFRXSEL        RCC_CCIPR2_SPDIFRXSEL_Msk
#define RCC_CCIPR2_SPDIFRXSEL_0      (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos)   /*!< 0x01000000 */
#define RCC_CCIPR2_SPDIFRXSEL_1      (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos)   /*!< 0x02000000 */

#define RCC_CCIPR2_CECSEL_Pos        (28U)
#define RCC_CCIPR2_CECSEL_Msk        (0x3UL << RCC_CCIPR2_CECSEL_Pos)       /*!< 0x03000000 */
#define RCC_CCIPR2_CECSEL            RCC_CCIPR2_CECSEL_Msk
#define RCC_CCIPR2_CECSEL_0          (0x1UL << RCC_CCIPR2_CECSEL_Pos)       /*!< 0x01000000 */
#define RCC_CCIPR2_CECSEL_1          (0x2UL << RCC_CCIPR2_CECSEL_Pos)       /*!< 0x02000000 */

/********************  Bit definition for RCC_CCIPR3 register  *************/
#define RCC_CCIPR3_USART1SEL_Pos     (0U)
#define RCC_CCIPR3_USART1SEL_Msk     (0x7UL << RCC_CCIPR3_USART1SEL_Pos)    /*!< 0x00000007 */
#define RCC_CCIPR3_USART1SEL         RCC_CCIPR3_USART1SEL_Msk
#define RCC_CCIPR3_USART1SEL_0       (0x1UL << RCC_CCIPR3_USART1SEL_Pos)    /*!< 0x00000001 */
#define RCC_CCIPR3_USART1SEL_1       (0x2UL << RCC_CCIPR3_USART1SEL_Pos)    /*!< 0x00000002 */
#define RCC_CCIPR3_USART1SEL_2       (0x4UL << RCC_CCIPR3_USART1SEL_Pos)    /*!< 0x00000004 */

#define RCC_CCIPR3_SPI45SEL_Pos      (4U)
#define RCC_CCIPR3_SPI45SEL_Msk      (0x7UL << RCC_CCIPR3_SPI45SEL_Pos)     /*!< 0x00000070 */
#define RCC_CCIPR3_SPI45SEL          RCC_CCIPR3_SPI45SEL_Msk
#define RCC_CCIPR3_SPI45SEL_0        (0x1UL << RCC_CCIPR3_SPI45SEL_Pos)     /*!< 0x00000010 */
#define RCC_CCIPR3_SPI45SEL_1        (0x2UL << RCC_CCIPR3_SPI45SEL_Pos)     /*!< 0x00000020 */
#define RCC_CCIPR3_SPI45SEL_2        (0x4UL << RCC_CCIPR3_SPI45SEL_Pos)     /*!< 0x00000040 */

#define RCC_CCIPR3_SPI1SEL_Pos       (8U)
#define RCC_CCIPR3_SPI1SEL_Msk       (0x7UL << RCC_CCIPR3_SPI1SEL_Pos)      /*!< 0x00000700 */
#define RCC_CCIPR3_SPI1SEL           RCC_CCIPR3_SPI1SEL_Msk
#define RCC_CCIPR3_SPI1SEL_0         (0x1UL << RCC_CCIPR3_SPI1SEL_Pos)      /*!< 0x00000100 */
#define RCC_CCIPR3_SPI1SEL_1         (0x2UL << RCC_CCIPR3_SPI1SEL_Pos)      /*!< 0x00000200 */
#define RCC_CCIPR3_SPI1SEL_2         (0x4UL << RCC_CCIPR3_SPI1SEL_Pos)      /*!< 0x00000400 */

#define RCC_CCIPR3_SAI1SEL_Pos       (16U)
#define RCC_CCIPR3_SAI1SEL_Msk       (0x7UL << RCC_CCIPR3_SAI1SEL_Pos)      /*!< 0x00070000 */
#define RCC_CCIPR3_SAI1SEL           RCC_CCIPR3_SAI1SEL_Msk
#define RCC_CCIPR3_SAI1SEL_0         (0x1UL << RCC_CCIPR3_SAI1SEL_Pos)      /*!< 0x00010000 */
#define RCC_CCIPR3_SAI1SEL_1         (0x2UL << RCC_CCIPR3_SAI1SEL_Pos)      /*!< 0x00020000 */
#define RCC_CCIPR3_SAI1SEL_2         (0x4UL << RCC_CCIPR3_SAI1SEL_Pos)      /*!< 0x00040000 */

#define RCC_CCIPR3_SAI2SEL_Pos       (20U)
#define RCC_CCIPR3_SAI2SEL_Msk       (0x7UL << RCC_CCIPR3_SAI2SEL_Pos)      /*!< 0x00700000 */
#define RCC_CCIPR3_SAI2SEL           RCC_CCIPR3_SAI2SEL_Msk
#define RCC_CCIPR3_SAI2SEL_0         (0x1UL << RCC_CCIPR3_SAI2SEL_Pos)      /*!< 0x00100000 */
#define RCC_CCIPR3_SAI2SEL_1         (0x2UL << RCC_CCIPR3_SAI2SEL_Pos)      /*!< 0x00200000 */
#define RCC_CCIPR3_SAI2SEL_2         (0x4UL << RCC_CCIPR3_SAI2SEL_Pos)      /*!< 0x00400000 */

/********************  Bit definition for RCC_CCIPR4 register  ************/
#define RCC_CCIPR4_LPUART1SEL_Pos    (0U)
#define RCC_CCIPR4_LPUART1SEL_Msk    (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos)   /*!< 0x00000007 */
#define RCC_CCIPR4_LPUART1SEL        RCC_CCIPR4_LPUART1SEL_Msk
#define RCC_CCIPR4_LPUART1SEL_0      (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos)   /*!< 0x00000001 */
#define RCC_CCIPR4_LPUART1SEL_1      (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos)   /*!< 0x00000002 */
#define RCC_CCIPR4_LPUART1SEL_2      (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos)   /*!< 0x00000004 */

#define RCC_CCIPR4_SPI6SEL_Pos       (4U)
#define RCC_CCIPR4_SPI6SEL_Msk       (0x7UL << RCC_CCIPR4_SPI6SEL_Pos)      /*!< 0x00000070 */
#define RCC_CCIPR4_SPI6SEL           RCC_CCIPR4_SPI6SEL_Msk
#define RCC_CCIPR4_SPI6SEL_0         (0x1UL << RCC_CCIPR4_SPI6SEL_Pos)      /*!< 0x00000010 */
#define RCC_CCIPR4_SPI6SEL_1         (0x2UL << RCC_CCIPR4_SPI6SEL_Pos)      /*!< 0x00000020 */
#define RCC_CCIPR4_SPI6SEL_2         (0x4UL << RCC_CCIPR4_SPI6SEL_Pos)      /*!< 0x00000040 */

#define RCC_CCIPR4_LPTIM23SEL_Pos    (8U)
#define RCC_CCIPR4_LPTIM23SEL_Msk    (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos)   /*!< 0x00000700 */
#define RCC_CCIPR4_LPTIM23SEL        RCC_CCIPR4_LPTIM23SEL_Msk
#define RCC_CCIPR4_LPTIM23SEL_0      (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos)   /*!< 0x00000100 */
#define RCC_CCIPR4_LPTIM23SEL_1      (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos)   /*!< 0x00000200 */
#define RCC_CCIPR4_LPTIM23SEL_2      (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos)   /*!< 0x00000400 */

#define RCC_CCIPR4_LPTIM45SEL_Pos    (12U)
#define RCC_CCIPR4_LPTIM45SEL_Msk    (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos)   /*!< 0x00007000 */
#define RCC_CCIPR4_LPTIM45SEL        RCC_CCIPR4_LPTIM45SEL_Msk
#define RCC_CCIPR4_LPTIM45SEL_0      (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos)   /*!< 0x00001000 */
#define RCC_CCIPR4_LPTIM45SEL_1      (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos)   /*!< 0x00002000 */
#define RCC_CCIPR4_LPTIM45SEL_2      (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos)   /*!< 0x00004000 */

/********************  Bit definition for RCC_CIER register  ******************/
#define RCC_CIER_LSIRDYIE_Pos          (0U)
#define RCC_CIER_LSIRDYIE_Msk          (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE              RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos          (1U)
#define RCC_CIER_LSERDYIE_Msk          (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE              RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos          (2U)
#define RCC_CIER_HSIRDYIE_Msk          (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000004 */
#define RCC_CIER_HSIRDYIE              RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos          (3U)
#define RCC_CIER_HSERDYIE_Msk          (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000008 */
#define RCC_CIER_HSERDYIE              RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_CSIRDYIE_Pos          (4U)
#define RCC_CIER_CSIRDYIE_Msk          (0x1UL << RCC_CIER_CSIRDYIE_Pos)        /*!< 0x00000010 */
#define RCC_CIER_CSIRDYIE              RCC_CIER_CSIRDYIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos        (5U)
#define RCC_CIER_HSI48RDYIE_Msk        (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000020 */
#define RCC_CIER_HSI48RDYIE            RCC_CIER_HSI48RDYIE_Msk
#define RCC_CIER_PLL1RDYIE_Pos         (6U)
#define RCC_CIER_PLL1RDYIE_Msk         (0x1UL << RCC_CIER_PLL1RDYIE_Pos)       /*!< 0x00000040 */
#define RCC_CIER_PLL1RDYIE             RCC_CIER_PLL1RDYIE_Msk
#define RCC_CIER_PLL2RDYIE_Pos         (7U)
#define RCC_CIER_PLL2RDYIE_Msk         (0x1UL << RCC_CIER_PLL2RDYIE_Pos)       /*!< 0x00000080 */
#define RCC_CIER_PLL2RDYIE             RCC_CIER_PLL2RDYIE_Msk
#define RCC_CIER_PLL3RDYIE_Pos         (8U)
#define RCC_CIER_PLL3RDYIE_Msk         (0x1UL << RCC_CIER_PLL3RDYIE_Pos)       /*!< 0x00000100 */
#define RCC_CIER_PLL3RDYIE             RCC_CIER_PLL3RDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos          (9U)
#define RCC_CIER_LSECSSIE_Msk          (0x1UL << RCC_CIER_LSECSSIE_Pos)        /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE              RCC_CIER_LSECSSIE_Msk

/********************  Bit definition for RCC_CIFR register  ******************/
#define RCC_CIFR_LSIRDYF_Pos           (0U)
#define RCC_CIFR_LSIRDYF_Msk           (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF               RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos           (1U)
#define RCC_CIFR_LSERDYF_Msk           (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF               RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos           (2U)
#define RCC_CIFR_HSIRDYF_Msk           (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000004 */
#define RCC_CIFR_HSIRDYF               RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos           (3U)
#define RCC_CIFR_HSERDYF_Msk           (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000008 */
#define RCC_CIFR_HSERDYF               RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_CSIRDYF_Pos           (4U)
#define RCC_CIFR_CSIRDYF_Msk           (0x1UL << RCC_CIFR_CSIRDYF_Pos)         /*!< 0x00000010 */
#define RCC_CIFR_CSIRDYF               RCC_CIFR_CSIRDYF_Msk
#define RCC_CIFR_HSI48RDYF_Pos         (5U)
#define RCC_CIFR_HSI48RDYF_Msk         (0x1UL << RCC_CIFR_HSI48RDYF_Pos)       /*!< 0x00000020 */
#define RCC_CIFR_HSI48RDYF             RCC_CIFR_HSI48RDYF_Msk
#define RCC_CIFR_PLL1RDYF_Pos          (6U)
#define RCC_CIFR_PLL1RDYF_Msk          (0x1UL << RCC_CIFR_PLL1RDYF_Pos)        /*!< 0x00000040 */
#define RCC_CIFR_PLL1RDYF              RCC_CIFR_PLL1RDYF_Msk
#define RCC_CIFR_PLL2RDYF_Pos          (7U)
#define RCC_CIFR_PLL2RDYF_Msk          (0x1UL << RCC_CIFR_PLL2RDYF_Pos)        /*!< 0x00000080 */
#define RCC_CIFR_PLL2RDYF              RCC_CIFR_PLL2RDYF_Msk
#define RCC_CIFR_PLL3RDYF_Pos          (8U)
#define RCC_CIFR_PLL3RDYF_Msk          (0x1UL << RCC_CIFR_PLL3RDYF_Pos)        /*!< 0x00000100 */
#define RCC_CIFR_PLL3RDYF              RCC_CIFR_PLL3RDYF_Msk
#define RCC_CIFR_LSECSSF_Pos           (9U)
#define RCC_CIFR_LSECSSF_Msk           (0x1UL << RCC_CIFR_LSECSSF_Pos)         /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF               RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSECSSF_Pos           (10U)
#define RCC_CIFR_HSECSSF_Msk           (0x1UL << RCC_CIFR_HSECSSF_Pos)         /*!< 0x00000400 */
#define RCC_CIFR_HSECSSF               RCC_CIFR_HSECSSF_Msk

/********************  Bit definition for RCC_CICR register  ******************/
#define RCC_CICR_LSIRDYC_Pos           (0U)
#define RCC_CICR_LSIRDYC_Msk           (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC               RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos           (1U)
#define RCC_CICR_LSERDYC_Msk           (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
#define RCC_CICR_LSERDYC               RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos           (2U)
#define RCC_CICR_HSIRDYC_Msk           (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000004 */
#define RCC_CICR_HSIRDYC               RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos           (3U)
#define RCC_CICR_HSERDYC_Msk           (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000008 */
#define RCC_CICR_HSERDYC               RCC_CICR_HSERDYC_Msk
#define RCC_CICR_CSIRDYC_Pos           (4U)
#define RCC_CICR_CSIRDYC_Msk           (0x1UL << RCC_CICR_CSIRDYC_Pos)         /*!< 0x00000010 */
#define RCC_CICR_CSIRDYC               RCC_CICR_CSIRDYC_Msk
#define RCC_CICR_HSI48RDYC_Pos         (5U)
#define RCC_CICR_HSI48RDYC_Msk         (0x1UL << RCC_CICR_HSI48RDYC_Pos)       /*!< 0x00000020 */
#define RCC_CICR_HSI48RDYC             RCC_CICR_HSI48RDYC_Msk
#define RCC_CICR_PLL1RDYC_Pos          (6U)
#define RCC_CICR_PLL1RDYC_Msk          (0x1UL << RCC_CICR_PLL1RDYC_Pos)        /*!< 0x00000040 */
#define RCC_CICR_PLL1RDYC              RCC_CICR_PLL1RDYC_Msk
#define RCC_CICR_PLL2RDYC_Pos          (7U)
#define RCC_CICR_PLL2RDYC_Msk          (0x1UL << RCC_CICR_PLL2RDYC_Pos)        /*!< 0x00000080 */
#define RCC_CICR_PLL2RDYC              RCC_CICR_PLL2RDYC_Msk
#define RCC_CICR_PLL3RDYC_Pos          (8U)
#define RCC_CICR_PLL3RDYC_Msk          (0x1UL << RCC_CICR_PLL3RDYC_Pos)        /*!< 0x00000100 */
#define RCC_CICR_PLL3RDYC              RCC_CICR_PLL3RDYC_Msk
#define RCC_CICR_LSECSSC_Pos           (9U)
#define RCC_CICR_LSECSSC_Msk           (0x1UL << RCC_CICR_LSECSSC_Pos)         /*!< 0x00000200 */
#define RCC_CICR_LSECSSC               RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSECSSC_Pos           (10U)
#define RCC_CICR_HSECSSC_Msk           (0x1UL << RCC_CICR_HSECSSC_Pos)         /*!< 0x00000400 */
#define RCC_CICR_HSECSSC               RCC_CICR_HSECSSC_Msk

/********************  Bit definition for RCC_BDCR register  ******************/
#define RCC_BDCR_LSEON_Pos             (0U)
#define RCC_BDCR_LSEON_Msk             (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
#define RCC_BDCR_LSEON                 RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos            (1U)
#define RCC_BDCR_LSERDY_Msk            (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
#define RCC_BDCR_LSERDY                RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos            (2U)
#define RCC_BDCR_LSEBYP_Msk            (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP                RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos            (3U)
#define RCC_BDCR_LSEDRV_Msk            (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV                RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0              (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1              (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */

#define RCC_BDCR_LSECSSON_Pos          (5U)
#define RCC_BDCR_LSECSSON_Msk          (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON              RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos           (6U)
#define RCC_BDCR_LSECSSD_Msk           (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD               RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_LSEEXT_Pos            (7U)
#define RCC_BDCR_LSEEXT_Msk            (0x1UL << RCC_BDCR_LSEEXT_Pos)          /*!< 0x00000080 */
#define RCC_BDCR_LSEEXT                RCC_BDCR_LSEEXT_Msk
#define RCC_BDCR_RTCSEL_Pos            (8U)
#define RCC_BDCR_RTCSEL_Msk            (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL                RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0              (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1              (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
#define RCC_BDCR_LSECSSRA_Pos          (12U)
#define RCC_BDCR_LSECSSRA_Msk          (0x1UL << RCC_BDCR_LSECSSRA_Pos)        /*!< 0x00001000 */
#define RCC_BDCR_LSECSSRA              RCC_BDCR_LSECSSRA_Msk

#define RCC_BDCR_RTCEN_Pos             (15U)
#define RCC_BDCR_RTCEN_Msk             (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
#define RCC_BDCR_RTCEN                 RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_VSWRST_Pos            (16U)
#define RCC_BDCR_VSWRST_Msk            (0x1UL << RCC_BDCR_VSWRST_Pos)          /*!< 0x00010000 */
#define RCC_BDCR_VSWRST                RCC_BDCR_VSWRST_Msk

/********************  Bit definition for RCC_CSR register  *******************/
#define RCC_CSR_LSION_Pos              (0U)
#define RCC_CSR_LSION_Msk              (0x1UL << RCC_CSR_LSION_Pos)            /*!< 0x00000001 */
#define RCC_CSR_LSION                  RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos             (1U)
#define RCC_CSR_LSIRDY_Msk             (0x1UL << RCC_CSR_LSIRDY_Pos)           /*!< 0x00000002 */
#define RCC_CSR_LSIRDY                 RCC_CSR_LSIRDY_Msk

/********************  Bit definition for RCC_AHB1RSTR register  **************/
#define RCC_AHB1RSTR_GPDMA1RST_Pos     (4U)
#define RCC_AHB1RSTR_GPDMA1RST_Msk     (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos)   /*!< 0x00000010 */
#define RCC_AHB1RSTR_GPDMA1RST         RCC_AHB1RSTR_GPDMA1RST_Msk
#define RCC_AHB1RSTR_ADC12RST_Pos      (5U)
#define RCC_AHB1RSTR_ADC12RST_Msk      (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)    /*!< 0x00000020 */
#define RCC_AHB1RSTR_ADC12RST          RCC_AHB1RSTR_ADC12RST_Msk
#define RCC_AHB1RSTR_ETH1RST_Pos       (15U)
#define RCC_AHB1RSTR_ETH1RST_Msk       (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos)     /*!< 0x00008000 */
#define RCC_AHB1RSTR_ETH1RST            RCC_AHB1RSTR_ETH1RST_Msk
#define RCC_AHB1RSTR_OTGHSRST_Pos      (25U)
#define RCC_AHB1RSTR_OTGHSRST_Msk      (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos)    /*!< 0x02000000 */
#define RCC_AHB1RSTR_OTGHSRST          RCC_AHB1RSTR_OTGHSRST_Msk
#define RCC_AHB1RSTR_USBPHYCRST_Pos    (26U)
#define RCC_AHB1RSTR_USBPHYCRST_Msk    (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos)  /*!< 0x04000000 */
#define RCC_AHB1RSTR_USBPHYCRST        RCC_AHB1RSTR_USBPHYCRST_Msk
#define RCC_AHB1RSTR_OTGFSRST_Pos      (27U)
#define RCC_AHB1RSTR_OTGFSRST_Msk      (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos)    /*!< 0x08000000 */
#define RCC_AHB1RSTR_OTGFSRST          RCC_AHB1RSTR_OTGFSRST_Msk
#define RCC_AHB1RSTR_ADF1RST_Pos       (31U)
#define RCC_AHB1RSTR_ADF1RST_Msk       (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos)     /*!< 0x80000000 */
#define RCC_AHB1RSTR_ADF1RST           RCC_AHB1RSTR_ADF1RST_Msk

/********************  Bit definition for RCC_AHB2RSTR register  **************/
#define RCC_AHB2RSTR_PSSIRST_Pos       (1U)
#define RCC_AHB2RSTR_PSSIRST_Msk       (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos)     /*!< 0x00000002 */
#define RCC_AHB2RSTR_PSSIRST           RCC_AHB2RSTR_PSSIRST_Msk
#define RCC_AHB2RSTR_SDMMC2RST_Pos     (9U)
#define RCC_AHB2RSTR_SDMMC2RST_Msk     (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)   /*!< 0x00000200 */
#define RCC_AHB2RSTR_SDMMC2RST         RCC_AHB2RSTR_SDMMC2RST_Msk
#define RCC_AHB2RSTR_CORDICRST_Pos     (14U)
#define RCC_AHB2RSTR_CORDICRST_Msk     (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos)   /*!< 0x00004000 */
#define RCC_AHB2RSTR_CORDICRST         RCC_AHB2RSTR_CORDICRST_Msk

/********************  Bit definition for RCC_AHB3RSTR register  **************/
#define RCC_AHB3RSTR_RNGRST_Pos        (0U)
#define RCC_AHB3RSTR_RNGRST_Msk        (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)      /*!< 0x00000001 */
#define RCC_AHB3RSTR_RNGRST            RCC_AHB3RSTR_RNGRST_Msk
#define RCC_AHB3RSTR_HASHRST_Pos       (1U)
#define RCC_AHB3RSTR_HASHRST_Msk       (0x1UL << RCC_AHB3RSTR_HASHRST_Pos)     /*!< 0x00000002 */
#define RCC_AHB3RSTR_HASHRST           RCC_AHB3RSTR_HASHRST_Msk
#define RCC_AHB3RSTR_CRYPRST_Pos       (2U)
#define RCC_AHB3RSTR_CRYPRST_Msk       (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos)     /*!< 0x00000004 */
#define RCC_AHB3RSTR_CRYPRST           RCC_AHB3RSTR_CRYPRST_Msk
#define RCC_AHB3RSTR_SAESRST_Pos       (4U)
#define RCC_AHB3RSTR_SAESRST_Msk       (0x1UL << RCC_AHB3RSTR_SAESRST_Pos)     /*!< 0x00000010 */
#define RCC_AHB3RSTR_SAESRST           RCC_AHB3RSTR_SAESRST_Msk
#define RCC_AHB3RSTR_PKARST_Pos        (6U)
#define RCC_AHB3RSTR_PKARST_Msk        (0x1UL << RCC_AHB3RSTR_PKARST_Pos)      /*!< 0x00000040 */
#define RCC_AHB3RSTR_PKARST            RCC_AHB3RSTR_PKARST_Msk

/********************  Bit definition for RCC_AHB4RSTR register  **************/
#define RCC_AHB4RSTR_GPIOARST_Pos      (0U)
#define RCC_AHB4RSTR_GPIOARST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)    /*!< 0x00000001 */
#define RCC_AHB4RSTR_GPIOARST          RCC_AHB4RSTR_GPIOARST_Msk
#define RCC_AHB4RSTR_GPIOBRST_Pos      (1U)
#define RCC_AHB4RSTR_GPIOBRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)    /*!< 0x00000002 */
#define RCC_AHB4RSTR_GPIOBRST          RCC_AHB4RSTR_GPIOBRST_Msk
#define RCC_AHB4RSTR_GPIOCRST_Pos      (2U)
#define RCC_AHB4RSTR_GPIOCRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)    /*!< 0x00000004 */
#define RCC_AHB4RSTR_GPIOCRST          RCC_AHB4RSTR_GPIOCRST_Msk
#define RCC_AHB4RSTR_GPIODRST_Pos      (3U)
#define RCC_AHB4RSTR_GPIODRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)    /*!< 0x00000008 */
#define RCC_AHB4RSTR_GPIODRST          RCC_AHB4RSTR_GPIODRST_Msk
#define RCC_AHB4RSTR_GPIOERST_Pos      (4U)
#define RCC_AHB4RSTR_GPIOERST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)    /*!< 0x00000010 */
#define RCC_AHB4RSTR_GPIOERST          RCC_AHB4RSTR_GPIOERST_Msk
#define RCC_AHB4RSTR_GPIOFRST_Pos      (5U)
#define RCC_AHB4RSTR_GPIOFRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)    /*!< 0x00000020 */
#define RCC_AHB4RSTR_GPIOFRST          RCC_AHB4RSTR_GPIOFRST_Msk
#define RCC_AHB4RSTR_GPIOGRST_Pos      (6U)
#define RCC_AHB4RSTR_GPIOGRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)    /*!< 0x00000040 */
#define RCC_AHB4RSTR_GPIOGRST          RCC_AHB4RSTR_GPIOGRST_Msk
#define RCC_AHB4RSTR_GPIOHRST_Pos      (7U)
#define RCC_AHB4RSTR_GPIOHRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)    /*!< 0x00000080 */
#define RCC_AHB4RSTR_GPIOHRST          RCC_AHB4RSTR_GPIOHRST_Msk
#define RCC_AHB4RSTR_GPIOMRST_Pos      (12U)
#define RCC_AHB4RSTR_GPIOMRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos)    /*!< 0x00001000 */
#define RCC_AHB4RSTR_GPIOMRST          RCC_AHB4RSTR_GPIOMRST_Msk
#define RCC_AHB4RSTR_GPIONRST_Pos      (13U)
#define RCC_AHB4RSTR_GPIONRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos)    /*!< 0x00002000 */
#define RCC_AHB4RSTR_GPIONRST          RCC_AHB4RSTR_GPIONRST_Msk
#define RCC_AHB4RSTR_GPIOORST_Pos      (14U)
#define RCC_AHB4RSTR_GPIOORST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos)    /*!< 0x00004000 */
#define RCC_AHB4RSTR_GPIOORST          RCC_AHB4RSTR_GPIOORST_Msk
#define RCC_AHB4RSTR_GPIOPRST_Pos      (15U)
#define RCC_AHB4RSTR_GPIOPRST_Msk      (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos)    /*!< 0x00008000 */
#define RCC_AHB4RSTR_GPIOPRST          RCC_AHB4RSTR_GPIOPRST_Msk
#define RCC_AHB4RSTR_CRCRST_Pos        (19U)
#define RCC_AHB4RSTR_CRCRST_Msk        (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)      /*!< 0x00080000 */
#define RCC_AHB4RSTR_CRCRST            RCC_AHB4RSTR_CRCRST_Msk

/********************  Bit definition for RCC_AHB5RSTR register  **************/
#define RCC_AHB5RSTR_HPDMA1RST_Pos     (0U)
#define RCC_AHB5RSTR_HPDMA1RST_Msk     (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos)   /*!< 0x00000001 */
#define RCC_AHB5RSTR_HPDMA1RST         RCC_AHB5RSTR_HPDMA1RST_Msk
#define RCC_AHB5RSTR_DMA2DRST_Pos      (1U)
#define RCC_AHB5RSTR_DMA2DRST_Msk      (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos)    /*!< 0x00000002 */
#define RCC_AHB5RSTR_DMA2DRST          RCC_AHB5RSTR_DMA2DRST_Msk
#define RCC_AHB5RSTR_JPEGRST_Pos       (3U)
#define RCC_AHB5RSTR_JPEGRST_Msk       (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos)     /*!< 0x00000008 */
#define RCC_AHB5RSTR_JPEGRST           RCC_AHB5RSTR_JPEGRST_Msk
#define RCC_AHB5RSTR_FMCRST_Pos        (4U)
#define RCC_AHB5RSTR_FMCRST_Msk        (0x1UL << RCC_AHB5RSTR_FMCRST_Pos)      /*!< 0x00000010 */
#define RCC_AHB5RSTR_FMCRST            RCC_AHB5RSTR_FMCRST_Msk
#define RCC_AHB5RSTR_XSPI1RST_Pos      (5U)
#define RCC_AHB5RSTR_XSPI1RST_Msk      (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos)    /*!< 0x00000020 */
#define RCC_AHB5RSTR_XSPI1RST          RCC_AHB5RSTR_XSPI1RST_Msk
#define RCC_AHB5RSTR_SDMMC1RST_Pos     (8U)
#define RCC_AHB5RSTR_SDMMC1RST_Msk     (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos)   /*!< 0x00000100 */
#define RCC_AHB5RSTR_SDMMC1RST         RCC_AHB5RSTR_SDMMC1RST_Msk
#define RCC_AHB5RSTR_XSPI2RST_Pos      (12U)
#define RCC_AHB5RSTR_XSPI2RST_Msk      (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos)    /*!< 0x00001000 */
#define RCC_AHB5RSTR_XSPI2RST          RCC_AHB5RSTR_XSPI2RST_Msk
#define RCC_AHB5RSTR_XSPIMRST_Pos      (14U)
#define RCC_AHB5RSTR_XSPIMRST_Msk      (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos)    /*!< 0x00004000 */
#define RCC_AHB5RSTR_XSPIMRST          RCC_AHB5RSTR_XSPIMRST_Msk
#define RCC_AHB5RSTR_GFXMMURST_Pos     (19U)
#define RCC_AHB5RSTR_GFXMMURST_Msk     (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos)   /*!< 0x00080000 */
#define RCC_AHB5RSTR_GFXMMURST         RCC_AHB5RSTR_GFXMMURST_Msk

/********************  Bit definition for RCC_APB1RSTR1 register  *************/
#define RCC_APB1RSTR1_TIM2RST_Pos      (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk      (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)    /*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST          RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos      (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk      (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)    /*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST          RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos      (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk      (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)    /*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST          RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM5RST_Pos      (3U)
#define RCC_APB1RSTR1_TIM5RST_Msk      (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)    /*!< 0x00000008 */
#define RCC_APB1RSTR1_TIM5RST          RCC_APB1RSTR1_TIM5RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos      (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk      (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)    /*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST          RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos      (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk      (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)    /*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST          RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_TIM12RST_Pos     (6U)
#define RCC_APB1RSTR1_TIM12RST_Msk     (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos)   /*!< 0x00000040 */
#define RCC_APB1RSTR1_TIM12RST         RCC_APB1RSTR1_TIM12RST_Msk
#define RCC_APB1RSTR1_TIM13RST_Pos     (7U)
#define RCC_APB1RSTR1_TIM13RST_Msk     (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos)   /*!< 0x00000080 */
#define RCC_APB1RSTR1_TIM13RST         RCC_APB1RSTR1_TIM13RST_Msk
#define RCC_APB1RSTR1_TIM14RST_Pos     (8U)
#define RCC_APB1RSTR1_TIM14RST_Msk     (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos)   /*!< 0x00000100 */
#define RCC_APB1RSTR1_TIM14RST         RCC_APB1RSTR1_TIM14RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos    (9U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk    (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)  /*!< 0x00000200 */
#define RCC_APB1RSTR1_LPTIM1RST        RCC_APB1RSTR1_LPTIM1RST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos      (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk      (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)    /*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST          RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos      (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk      (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)    /*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST          RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_SPDIFRXRST_Pos   (16U)
#define RCC_APB1RSTR1_SPDIFRXRST_Msk   (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */
#define RCC_APB1RSTR1_SPDIFRXRST       RCC_APB1RSTR1_SPDIFRXRST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos    (17U)
#define RCC_APB1RSTR1_USART2RST_Msk    (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)  /*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST        RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos    (18U)
#define RCC_APB1RSTR1_USART3RST_Msk    (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)  /*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST        RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos     (19U)
#define RCC_APB1RSTR1_UART4RST_Msk     (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)   /*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST         RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_UART5RST_Pos     (20U)
#define RCC_APB1RSTR1_UART5RST_Msk     (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)   /*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST         RCC_APB1RSTR1_UART5RST_Msk
#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1_I3C1RST     RCC_APB1RSTR1_I2C1_I3C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos      (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk      (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)    /*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST          RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos      (23U)
#define RCC_APB1RSTR1_I2C3RST_Msk      (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)    /*!< 0x00800000 */
#define RCC_APB1RSTR1_I2C3RST          RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_CECRST_Pos       (27U)
#define RCC_APB1RSTR1_CECRST_Msk       (0x1UL << RCC_APB1RSTR1_CECRST_Pos)     /*!< 0x08000000 */
#define RCC_APB1RSTR1_CECRST           RCC_APB1RSTR1_CECRST_Msk
#define RCC_APB1RSTR1_UART7RST_Pos     (30U)
#define RCC_APB1RSTR1_UART7RST_Msk     (0x1UL << RCC_APB1RSTR1_UART7RST_Pos)   /*!< 0x40000000 */
#define RCC_APB1RSTR1_UART7RST         RCC_APB1RSTR1_UART7RST_Msk
#define RCC_APB1RSTR1_UART8RST_Pos     (31U)
#define RCC_APB1RSTR1_UART8RST_Msk     (0x1UL << RCC_APB1RSTR1_UART8RST_Pos)   /*!< 0x80000000 */
#define RCC_APB1RSTR1_UART8RST         RCC_APB1RSTR1_UART8RST_Msk

/********************  Bit definition for RCC_APB1RSTR2 register  *************/
#define RCC_APB1RSTR2_CRSRST_Pos       (1U)
#define RCC_APB1RSTR2_CRSRST_Msk       (0x1UL << RCC_APB1RSTR2_CRSRST_Pos)     /*!< 0x00000002 */
#define RCC_APB1RSTR2_CRSRST           RCC_APB1RSTR2_CRSRST_Msk
#define RCC_APB1RSTR2_MDIOSRST_Pos     (5U)
#define RCC_APB1RSTR2_MDIOSRST_Msk     (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos)   /*!< 0x00000020 */
#define RCC_APB1RSTR2_MDIOSRST         RCC_APB1RSTR2_MDIOSRST_Msk
#define RCC_APB1RSTR2_FDCANRST_Pos     (8U)
#define RCC_APB1RSTR2_FDCANRST_Msk     (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos)   /*!< 0x00000100 */
#define RCC_APB1RSTR2_FDCANRST         RCC_APB1RSTR2_FDCANRST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos     (27U)
#define RCC_APB1RSTR2_UCPD1RST_Msk     (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)   /*!< 0x08000000 */
#define RCC_APB1RSTR2_UCPD1RST         RCC_APB1RSTR2_UCPD1RST_Msk

/********************  Bit definition for RCC_APB2RSTR register  **************/
#define RCC_APB2RSTR_TIM1RST_Pos       (0U)
#define RCC_APB2RSTR_TIM1RST_Msk       (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)     /*!< 0x00000001 */
#define RCC_APB2RSTR_TIM1RST           RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos     (4U)
#define RCC_APB2RSTR_USART1RST_Msk     (0x1UL << RCC_APB2RSTR_USART1RST_Pos)   /*!< 0x00000010 */
#define RCC_APB2RSTR_USART1RST         RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos       (12U)
#define RCC_APB2RSTR_SPI1RST_Msk       (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)     /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST           RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_SPI4RST_Pos       (13U)
#define RCC_APB2RSTR_SPI4RST_Msk       (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)     /*!< 0x00002000 */
#define RCC_APB2RSTR_SPI4RST           RCC_APB2RSTR_SPI4RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos      (16U)
#define RCC_APB2RSTR_TIM15RST_Msk      (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)    /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST          RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos      (17U)
#define RCC_APB2RSTR_TIM16RST_Msk      (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)    /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST          RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos      (18U)
#define RCC_APB2RSTR_TIM17RST_Msk      (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)    /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST          RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM9RST_Pos       (19U)
#define RCC_APB2RSTR_TIM9RST_Msk       (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)     /*!< 0x00080000 */
#define RCC_APB2RSTR_TIM9RST           RCC_APB2RSTR_TIM9RST_Msk
#define RCC_APB2RSTR_SPI5RST_Pos       (20U)
#define RCC_APB2RSTR_SPI5RST_Msk       (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)     /*!< 0x00100000 */
#define RCC_APB2RSTR_SPI5RST           RCC_APB2RSTR_SPI5RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos       (22U)
#define RCC_APB2RSTR_SAI1RST_Msk       (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)     /*!< 0x00400000 */
#define RCC_APB2RSTR_SAI1RST           RCC_APB2RSTR_SAI1RST_Msk
#define RCC_APB2RSTR_SAI2RST_Pos       (23U)
#define RCC_APB2RSTR_SAI2RST_Msk       (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)     /*!< 0x00800000 */
#define RCC_APB2RSTR_SAI2RST           RCC_APB2RSTR_SAI2RST_Msk

/********************  Bit definition for RCC_APB4RSTR register  **************/
#define RCC_APB4RSTR_SBSRST_Pos        (1U)
#define RCC_APB4RSTR_SBSRST_Msk        (0x1UL << RCC_APB4RSTR_SBSRST_Pos)      /*!< 0x00000002 */
#define RCC_APB4RSTR_SBSRST            RCC_APB4RSTR_SBSRST_Msk
#define RCC_APB4RSTR_LPUART1RST_Pos    (3U)
#define RCC_APB4RSTR_LPUART1RST_Msk    (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)  /*!< 0x00000008 */
#define RCC_APB4RSTR_LPUART1RST        RCC_APB4RSTR_LPUART1RST_Msk
#define RCC_APB4RSTR_SPI6RST_Pos       (5U)
#define RCC_APB4RSTR_SPI6RST_Msk       (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)     /*!< 0x00000020 */
#define RCC_APB4RSTR_SPI6RST           RCC_APB4RSTR_SPI6RST_Msk
#define RCC_APB4RSTR_LPTIM2RST_Pos     (9U)
#define RCC_APB4RSTR_LPTIM2RST_Msk     (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)   /*!< 0x00000200 */
#define RCC_APB4RSTR_LPTIM2RST         RCC_APB4RSTR_LPTIM2RST_Msk
#define RCC_APB4RSTR_LPTIM3RST_Pos     (10U)
#define RCC_APB4RSTR_LPTIM3RST_Msk     (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)   /*!< 0x00000400 */
#define RCC_APB4RSTR_LPTIM3RST         RCC_APB4RSTR_LPTIM3RST_Msk
#define RCC_APB4RSTR_LPTIM4RST_Pos     (11U)
#define RCC_APB4RSTR_LPTIM4RST_Msk     (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)   /*!< 0x00000800 */
#define RCC_APB4RSTR_LPTIM4RST         RCC_APB4RSTR_LPTIM4RST_Msk
#define RCC_APB4RSTR_LPTIM5RST_Pos     (12U)
#define RCC_APB4RSTR_LPTIM5RST_Msk     (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)   /*!< 0x00001000 */
#define RCC_APB4RSTR_LPTIM5RST         RCC_APB4RSTR_LPTIM5RST_Msk
#define RCC_APB4RSTR_VREFRST_Pos       (15U)
#define RCC_APB4RSTR_VREFRST_Msk       (0x1UL << RCC_APB4RSTR_VREFRST_Pos)     /*!< 0x00008000 */
#define RCC_APB4RSTR_VREFRST           RCC_APB4RSTR_VREFRST_Msk
#define RCC_APB4RSTR_DTSRST_Pos        (26U)
#define RCC_APB4RSTR_DTSRST_Msk        (0x1UL << RCC_APB4RSTR_DTSRST_Pos)      /*!< 0x04000000 */
#define RCC_APB4RSTR_DTSRST            RCC_APB4RSTR_DTSRST_Msk

/********************  Bit definition for RCC_APB5RSTR register  **************/
#define RCC_APB5RSTR_DCMIPPRST_Pos     (2U)
#define RCC_APB5RSTR_DCMIPPRST_Msk     (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos)   /*!< 0x00000004 */
#define RCC_APB5RSTR_DCMIPPRST         RCC_APB5RSTR_DCMIPPRST_Msk
#define RCC_APB5RSTR_GFXTIMRST_Pos     (4U)
#define RCC_APB5RSTR_GFXTIMRST_Msk     (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos)   /*!< 0x00000010 */
#define RCC_APB5RSTR_GFXTIMRST         RCC_APB5RSTR_GFXTIMRST_Msk

/********************  Bit definition for RCC_CKGDISR register  ***************/
#define RCC_CKGDISR_AXICKG_Pos         (0U)
#define RCC_CKGDISR_AXICKG_Msk         (0x1UL << RCC_CKGDISR_AXICKG_Pos)       /*!< 0x00000001 */
#define RCC_CKGDISR_AXICKG             RCC_CKGDISR_AXICKG_Msk
#define RCC_CKGDISR_AHBMCKG_Pos        (1U)
#define RCC_CKGDISR_AHBMCKG_Msk        (0x1UL << RCC_CKGDISR_AHBMCKG_Pos)      /*!< 0x00000002 */
#define RCC_CKGDISR_AHBMCKG            RCC_CKGDISR_AHBMCKG_Msk
#define RCC_CKGDISR_SDMMC1CKG_Pos      (2U)
#define RCC_CKGDISR_SDMMC1CKG_Msk      (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos)    /*!< 0x00000004 */
#define RCC_CKGDISR_SDMMC1CKG           RCC_CKGDISR_SDMMC1CKG_Msk
#define RCC_CKGDISR_HPDMA1CKG_Pos      (3U)
#define RCC_CKGDISR_HPDMA1CKG_Msk      (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos)    /*!< 0x00000008 */
#define RCC_CKGDISR_HPDMA1CKG          RCC_CKGDISR_HPDMA1CKG_Msk
#define RCC_CKGDISR_CPUCKG_Pos         (4U)
#define RCC_CKGDISR_CPUCKG_Msk         (0x1UL << RCC_CKGDISR_CPUCKG_Pos)       /*!< 0x00000010 */
#define RCC_CKGDISR_CPUCKG             RCC_CKGDISR_CPUCKG_Msk
#define RCC_CKGDISR_DCMIPPCKG_Pos      (8U)
#define RCC_CKGDISR_DCMIPPCKG_Msk      (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos)    /*!< 0x00000100 */
#define RCC_CKGDISR_DCMIPPCKG          RCC_CKGDISR_DCMIPPCKG_Msk
#define RCC_CKGDISR_DMA2DCKG_Pos       (9U)
#define RCC_CKGDISR_DMA2DCKG_Msk       (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos)     /*!< 0x00000200 */
#define RCC_CKGDISR_DMA2DCKG           RCC_CKGDISR_DMA2DCKG_Msk
#define RCC_CKGDISR_GFXMMUSCKG_Pos     (10U)
#define RCC_CKGDISR_GFXMMUSCKG_Msk     (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos)   /*!< 0x00000400 */
#define RCC_CKGDISR_GFXMMUSCKG         RCC_CKGDISR_GFXMMUSCKG_Msk
#define RCC_CKGDISR_GFXMMUMCKG_Pos     (12U)
#define RCC_CKGDISR_GFXMMUMCKG_Msk     (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos)   /*!< 0x00001000 */
#define RCC_CKGDISR_GFXMMUMCKG         RCC_CKGDISR_GFXMMUMCKG_Msk
#define RCC_CKGDISR_AHBSCKG_Pos        (13U)
#define RCC_CKGDISR_AHBSCKG_Msk        (0x1UL << RCC_CKGDISR_AHBSCKG_Pos)      /*!< 0x00002000 */
#define RCC_CKGDISR_AHBSCKG            RCC_CKGDISR_AHBSCKG_Msk
#define RCC_CKGDISR_FMCCKG_Pos         (14U)
#define RCC_CKGDISR_FMCCKG_Msk         (0x1UL << RCC_CKGDISR_FMCCKG_Pos)       /*!< 0x00004000 */
#define RCC_CKGDISR_FMCCKG             RCC_CKGDISR_FMCCKG_Msk
#define RCC_CKGDISR_XSPI1CKG_Pos       (15U)
#define RCC_CKGDISR_XSPI1CKG_Msk       (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos)     /*!< 0x00008000 */
#define RCC_CKGDISR_XSPI1CKG           RCC_CKGDISR_XSPI1CKG_Msk
#define RCC_CKGDISR_XSPI2CKG_Pos       (16U)
#define RCC_CKGDISR_XSPI2CKG_Msk       (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos)     /*!< 0x00010000 */
#define RCC_CKGDISR_XSPI2CKG           RCC_CKGDISR_XSPI2CKG_Msk
#define RCC_CKGDISR_AXISRAM4CKG_Pos    (17U)
#define RCC_CKGDISR_AXISRAM4CKG_Msk    (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos)  /*!< 0x00020000 */
#define RCC_CKGDISR_AXISRAM4CKG        RCC_CKGDISR_AXISRAM4CKG_Msk
#define RCC_CKGDISR_AXISRAM3CKG_Pos    (18U)
#define RCC_CKGDISR_AXISRAM3CKG_Msk    (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos)  /*!< 0x00040000 */
#define RCC_CKGDISR_AXISRAM3CKG        RCC_CKGDISR_AXISRAM3CKG_Msk
#define RCC_CKGDISR_AXISRAM2CKG_Pos    (19U)
#define RCC_CKGDISR_AXISRAM2CKG_Msk    (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos)  /*!< 0x00080000 */
#define RCC_CKGDISR_AXISRAM2CKG        RCC_CKGDISR_AXISRAM2CKG_Msk
#define RCC_CKGDISR_AXISRAM1CKG_Pos    (20U)
#define RCC_CKGDISR_AXISRAM1CKG_Msk    (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos)  /*!< 0x00100000 */
#define RCC_CKGDISR_AXISRAM1CKG        RCC_CKGDISR_AXISRAM1CKG_Msk
#define RCC_CKGDISR_FLASHCKG_Pos       (21U)
#define RCC_CKGDISR_FLASHCKG_Msk       (0x1UL << RCC_CKGDISR_FLASHCKG_Pos)     /*!< 0x00200000 */
#define RCC_CKGDISR_FLASHCKG           RCC_CKGDISR_FLASHCKG_Msk
#define RCC_CKGDISR_EXTICKG_Pos        (30U)
#define RCC_CKGDISR_EXTICKG_Msk        (0x1UL << RCC_CKGDISR_EXTICKG_Pos)      /*!< 0x40000000 */
#define RCC_CKGDISR_EXTICKG            RCC_CKGDISR_EXTICKG_Msk
#define RCC_CKGDISR_JTAGCKG_Pos        (31U)
#define RCC_CKGDISR_JTAGCKG_Msk        (0x1UL << RCC_CKGDISR_JTAGCKG_Pos)      /*!< 0x80000000 */
#define RCC_CKGDISR_JTAGCKG            RCC_CKGDISR_JTAGCKG_Msk

/********************  Bit definition for RCC_PLL1DIVR2 register  *************/
#define RCC_PLL1DIVR2_DIVS_Pos        (0U)
#define RCC_PLL1DIVR2_DIVS_Msk        (0x7UL << RCC_PLL1DIVR2_DIVS_Pos)      /*!< 0x00000007 */
#define RCC_PLL1DIVR2_DIVS            RCC_PLL1DIVR2_DIVS_Msk                 /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */
#define RCC_PLL1DIVR2_DIVS_0          (0x1UL << RCC_PLL1DIVR2_DIVS_Pos)      /*!< 0x00000001 */
#define RCC_PLL1DIVR2_DIVS_1          (0x2UL << RCC_PLL1DIVR2_DIVS_Pos)      /*!< 0x00000002 */
#define RCC_PLL1DIVR2_DIVS_2          (0x4UL << RCC_PLL1DIVR2_DIVS_Pos)      /*!< 0x00000004 */

/********************  Bit definition for RCC_PLL2DIVR2 register  *************/
#define RCC_PLL2DIVR2_DIVS_Pos        (0U)
#define RCC_PLL2DIVR2_DIVS_Msk        (0x7UL << RCC_PLL2DIVR2_DIVS_Pos)      /*!< 0x00000007 */
#define RCC_PLL2DIVR2_DIVS            RCC_PLL2DIVR2_DIVS_Msk                 /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */
#define RCC_PLL2DIVR2_DIVS_0          (0x1UL << RCC_PLL2DIVR2_DIVS_Pos)      /*!< 0x00000001 */
#define RCC_PLL2DIVR2_DIVS_1          (0x2UL << RCC_PLL2DIVR2_DIVS_Pos)      /*!< 0x00000002 */
#define RCC_PLL2DIVR2_DIVS_2          (0x4UL << RCC_PLL2DIVR2_DIVS_Pos)      /*!< 0x00000004 */

#define RCC_PLL2DIVR2_DIVT_Pos        (8U)
#define RCC_PLL2DIVR2_DIVT_Msk        (0x7UL << RCC_PLL2DIVR2_DIVT_Pos)      /*!< 0x00000700 */
#define RCC_PLL2DIVR2_DIVT            RCC_PLL2DIVR2_DIVT_Msk                 /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */
#define RCC_PLL2DIVR2_DIVT_0          (0x1UL << RCC_PLL2DIVR2_DIVT_Pos)      /*!< 0x00000100 */
#define RCC_PLL2DIVR2_DIVT_1          (0x2UL << RCC_PLL2DIVR2_DIVT_Pos)      /*!< 0x00000200 */
#define RCC_PLL2DIVR2_DIVT_2          (0x4UL << RCC_PLL2DIVR2_DIVT_Pos)      /*!< 0x00000400 */

/********************  Bit definition for RCC_PLL3DIVR2 register  *************/
#define RCC_PLL3DIVR2_DIVS_Pos        (0U)
#define RCC_PLL3DIVR2_DIVS_Msk        (0x7UL << RCC_PLL3DIVR2_DIVS_Pos)      /*!< 0x00000007 */
#define RCC_PLL3DIVR2_DIVS            RCC_PLL3DIVR2_DIVS_Msk                 /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */
#define RCC_PLL3DIVR2_DIVS_0          (0x1UL << RCC_PLL3DIVR2_DIVS_Pos)      /*!< 0x00000001 */
#define RCC_PLL3DIVR2_DIVS_1          (0x2UL << RCC_PLL3DIVR2_DIVS_Pos)      /*!< 0x00000002 */
#define RCC_PLL3DIVR2_DIVS_2          (0x4UL << RCC_PLL3DIVR2_DIVS_Pos)      /*!< 0x00000004 */

/********************  Bit definition for RCC_PLL1SSCGR register  *************/
#define RCC_PLL1SSCGR_MODPER_Pos      (0U)
#define RCC_PLL1SSCGR_MODPER_Msk      (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00001FFF */
#define RCC_PLL1SSCGR_MODPER          RCC_PLL1SSCGR_MODPER_Msk                /*!< MODPER[12:0] bits: Modulation Period Adjustment */
#define RCC_PLL1SSCGR_MODPER_0        (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000001 */
#define RCC_PLL1SSCGR_MODPER_1        (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000002 */
#define RCC_PLL1SSCGR_MODPER_2        (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000004 */
#define RCC_PLL1SSCGR_MODPER_3        (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000008 */
#define RCC_PLL1SSCGR_MODPER_4        (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000010 */
#define RCC_PLL1SSCGR_MODPER_5        (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000020 */
#define RCC_PLL1SSCGR_MODPER_6        (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000040 */
#define RCC_PLL1SSCGR_MODPER_7        (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000080 */
#define RCC_PLL1SSCGR_MODPER_8        (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000100 */
#define RCC_PLL1SSCGR_MODPER_9        (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000200 */
#define RCC_PLL1SSCGR_MODPER_10       (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000400 */
#define RCC_PLL1SSCGR_MODPER_11       (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00000800 */
#define RCC_PLL1SSCGR_MODPER_12       (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos)  /*!< 0x00001000 */
#define RCC_PLL1SSCGR_TPDFNDIS_Pos    (13U)
#define RCC_PLL1SSCGR_TPDFNDIS_Msk    (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos)   /*!< 0x00002000 */
#define RCC_PLL1SSCGR_TPDFNDIS        RCC_PLL1SSCGR_TPDFNDIS_Msk
#define RCC_PLL1SSCGR_RPDFNDIS_Pos    (14U)
#define RCC_PLL1SSCGR_RPDFNDIS_Msk    (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos)   /*!< 0x00004000 */
#define RCC_PLL1SSCGR_RPDFNDIS        RCC_PLL1SSCGR_RPDFNDIS_Msk
#define RCC_PLL1SSCGR_SPREADSEL_Pos   (15U)
#define RCC_PLL1SSCGR_SPREADSEL_Msk   (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos)  /*!< 0x00008000 */
#define RCC_PLL1SSCGR_SPREADSEL       RCC_PLL1SSCGR_SPREADSEL_Msk
#define RCC_PLL1SSCGR_INCSTEP_Pos     (16U)
#define RCC_PLL1SSCGR_INCSTEP_Msk     (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL1SSCGR_INCSTEP         RCC_PLL1SSCGR_INCSTEP_Msk               /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */
#define RCC_PLL1SSCGR_INCSTEP_0       (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */
#define RCC_PLL1SSCGR_INCSTEP_1       (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */
#define RCC_PLL1SSCGR_INCSTEP_2       (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */
#define RCC_PLL1SSCGR_INCSTEP_3       (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */
#define RCC_PLL1SSCGR_INCSTEP_4       (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */
#define RCC_PLL1SSCGR_INCSTEP_5       (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */
#define RCC_PLL1SSCGR_INCSTEP_6       (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */
#define RCC_PLL1SSCGR_INCSTEP_7       (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */
#define RCC_PLL1SSCGR_INCSTEP_8       (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */
#define RCC_PLL1SSCGR_INCSTEP_9       (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */
#define RCC_PLL1SSCGR_INCSTEP_10      (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */
#define RCC_PLL1SSCGR_INCSTEP_11      (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */
#define RCC_PLL1SSCGR_INCSTEP_12      (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */
#define RCC_PLL1SSCGR_INCSTEP_13      (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */
#define RCC_PLL1SSCGR_INCSTEP_14      (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */

/********************  Bit definition for RCC_PLL2SSCGR register  *************/
#define RCC_PLL2SSCGR_MODPER_Pos      (0U)
#define RCC_PLL2SSCGR_MODPER_Msk      (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00001FFF */
#define RCC_PLL2SSCGR_MODPER          RCC_PLL2SSCGR_MODPER_Msk                /*!< MODPER[12:0] bits: Modulation Period Adjustment */
#define RCC_PLL2SSCGR_MODPER_0        (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000001 */
#define RCC_PLL2SSCGR_MODPER_1        (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000002 */
#define RCC_PLL2SSCGR_MODPER_2        (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000004 */
#define RCC_PLL2SSCGR_MODPER_3        (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000008 */
#define RCC_PLL2SSCGR_MODPER_4        (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000010 */
#define RCC_PLL2SSCGR_MODPER_5        (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000020 */
#define RCC_PLL2SSCGR_MODPER_6        (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000040 */
#define RCC_PLL2SSCGR_MODPER_7        (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000080 */
#define RCC_PLL2SSCGR_MODPER_8        (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000100 */
#define RCC_PLL2SSCGR_MODPER_9        (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000200 */
#define RCC_PLL2SSCGR_MODPER_10       (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000400 */
#define RCC_PLL2SSCGR_MODPER_11       (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00000800 */
#define RCC_PLL2SSCGR_MODPER_12       (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos)  /*!< 0x00001000 */
#define RCC_PLL2SSCGR_TPDFNDIS_Pos    (13U)
#define RCC_PLL2SSCGR_TPDFNDIS_Msk    (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos)   /*!< 0x00002000 */
#define RCC_PLL2SSCGR_TPDFNDIS        RCC_PLL2SSCGR_TPDFNDIS_Msk
#define RCC_PLL2SSCGR_RPDFNDIS_Pos    (14U)
#define RCC_PLL2SSCGR_RPDFNDIS_Msk    (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos)   /*!< 0x00004000 */
#define RCC_PLL2SSCGR_RPDFNDIS        RCC_PLL2SSCGR_RPDFNDIS_Msk
#define RCC_PLL2SSCGR_SPREADSEL_Pos   (15U)
#define RCC_PLL2SSCGR_SPREADSEL_Msk   (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos)  /*!< 0x00008000 */
#define RCC_PLL2SSCGR_SPREADSEL       RCC_PLL2SSCGR_SPREADSEL_Msk
#define RCC_PLL2SSCGR_INCSTEP_Pos     (16U)
#define RCC_PLL2SSCGR_INCSTEP_Msk     (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL2SSCGR_INCSTEP         RCC_PLL2SSCGR_INCSTEP_Msk               /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */
#define RCC_PLL2SSCGR_INCSTEP_0       (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */
#define RCC_PLL2SSCGR_INCSTEP_1       (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */
#define RCC_PLL2SSCGR_INCSTEP_2       (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */
#define RCC_PLL2SSCGR_INCSTEP_3       (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */
#define RCC_PLL2SSCGR_INCSTEP_4       (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */
#define RCC_PLL2SSCGR_INCSTEP_5       (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */
#define RCC_PLL2SSCGR_INCSTEP_6       (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */
#define RCC_PLL2SSCGR_INCSTEP_7       (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */
#define RCC_PLL2SSCGR_INCSTEP_8       (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */
#define RCC_PLL2SSCGR_INCSTEP_9       (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */
#define RCC_PLL2SSCGR_INCSTEP_10      (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */
#define RCC_PLL2SSCGR_INCSTEP_11      (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */
#define RCC_PLL2SSCGR_INCSTEP_12      (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */
#define RCC_PLL2SSCGR_INCSTEP_13      (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */
#define RCC_PLL2SSCGR_INCSTEP_14      (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */

/********************  Bit definition for RCC_PLL3SSCGR register  *************/
#define RCC_PLL3SSCGR_MODPER_Pos      (0U)
#define RCC_PLL3SSCGR_MODPER_Msk      (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00001FFF */
#define RCC_PLL3SSCGR_MODPER          RCC_PLL3SSCGR_MODPER_Msk                /*!< MODPER[12:0] bits: Modulation Period Adjustment */
#define RCC_PLL3SSCGR_MODPER_0        (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000001 */
#define RCC_PLL3SSCGR_MODPER_1        (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000002 */
#define RCC_PLL3SSCGR_MODPER_2        (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000004 */
#define RCC_PLL3SSCGR_MODPER_3        (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000008 */
#define RCC_PLL3SSCGR_MODPER_4        (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000010 */
#define RCC_PLL3SSCGR_MODPER_5        (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000020 */
#define RCC_PLL3SSCGR_MODPER_6        (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000040 */
#define RCC_PLL3SSCGR_MODPER_7        (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000080 */
#define RCC_PLL3SSCGR_MODPER_8        (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000100 */
#define RCC_PLL3SSCGR_MODPER_9        (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000200 */
#define RCC_PLL3SSCGR_MODPER_10       (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000400 */
#define RCC_PLL3SSCGR_MODPER_11       (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00000800 */
#define RCC_PLL3SSCGR_MODPER_12       (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos)  /*!< 0x00001000 */
#define RCC_PLL3SSCGR_TPDFNDIS_Pos    (13U)
#define RCC_PLL3SSCGR_TPDFNDIS_Msk    (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos)   /*!< 0x00002000 */
#define RCC_PLL3SSCGR_TPDFNDIS        RCC_PLL3SSCGR_TPDFNDIS_Msk
#define RCC_PLL3SSCGR_RPDFNDIS_Pos    (14U)
#define RCC_PLL3SSCGR_RPDFNDIS_Msk    (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos)   /*!< 0x00004000 */
#define RCC_PLL3SSCGR_RPDFNDIS        RCC_PLL3SSCGR_RPDFNDIS_Msk
#define RCC_PLL3SSCGR_SPREADSEL_Pos   (15U)
#define RCC_PLL3SSCGR_SPREADSEL_Msk   (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos)  /*!< 0x00008000 */
#define RCC_PLL3SSCGR_SPREADSEL       RCC_PLL3SSCGR_SPREADSEL_Msk
#define RCC_PLL3SSCGR_INCSTEP_Pos     (16U)
#define RCC_PLL3SSCGR_INCSTEP_Msk     (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL3SSCGR_INCSTEP         RCC_PLL3SSCGR_INCSTEP_Msk               /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */
#define RCC_PLL3SSCGR_INCSTEP_0       (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */
#define RCC_PLL3SSCGR_INCSTEP_1       (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */
#define RCC_PLL3SSCGR_INCSTEP_2       (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */
#define RCC_PLL3SSCGR_INCSTEP_3       (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */
#define RCC_PLL3SSCGR_INCSTEP_4       (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */
#define RCC_PLL3SSCGR_INCSTEP_5       (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */
#define RCC_PLL3SSCGR_INCSTEP_6       (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */
#define RCC_PLL3SSCGR_INCSTEP_7       (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */
#define RCC_PLL3SSCGR_INCSTEP_8       (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */
#define RCC_PLL3SSCGR_INCSTEP_9       (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */
#define RCC_PLL3SSCGR_INCSTEP_10      (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */
#define RCC_PLL3SSCGR_INCSTEP_11      (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */
#define RCC_PLL3SSCGR_INCSTEP_12      (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */
#define RCC_PLL3SSCGR_INCSTEP_13      (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */
#define RCC_PLL3SSCGR_INCSTEP_14      (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */

/********************  Bit definition for RCC_CKPROTR register  ***************/
#define RCC_CKPROTR_XSPICKP_Pos        (0U)
#define RCC_CKPROTR_XSPICKP_Msk        (0x1UL << RCC_CKPROTR_XSPICKP_Pos)      /*!< 0x00000001 */
#define RCC_CKPROTR_XSPICKP            RCC_CKPROTR_XSPICKP_Msk
#define RCC_CKPROTR_FMCCKP_Pos         (1U)
#define RCC_CKPROTR_FMCCKP_Msk         (0x1UL << RCC_CKPROTR_FMCCKP_Pos)       /*!< 0x00000002 */
#define RCC_CKPROTR_FMCCKP             RCC_CKPROTR_FMCCKP_Msk
#define RCC_CKPROTR_XSPI1SWP_Pos       (4U)
#define RCC_CKPROTR_XSPI1SWP_Msk       (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos)     /*!< 0x00000070 */
#define RCC_CKPROTR_XSPI1SWP           RCC_CKPROTR_XSPI1SWP_Msk
#define RCC_CKPROTR_XSPI1SWP_0         (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos)     /*!< 0x00000010 */
#define RCC_CKPROTR_XSPI1SWP_1         (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos)     /*!< 0x00000020 */
#define RCC_CKPROTR_XSPI1SWP_2         (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos)     /*!< 0x00000040 */
#define RCC_CKPROTR_XSPI2SWP_Pos       (8U)
#define RCC_CKPROTR_XSPI2SWP_Msk       (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos)     /*!< 0x00000700 */
#define RCC_CKPROTR_XSPI2SWP           RCC_CKPROTR_XSPI2SWP_Msk
#define RCC_CKPROTR_XSPI2SWP_0         (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos)     /*!< 0x00000100 */
#define RCC_CKPROTR_XSPI2SWP_1         (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos)     /*!< 0x00000200 */
#define RCC_CKPROTR_XSPI2SWP_2         (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos)     /*!< 0x00000400 */
#define RCC_CKPROTR_FMCSWP_Pos         (12U)
#define RCC_CKPROTR_FMCSWP_Msk         (0x7UL << RCC_CKPROTR_FMCSWP_Pos)       /*!< 0x00007000 */
#define RCC_CKPROTR_FMCSWP             RCC_CKPROTR_FMCSWP_Msk
#define RCC_CKPROTR_FMCSWP_0           (0x1UL << RCC_CKPROTR_FMCSWP_Pos)       /*!< 0x00001000 */
#define RCC_CKPROTR_FMCSWP_1           (0x2UL << RCC_CKPROTR_FMCSWP_Pos)       /*!< 0x00002000 */
#define RCC_CKPROTR_FMCSWP_2           (0x4UL << RCC_CKPROTR_FMCSWP_Pos)       /*!< 0x00004000 */

/********************  Bit definition for RCC_RSR register  *******************/
#define RCC_RSR_RMVF_Pos               (16U)
#define RCC_RSR_RMVF_Msk               (0x1UL << RCC_RSR_RMVF_Pos)             /*!< 0x00010000 */
#define RCC_RSR_RMVF                   RCC_RSR_RMVF_Msk
#define RCC_RSR_OBLRSTF_Pos            (17U)
#define RCC_RSR_OBLRSTF_Msk            (0x1UL << RCC_RSR_OBLRSTF_Pos)          /*!< 0x00020000 */
#define RCC_RSR_OBLRSTF                RCC_RSR_OBLRSTF_Msk
#define RCC_RSR_BORRSTF_Pos            (21U)
#define RCC_RSR_BORRSTF_Msk            (0x1UL << RCC_RSR_BORRSTF_Pos)          /*!< 0x00200000 */
#define RCC_RSR_BORRSTF                RCC_RSR_BORRSTF_Msk
#define RCC_RSR_PINRSTF_Pos            (22U)
#define RCC_RSR_PINRSTF_Msk            (0x1UL << RCC_RSR_PINRSTF_Pos)          /*!< 0x00400000 */
#define RCC_RSR_PINRSTF                RCC_RSR_PINRSTF_Msk
#define RCC_RSR_PORRSTF_Pos            (23U)
#define RCC_RSR_PORRSTF_Msk            (0x1UL << RCC_RSR_PORRSTF_Pos)          /*!< 0x00800000 */
#define RCC_RSR_PORRSTF                RCC_RSR_PORRSTF_Msk
#define RCC_RSR_SFTRSTF_Pos            (24U)
#define RCC_RSR_SFTRSTF_Msk            (0x1UL << RCC_RSR_SFTRSTF_Pos)          /*!< 0x01000000 */
#define RCC_RSR_SFTRSTF                RCC_RSR_SFTRSTF_Msk
#define RCC_RSR_IWDGRSTF_Pos           (26U)
#define RCC_RSR_IWDGRSTF_Msk           (0x1UL << RCC_RSR_IWDGRSTF_Pos)         /*!< 0x04000000 */
#define RCC_RSR_IWDGRSTF               RCC_RSR_IWDGRSTF_Msk
#define RCC_RSR_WWDGRSTF_Pos           (28U)
#define RCC_RSR_WWDGRSTF_Msk           (0x1UL << RCC_RSR_WWDGRSTF_Pos)         /*!< 0x10000000 */
#define RCC_RSR_WWDGRSTF               RCC_RSR_WWDGRSTF_Msk
#define RCC_RSR_LPWRRSTF_Pos           (30U)
#define RCC_RSR_LPWRRSTF_Msk           (0x1UL << RCC_RSR_LPWRRSTF_Pos)         /*!< 0x40000000 */
#define RCC_RSR_LPWRRSTF               RCC_RSR_LPWRRSTF_Msk

/********************  Bit definition for RCC_AHB1ENR register  ***************/
#define RCC_AHB1ENR_GPDMA1EN_Pos       (4U)
#define RCC_AHB1ENR_GPDMA1EN_Msk       (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)     /*!< 0x00000010 */
#define RCC_AHB1ENR_GPDMA1EN           RCC_AHB1ENR_GPDMA1EN_Msk
#define RCC_AHB1ENR_ADC12EN_Pos        (5U)
#define RCC_AHB1ENR_ADC12EN_Msk        (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)      /*!< 0x00000020 */
#define RCC_AHB1ENR_ADC12EN            RCC_AHB1ENR_ADC12EN_Msk
#define RCC_AHB1ENR_ETH1MACEN_Pos      (15U)
#define RCC_AHB1ENR_ETH1MACEN_Msk      (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)    /*!< 0x00008000 */
#define RCC_AHB1ENR_ETH1MACEN          RCC_AHB1ENR_ETH1MACEN_Msk
#define RCC_AHB1ENR_ETH1TXEN_Pos       (16U)
#define RCC_AHB1ENR_ETH1TXEN_Msk       (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)     /*!< 0x00010000 */
#define RCC_AHB1ENR_ETH1TXEN           RCC_AHB1ENR_ETH1TXEN_Msk
#define RCC_AHB1ENR_ETH1RXEN_Pos       (17U)
#define RCC_AHB1ENR_ETH1RXEN_Msk       (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)     /*!< 0x00020000 */
#define RCC_AHB1ENR_ETH1RXEN           RCC_AHB1ENR_ETH1RXEN_Msk
#define RCC_AHB1ENR_OTGHSEN_Pos        (25U)
#define RCC_AHB1ENR_OTGHSEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)      /*!< 0x02000000 */
#define RCC_AHB1ENR_OTGHSEN            RCC_AHB1ENR_OTGHSEN_Msk
#define RCC_AHB1ENR_USBPHYCEN_Pos      (26U)
#define RCC_AHB1ENR_USBPHYCEN_Msk      (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos)    /*!< 0x04000000 */
#define RCC_AHB1ENR_USBPHYCEN          RCC_AHB1ENR_USBPHYCEN_Msk
#define RCC_AHB1ENR_OTGFSEN_Pos        (27U)
#define RCC_AHB1ENR_OTGFSEN_Msk        (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos)      /*!< 0x08000000 */
#define RCC_AHB1ENR_OTGFSEN            RCC_AHB1ENR_OTGFSEN_Msk
#define RCC_AHB1ENR_ADF1EN_Pos         (31U)
#define RCC_AHB1ENR_ADF1EN_Msk         (0x1UL << RCC_AHB1ENR_ADF1EN_Pos)       /*!< 0x80000000 */
#define RCC_AHB1ENR_ADF1EN             RCC_AHB1ENR_ADF1EN_Msk

/********************  Bit definition for RCC_AHB2ENR register  ***************/
#define RCC_AHB2ENR_PSSIEN_Pos         (1U)
#define RCC_AHB2ENR_PSSIEN_Msk         (0x1UL << RCC_AHB2ENR_PSSIEN_Pos)       /*!< 0x00000002 */
#define RCC_AHB2ENR_PSSIEN             RCC_AHB2ENR_PSSIEN_Msk
#define RCC_AHB2ENR_SDMMC2EN_Pos       (9U)
#define RCC_AHB2ENR_SDMMC2EN_Msk       (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)     /*!< 0x00000200 */
#define RCC_AHB2ENR_SDMMC2EN           RCC_AHB2ENR_SDMMC2EN_Msk
#define RCC_AHB2ENR_CORDICEN_Pos       (14U)
#define RCC_AHB2ENR_CORDICEN_Msk       (0x1UL << RCC_AHB2ENR_CORDICEN_Pos)     /*!< 0x00004000 */
#define RCC_AHB2ENR_CORDICEN           RCC_AHB2ENR_CORDICEN_Msk
#define RCC_AHB2ENR_SRAM1EN_Pos        (29U)
#define RCC_AHB2ENR_SRAM1EN_Msk        (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)      /*!< 0x20000000 */
#define RCC_AHB2ENR_SRAM1EN            RCC_AHB2ENR_SRAM1EN_Msk
#define RCC_AHB2ENR_SRAM2EN_Pos        (30U)
#define RCC_AHB2ENR_SRAM2EN_Msk        (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)      /*!< 0x40000000 */
#define RCC_AHB2ENR_SRAM2EN            RCC_AHB2ENR_SRAM2EN_Msk

/********************  Bit definition for RCC_AHB3ENR register  ***************/
#define RCC_AHB3ENR_RNGEN_Pos          (0U)
#define RCC_AHB3ENR_RNGEN_Msk          (0x1UL << RCC_AHB3ENR_RNGEN_Pos)        /*!< 0x00000001 */
#define RCC_AHB3ENR_RNGEN              RCC_AHB3ENR_RNGEN_Msk
#define RCC_AHB3ENR_HASHEN_Pos         (1U)
#define RCC_AHB3ENR_HASHEN_Msk         (0x1UL << RCC_AHB3ENR_HASHEN_Pos)       /*!< 0x00000002 */
#define RCC_AHB3ENR_HASHEN             RCC_AHB3ENR_HASHEN_Msk
#define RCC_AHB3ENR_CRYPEN_Pos         (2U)
#define RCC_AHB3ENR_CRYPEN_Msk         (0x1UL << RCC_AHB3ENR_CRYPEN_Pos)       /*!< 0x00000004 */
#define RCC_AHB3ENR_CRYPEN             RCC_AHB3ENR_CRYPEN_Msk
#define RCC_AHB3ENR_SAESEN_Pos         (4U)
#define RCC_AHB3ENR_SAESEN_Msk         (0x1UL << RCC_AHB3ENR_SAESEN_Pos)       /*!< 0x00000010 */
#define RCC_AHB3ENR_SAESEN             RCC_AHB3ENR_SAESEN_Msk
#define RCC_AHB3ENR_PKAEN_Pos          (6U)
#define RCC_AHB3ENR_PKAEN_Msk          (0x1UL << RCC_AHB3ENR_PKAEN_Pos)        /*!< 0x00000040 */
#define RCC_AHB3ENR_PKAEN              RCC_AHB3ENR_PKAEN_Msk

/********************  Bit definition for RCC_AHB4ENR register  ***************/
#define RCC_AHB4ENR_GPIOAEN_Pos        (0U)
#define RCC_AHB4ENR_GPIOAEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)      /*!< 0x00000001 */
#define RCC_AHB4ENR_GPIOAEN            RCC_AHB4ENR_GPIOAEN_Msk
#define RCC_AHB4ENR_GPIOBEN_Pos        (1U)
#define RCC_AHB4ENR_GPIOBEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)      /*!< 0x00000002 */
#define RCC_AHB4ENR_GPIOBEN            RCC_AHB4ENR_GPIOBEN_Msk
#define RCC_AHB4ENR_GPIOCEN_Pos        (2U)
#define RCC_AHB4ENR_GPIOCEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)      /*!< 0x00000004 */
#define RCC_AHB4ENR_GPIOCEN            RCC_AHB4ENR_GPIOCEN_Msk
#define RCC_AHB4ENR_GPIODEN_Pos        (3U)
#define RCC_AHB4ENR_GPIODEN_Msk        (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)      /*!< 0x00000008 */
#define RCC_AHB4ENR_GPIODEN            RCC_AHB4ENR_GPIODEN_Msk
#define RCC_AHB4ENR_GPIOEEN_Pos        (4U)
#define RCC_AHB4ENR_GPIOEEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)      /*!< 0x00000010 */
#define RCC_AHB4ENR_GPIOEEN            RCC_AHB4ENR_GPIOEEN_Msk
#define RCC_AHB4ENR_GPIOFEN_Pos        (5U)
#define RCC_AHB4ENR_GPIOFEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)      /*!< 0x00000020 */
#define RCC_AHB4ENR_GPIOFEN            RCC_AHB4ENR_GPIOFEN_Msk
#define RCC_AHB4ENR_GPIOGEN_Pos        (6U)
#define RCC_AHB4ENR_GPIOGEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)      /*!< 0x00000040 */
#define RCC_AHB4ENR_GPIOGEN            RCC_AHB4ENR_GPIOGEN_Msk
#define RCC_AHB4ENR_GPIOHEN_Pos        (7U)
#define RCC_AHB4ENR_GPIOHEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)      /*!< 0x00000080 */
#define RCC_AHB4ENR_GPIOHEN            RCC_AHB4ENR_GPIOHEN_Msk
#define RCC_AHB4ENR_GPIOMEN_Pos        (12U)
#define RCC_AHB4ENR_GPIOMEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos)      /*!< 0x00001000 */
#define RCC_AHB4ENR_GPIOMEN            RCC_AHB4ENR_GPIOMEN_Msk
#define RCC_AHB4ENR_GPIONEN_Pos        (13U)
#define RCC_AHB4ENR_GPIONEN_Msk        (0x1UL << RCC_AHB4ENR_GPIONEN_Pos)      /*!< 0x00002000 */
#define RCC_AHB4ENR_GPIONEN            RCC_AHB4ENR_GPIONEN_Msk
#define RCC_AHB4ENR_GPIOOEN_Pos        (14U)
#define RCC_AHB4ENR_GPIOOEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos)      /*!< 0x00004000 */
#define RCC_AHB4ENR_GPIOOEN            RCC_AHB4ENR_GPIOOEN_Msk
#define RCC_AHB4ENR_GPIOPEN_Pos        (15U)
#define RCC_AHB4ENR_GPIOPEN_Msk        (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos)      /*!< 0x00008000 */
#define RCC_AHB4ENR_GPIOPEN            RCC_AHB4ENR_GPIOPEN_Msk
#define RCC_AHB4ENR_CRCEN_Pos          (19U)
#define RCC_AHB4ENR_CRCEN_Msk          (0x1UL << RCC_AHB4ENR_CRCEN_Pos)        /*!< 0x00080000 */
#define RCC_AHB4ENR_CRCEN              RCC_AHB4ENR_CRCEN_Msk
#define RCC_AHB4ENR_BKPRAMEN_Pos       (28U)
#define RCC_AHB4ENR_BKPRAMEN_Msk       (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)     /*!< 0x10000000 */
#define RCC_AHB4ENR_BKPRAMEN           RCC_AHB4ENR_BKPRAMEN_Msk

/********************  Bit definition for RCC_AHB5ENR register  ***************/
#define RCC_AHB5ENR_HPDMA1EN_Pos       (0U)
#define RCC_AHB5ENR_HPDMA1EN_Msk       (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos)     /*!< 0x00000001 */
#define RCC_AHB5ENR_HPDMA1EN           RCC_AHB5ENR_HPDMA1EN_Msk
#define RCC_AHB5ENR_DMA2DEN_Pos        (1U)
#define RCC_AHB5ENR_DMA2DEN_Msk        (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos)      /*!< 0x00000002 */
#define RCC_AHB5ENR_DMA2DEN            RCC_AHB5ENR_DMA2DEN_Msk
#define RCC_AHB5ENR_JPEGEN_Pos         (3U)
#define RCC_AHB5ENR_JPEGEN_Msk         (0x1UL << RCC_AHB5ENR_JPEGEN_Pos)       /*!< 0x00000008 */
#define RCC_AHB5ENR_JPEGEN             RCC_AHB5ENR_JPEGEN_Msk
#define RCC_AHB5ENR_FMCEN_Pos          (4U)
#define RCC_AHB5ENR_FMCEN_Msk          (0x1UL << RCC_AHB5ENR_FMCEN_Pos)        /*!< 0x00000010 */
#define RCC_AHB5ENR_FMCEN              RCC_AHB5ENR_FMCEN_Msk
#define RCC_AHB5ENR_XSPI1EN_Pos        (5U)
#define RCC_AHB5ENR_XSPI1EN_Msk        (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos)      /*!< 0x00000020 */
#define RCC_AHB5ENR_XSPI1EN            RCC_AHB5ENR_XSPI1EN_Msk
#define RCC_AHB5ENR_SDMMC1EN_Pos       (8U)
#define RCC_AHB5ENR_SDMMC1EN_Msk       (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos)     /*!< 0x00000100 */
#define RCC_AHB5ENR_SDMMC1EN           RCC_AHB5ENR_SDMMC1EN_Msk
#define RCC_AHB5ENR_XSPI2EN_Pos        (12U)
#define RCC_AHB5ENR_XSPI2EN_Msk        (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos)      /*!< 0x00001000 */
#define RCC_AHB5ENR_XSPI2EN            RCC_AHB5ENR_XSPI2EN_Msk
#define RCC_AHB5ENR_XSPIMEN_Pos        (14U)
#define RCC_AHB5ENR_XSPIMEN_Msk        (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos)     /*!< 0x00004000 */
#define RCC_AHB5ENR_XSPIMEN            RCC_AHB5ENR_XSPIMEN_Msk
#define RCC_AHB5ENR_GFXMMUEN_Pos       (19U)
#define RCC_AHB5ENR_GFXMMUEN_Msk       (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos)     /*!< 0x00080000 */
#define RCC_AHB5ENR_GFXMMUEN           RCC_AHB5ENR_GFXMMUEN_Msk

/********************  Bit definition for RCC_APB1ENR1 register  **************/
#define RCC_APB1ENR1_TIM2EN_Pos        (0U)
#define RCC_APB1ENR1_TIM2EN_Msk        (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)      /*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN            RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos        (1U)
#define RCC_APB1ENR1_TIM3EN_Msk        (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)      /*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN            RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos        (2U)
#define RCC_APB1ENR1_TIM4EN_Msk        (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)      /*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN            RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM5EN_Pos        (3U)
#define RCC_APB1ENR1_TIM5EN_Msk        (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)      /*!< 0x00000008 */
#define RCC_APB1ENR1_TIM5EN            RCC_APB1ENR1_TIM5EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos        (4U)
#define RCC_APB1ENR1_TIM6EN_Msk        (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)      /*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN            RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos        (5U)
#define RCC_APB1ENR1_TIM7EN_Msk        (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)      /*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN            RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_TIM12EN_Pos       (6U)
#define RCC_APB1ENR1_TIM12EN_Msk       (0x1UL << RCC_APB1ENR1_TIM12EN_Pos)     /*!< 0x00000040 */
#define RCC_APB1ENR1_TIM12EN           RCC_APB1ENR1_TIM12EN_Msk
#define RCC_APB1ENR1_TIM13EN_Pos       (7U)
#define RCC_APB1ENR1_TIM13EN_Msk       (0x1UL << RCC_APB1ENR1_TIM13EN_Pos)     /*!< 0x00000080 */
#define RCC_APB1ENR1_TIM13EN           RCC_APB1ENR1_TIM13EN_Msk
#define RCC_APB1ENR1_TIM14EN_Pos       (8U)
#define RCC_APB1ENR1_TIM14EN_Msk       (0x1UL << RCC_APB1ENR1_TIM14EN_Pos)     /*!< 0x00000100 */
#define RCC_APB1ENR1_TIM14EN           RCC_APB1ENR1_TIM14EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos      (9U)
#define RCC_APB1ENR1_LPTIM1EN_Msk      (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)    /*!< 0x00000200 */
#define RCC_APB1ENR1_LPTIM1EN          RCC_APB1ENR1_LPTIM1EN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos        (11U)
#define RCC_APB1ENR1_WWDGEN_Msk        (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)      /*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN            RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos        (14U)
#define RCC_APB1ENR1_SPI2EN_Msk        (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)      /*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN            RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos        (15U)
#define RCC_APB1ENR1_SPI3EN_Msk        (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)      /*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN            RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_SPDIFRXEN_Pos     (16U)
#define RCC_APB1ENR1_SPDIFRXEN_Msk     (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos)   /*!< 0x00010000 */
#define RCC_APB1ENR1_SPDIFRXEN         RCC_APB1ENR1_SPDIFRXEN_Msk
#define RCC_APB1ENR1_USART2EN_Pos      (17U)
#define RCC_APB1ENR1_USART2EN_Msk      (0x1UL << RCC_APB1ENR1_USART2EN_Pos)    /*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN          RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos      (18U)
#define RCC_APB1ENR1_USART3EN_Msk      (0x1UL << RCC_APB1ENR1_USART3EN_Pos)    /*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN          RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos       (19U)
#define RCC_APB1ENR1_UART4EN_Msk       (0x1UL << RCC_APB1ENR1_UART4EN_Pos)     /*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN           RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_UART5EN_Pos       (20U)
#define RCC_APB1ENR1_UART5EN_Msk       (0x1UL << RCC_APB1ENR1_UART5EN_Pos)     /*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN           RCC_APB1ENR1_UART5EN_Msk
#define RCC_APB1ENR1_I2C1_I3C1EN_Pos   (21U)
#define RCC_APB1ENR1_I2C1_I3C1EN_Msk   (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1_I3C1EN       RCC_APB1ENR1_I2C1_I3C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos        (22U)
#define RCC_APB1ENR1_I2C2EN_Msk        (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)      /*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN            RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos        (23U)
#define RCC_APB1ENR1_I2C3EN_Msk        (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)      /*!< 0x00800000 */
#define RCC_APB1ENR1_I2C3EN            RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_CECEN_Pos         (27U)
#define RCC_APB1ENR1_CECEN_Msk         (0x1UL << RCC_APB1ENR1_CECEN_Pos)       /*!< 0x08000000 */
#define RCC_APB1ENR1_CECEN             RCC_APB1ENR1_CECEN_Msk
#define RCC_APB1ENR1_UART7EN_Pos       (30U)
#define RCC_APB1ENR1_UART7EN_Msk       (0x1UL << RCC_APB1ENR1_UART7EN_Pos)     /*!< 0x40000000 */
#define RCC_APB1ENR1_UART7EN           RCC_APB1ENR1_UART7EN_Msk
#define RCC_APB1ENR1_UART8EN_Pos       (31U)
#define RCC_APB1ENR1_UART8EN_Msk       (0x1UL << RCC_APB1ENR1_UART8EN_Pos)     /*!< 0x80000000 */
#define RCC_APB1ENR1_UART8EN           RCC_APB1ENR1_UART8EN_Msk

/********************  Bit definition for RCC_APB1ENR2 register  **************/
#define RCC_APB1ENR2_CRSEN_Pos         (1U)
#define RCC_APB1ENR2_CRSEN_Msk         (0x1UL << RCC_APB1ENR2_CRSEN_Pos)       /*!< 0x00000002 */
#define RCC_APB1ENR2_CRSEN             RCC_APB1ENR2_CRSEN_Msk
#define RCC_APB1ENR2_MDIOSEN_Pos       (5U)
#define RCC_APB1ENR2_MDIOSEN_Msk       (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos)     /*!< 0x00000020 */
#define RCC_APB1ENR2_MDIOSEN           RCC_APB1ENR2_MDIOSEN_Msk
#define RCC_APB1ENR2_FDCANEN_Pos       (8U)
#define RCC_APB1ENR2_FDCANEN_Msk       (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)     /*!< 0x00000100 */
#define RCC_APB1ENR2_FDCANEN           RCC_APB1ENR2_FDCANEN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos       (27U)
#define RCC_APB1ENR2_UCPD1EN_Msk       (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)     /*!< 0x08000000 */
#define RCC_APB1ENR2_UCPD1EN           RCC_APB1ENR2_UCPD1EN_Msk

/********************  Bit definition for RCC_APB2ENR register  ***************/
#define RCC_APB2ENR_TIM1EN_Pos         (0U)
#define RCC_APB2ENR_TIM1EN_Msk         (0x1UL << RCC_APB2ENR_TIM1EN_Pos)       /*!< 0x00000001 */
#define RCC_APB2ENR_TIM1EN             RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_USART1EN_Pos       (4U)
#define RCC_APB2ENR_USART1EN_Msk       (0x1UL << RCC_APB2ENR_USART1EN_Pos)     /*!< 0x00000010 */
#define RCC_APB2ENR_USART1EN           RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos         (12U)
#define RCC_APB2ENR_SPI1EN_Msk         (0x1UL << RCC_APB2ENR_SPI1EN_Pos)       /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN             RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_SPI4EN_Pos         (13U)
#define RCC_APB2ENR_SPI4EN_Msk         (0x1UL << RCC_APB2ENR_SPI4EN_Pos)       /*!< 0x00002000 */
#define RCC_APB2ENR_SPI4EN             RCC_APB2ENR_SPI4EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos        (16U)
#define RCC_APB2ENR_TIM15EN_Msk        (0x1UL << RCC_APB2ENR_TIM15EN_Pos)      /*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN            RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos        (17U)
#define RCC_APB2ENR_TIM16EN_Msk        (0x1UL << RCC_APB2ENR_TIM16EN_Pos)      /*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN            RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos        (18U)
#define RCC_APB2ENR_TIM17EN_Msk        (0x1UL << RCC_APB2ENR_TIM17EN_Pos)      /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN            RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM9EN_Pos         (19U)
#define RCC_APB2ENR_TIM9EN_Msk         (0x1UL << RCC_APB2ENR_TIM9EN_Pos)       /*!< 0x00080000 */
#define RCC_APB2ENR_TIM9EN             RCC_APB2ENR_TIM9EN_Msk
#define RCC_APB2ENR_SPI5EN_Pos         (20U)
#define RCC_APB2ENR_SPI5EN_Msk         (0x1UL << RCC_APB2ENR_SPI5EN_Pos)       /*!< 0x00100000 */
#define RCC_APB2ENR_SPI5EN             RCC_APB2ENR_SPI5EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos         (22U)
#define RCC_APB2ENR_SAI1EN_Msk         (0x1UL << RCC_APB2ENR_SAI1EN_Pos)       /*!< 0x00400000 */
#define RCC_APB2ENR_SAI1EN             RCC_APB2ENR_SAI1EN_Msk
#define RCC_APB2ENR_SAI2EN_Pos         (23U)
#define RCC_APB2ENR_SAI2EN_Msk         (0x1UL << RCC_APB2ENR_SAI2EN_Pos)       /*!< 0x00800000 */
#define RCC_APB2ENR_SAI2EN             RCC_APB2ENR_SAI2EN_Msk

/********************  Bit definition for RCC_APB4ENR register  ***************/
#define RCC_APB4ENR_SBSEN_Pos          (1U)
#define RCC_APB4ENR_SBSEN_Msk          (0x1UL << RCC_APB4ENR_SBSEN_Pos)        /*!< 0x00000002 */
#define RCC_APB4ENR_SBSEN              RCC_APB4ENR_SBSEN_Msk
#define RCC_APB4ENR_LPUART1EN_Pos      (3U)
#define RCC_APB4ENR_LPUART1EN_Msk      (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)    /*!< 0x00000008 */
#define RCC_APB4ENR_LPUART1EN          RCC_APB4ENR_LPUART1EN_Msk
#define RCC_APB4ENR_SPI6EN_Pos         (5U)
#define RCC_APB4ENR_SPI6EN_Msk         (0x1UL << RCC_APB4ENR_SPI6EN_Pos)       /*!< 0x00000020 */
#define RCC_APB4ENR_SPI6EN             RCC_APB4ENR_SPI6EN_Msk
#define RCC_APB4ENR_LPTIM2EN_Pos       (9U)
#define RCC_APB4ENR_LPTIM2EN_Msk       (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)     /*!< 0x00000200 */
#define RCC_APB4ENR_LPTIM2EN           RCC_APB4ENR_LPTIM2EN_Msk
#define RCC_APB4ENR_LPTIM3EN_Pos       (10U)
#define RCC_APB4ENR_LPTIM3EN_Msk       (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)     /*!< 0x00000400 */
#define RCC_APB4ENR_LPTIM3EN           RCC_APB4ENR_LPTIM3EN_Msk
#define RCC_APB4ENR_LPTIM4EN_Pos       (11U)
#define RCC_APB4ENR_LPTIM4EN_Msk       (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)     /*!< 0x00000800 */
#define RCC_APB4ENR_LPTIM4EN           RCC_APB4ENR_LPTIM4EN_Msk
#define RCC_APB4ENR_LPTIM5EN_Pos       (12U)
#define RCC_APB4ENR_LPTIM5EN_Msk       (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)     /*!< 0x00001000 */
#define RCC_APB4ENR_LPTIM5EN           RCC_APB4ENR_LPTIM5EN_Msk
#define RCC_APB4ENR_VREFEN_Pos         (15U)
#define RCC_APB4ENR_VREFEN_Msk         (0x1UL << RCC_APB4ENR_VREFEN_Pos)       /*!< 0x00008000 */
#define RCC_APB4ENR_VREFEN             RCC_APB4ENR_VREFEN_Msk
#define RCC_APB4ENR_RTCAPBEN_Pos       (16U)
#define RCC_APB4ENR_RTCAPBEN_Msk       (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)     /*!< 0x00010000 */
#define RCC_APB4ENR_RTCAPBEN           RCC_APB4ENR_RTCAPBEN_Msk
#define RCC_APB4ENR_DTSEN_Pos          (26U)
#define RCC_APB4ENR_DTSEN_Msk          (0x1UL << RCC_APB4ENR_DTSEN_Pos)        /*!< 0x04000000 */
#define RCC_APB4ENR_DTSEN              RCC_APB4ENR_DTSEN_Msk

/********************  Bit definition for RCC_APB5ENR register  ***************/
#define RCC_APB5ENR_DCMIPPEN_Pos       (2U)
#define RCC_APB5ENR_DCMIPPEN_Msk       (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos)     /*!< 0x00000004 */
#define RCC_APB5ENR_DCMIPPEN           RCC_APB5ENR_DCMIPPEN_Msk
#define RCC_APB5ENR_GFXTIMEN_Pos       (4U)
#define RCC_APB5ENR_GFXTIMEN_Msk       (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos)     /*!< 0x00000010 */
#define RCC_APB5ENR_GFXTIMEN           RCC_APB5ENR_GFXTIMEN_Msk

/********************  Bit definition for RCC_AHB1LPENR register  *************/
#define RCC_AHB1LPENR_GPDMA1LPEN_Pos   (4U)
#define RCC_AHB1LPENR_GPDMA1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1LPENR_GPDMA1LPEN       RCC_AHB1LPENR_GPDMA1LPEN_Msk
#define RCC_AHB1LPENR_ADC12LPEN_Pos    (5U)
#define RCC_AHB1LPENR_ADC12LPEN_Msk    (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)  /*!< 0x00000020 */
#define RCC_AHB1LPENR_ADC12LPEN        RCC_AHB1LPENR_ADC12LPEN_Msk
#define RCC_AHB1LPENR_ETH1MACLPEN_Pos  (15U)
#define RCC_AHB1LPENR_ETH1MACLPEN_Msk  (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
#define RCC_AHB1LPENR_ETH1MACLPEN      RCC_AHB1LPENR_ETH1MACLPEN_Msk
#define RCC_AHB1LPENR_ETH1TXLPEN_Pos   (16U)
#define RCC_AHB1LPENR_ETH1TXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
#define RCC_AHB1LPENR_ETH1TXLPEN       RCC_AHB1LPENR_ETH1TXLPEN_Msk
#define RCC_AHB1LPENR_ETH1RXLPEN_Pos   (17U)
#define RCC_AHB1LPENR_ETH1RXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
#define RCC_AHB1LPENR_ETH1RXLPEN       RCC_AHB1LPENR_ETH1RXLPEN_Msk
#define RCC_AHB1LPENR_UCPDCTRL_Pos     (24U)
#define RCC_AHB1LPENR_UCPDCTRL_Msk     (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos)  /*!< 0x01000000 */
#define RCC_AHB1LPENR_UCPDCTRL         RCC_AHB1LPENR_UCPDCTRL_Msk
#define RCC_AHB1LPENR_OTGHSLPEN_Pos    (25U)
#define RCC_AHB1LPENR_OTGHSLPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)  /*!< 0x02000000 */
#define RCC_AHB1LPENR_OTGHSLPEN        RCC_AHB1LPENR_OTGHSLPEN_Msk
#define RCC_AHB1LPENR_USBPHYCLPEN_Pos  (26U)
#define RCC_AHB1LPENR_USBPHYCLPEN_Msk  (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */
#define RCC_AHB1LPENR_USBPHYCLPEN      RCC_AHB1LPENR_USBPHYCLPEN_Msk
#define RCC_AHB1LPENR_OTGFSLPEN_Pos    (27U)
#define RCC_AHB1LPENR_OTGFSLPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos)  /*!< 0x08000000 */
#define RCC_AHB1LPENR_OTGFSLPEN        RCC_AHB1LPENR_OTGFSLPEN_Msk
#define RCC_AHB1LPENR_ADF1LPEN_Pos     (31U)
#define RCC_AHB1LPENR_ADF1LPEN_Msk     (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos)   /*!< 0x80000000 */
#define RCC_AHB1LPENR_ADF1LPEN         RCC_AHB1LPENR_ADF1LPEN_Msk

/********************  Bit definition for RCC_AHB2LPENR register  *************/
#define RCC_AHB2LPENR_PSSILPEN_Pos     (1U)
#define RCC_AHB2LPENR_PSSILPEN_Msk     (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos)   /*!< 0x00000002 */
#define RCC_AHB2LPENR_PSSILPEN         RCC_AHB2LPENR_PSSILPEN_Msk
#define RCC_AHB2LPENR_SDMMC2LPEN_Pos   (9U)
#define RCC_AHB2LPENR_SDMMC2LPEN_Msk   (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2LPENR_SDMMC2LPEN       RCC_AHB2LPENR_SDMMC2LPEN_Msk
#define RCC_AHB2LPENR_CORDICLPEN_Pos   (14U)
#define RCC_AHB2LPENR_CORDICLPEN_Msk   (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */
#define RCC_AHB2LPENR_CORDICLPEN       RCC_AHB2LPENR_CORDICLPEN_Msk
#define RCC_AHB2LPENR_SRAM1LPEN_Pos    (29U)
#define RCC_AHB2LPENR_SRAM1LPEN_Msk    (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)  /*!< 0x20000000 */
#define RCC_AHB2LPENR_SRAM1LPEN        RCC_AHB2LPENR_SRAM1LPEN_Msk
#define RCC_AHB2LPENR_SRAM2LPEN_Pos    (30U)
#define RCC_AHB2LPENR_SRAM2LPEN_Msk    (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)  /*!< 0x40000000 */
#define RCC_AHB2LPENR_SRAM2LPEN        RCC_AHB2LPENR_SRAM2LPEN_Msk

/********************  Bit definition for RCC_AHB3LPENR register  *************/
#define RCC_AHB3LPENR_RNGLPEN_Pos      (0U)
#define RCC_AHB3LPENR_RNGLPEN_Msk      (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos)    /*!< 0x00000001 */
#define RCC_AHB3LPENR_RNGLPEN          RCC_AHB3LPENR_RNGLPEN_Msk
#define RCC_AHB3LPENR_HASHLPEN_Pos     (1U)
#define RCC_AHB3LPENR_HASHLPEN_Msk     (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos)   /*!< 0x00000002 */
#define RCC_AHB3LPENR_HASHLPEN         RCC_AHB3LPENR_HASHLPEN_Msk
#define RCC_AHB3LPENR_CRYPLPEN_Pos     (2U)
#define RCC_AHB3LPENR_CRYPLPEN_Msk     (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos)   /*!< 0x00000004 */
#define RCC_AHB3LPENR_CRYPLPEN         RCC_AHB3LPENR_CRYPLPEN_Msk
#define RCC_AHB3LPENR_SAESLPEN_Pos     (4U)
#define RCC_AHB3LPENR_SAESLPEN_Msk     (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos)   /*!< 0x00000010 */
#define RCC_AHB3LPENR_SAESLPEN         RCC_AHB3LPENR_SAESLPEN_Msk
#define RCC_AHB3LPENR_PKALPEN_Pos      (6U)
#define RCC_AHB3LPENR_PKALPEN_Msk      (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos)    /*!< 0x00000040 */
#define RCC_AHB3LPENR_PKALPEN          RCC_AHB3LPENR_PKALPEN_Msk

/********************  Bit definition for RCC_AHB4LPENR register  *************/
#define RCC_AHB4LPENR_GPIOALPEN_Pos    (0U)
#define RCC_AHB4LPENR_GPIOALPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)  /*!< 0x00000001 */
#define RCC_AHB4LPENR_GPIOALPEN        RCC_AHB4LPENR_GPIOALPEN_Msk
#define RCC_AHB4LPENR_GPIOBLPEN_Pos    (1U)
#define RCC_AHB4LPENR_GPIOBLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)  /*!< 0x00000002 */
#define RCC_AHB4LPENR_GPIOBLPEN        RCC_AHB4LPENR_GPIOBLPEN_Msk
#define RCC_AHB4LPENR_GPIOCLPEN_Pos    (2U)
#define RCC_AHB4LPENR_GPIOCLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)  /*!< 0x00000004 */
#define RCC_AHB4LPENR_GPIOCLPEN        RCC_AHB4LPENR_GPIOCLPEN_Msk
#define RCC_AHB4LPENR_GPIODLPEN_Pos    (3U)
#define RCC_AHB4LPENR_GPIODLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)  /*!< 0x00000008 */
#define RCC_AHB4LPENR_GPIODLPEN        RCC_AHB4LPENR_GPIODLPEN_Msk
#define RCC_AHB4LPENR_GPIOELPEN_Pos    (4U)
#define RCC_AHB4LPENR_GPIOELPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)  /*!< 0x00000010 */
#define RCC_AHB4LPENR_GPIOELPEN        RCC_AHB4LPENR_GPIOELPEN_Msk
#define RCC_AHB4LPENR_GPIOFLPEN_Pos    (5U)
#define RCC_AHB4LPENR_GPIOFLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)  /*!< 0x00000020 */
#define RCC_AHB4LPENR_GPIOFLPEN        RCC_AHB4LPENR_GPIOFLPEN_Msk
#define RCC_AHB4LPENR_GPIOGLPEN_Pos    (6U)
#define RCC_AHB4LPENR_GPIOGLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)  /*!< 0x00000040 */
#define RCC_AHB4LPENR_GPIOGLPEN        RCC_AHB4LPENR_GPIOGLPEN_Msk
#define RCC_AHB4LPENR_GPIOHLPEN_Pos    (7U)
#define RCC_AHB4LPENR_GPIOHLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)  /*!< 0x00000080 */
#define RCC_AHB4LPENR_GPIOHLPEN        RCC_AHB4LPENR_GPIOHLPEN_Msk
#define RCC_AHB4LPENR_GPIOMLPEN_Pos    (12U)
#define RCC_AHB4LPENR_GPIOMLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos)  /*!< 0x00001000 */
#define RCC_AHB4LPENR_GPIOMLPEN        RCC_AHB4LPENR_GPIOMLPEN_Msk
#define RCC_AHB4LPENR_GPIONLPEN_Pos    (13U)
#define RCC_AHB4LPENR_GPIONLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)  /*!< 0x00002000 */
#define RCC_AHB4LPENR_GPIONLPEN        RCC_AHB4LPENR_GPIONLPEN_Msk
#define RCC_AHB4LPENR_GPIOOLPEN_Pos    (14U)
#define RCC_AHB4LPENR_GPIOOLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)  /*!< 0x00004000 */
#define RCC_AHB4LPENR_GPIOOLPEN        RCC_AHB4LPENR_GPIOOLPEN_Msk
#define RCC_AHB4LPENR_GPIOPLPEN_Pos    (15U)
#define RCC_AHB4LPENR_GPIOPLPEN_Msk    (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)  /*!< 0x00008000 */
#define RCC_AHB4LPENR_GPIOPLPEN        RCC_AHB4LPENR_GPIOPLPEN_Msk
#define RCC_AHB4LPENR_CRCLPEN_Pos      (19U)
#define RCC_AHB4LPENR_CRCLPEN_Msk      (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)    /*!< 0x00080000 */
#define RCC_AHB4LPENR_CRCLPEN          RCC_AHB4LPENR_CRCLPEN_Msk
#define RCC_AHB4LPENR_BKPRAMLPEN_Pos   (28U)
#define RCC_AHB4LPENR_BKPRAMLPEN_Msk   (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
#define RCC_AHB4LPENR_BKPRAMLPEN       RCC_AHB4LPENR_BKPRAMLPEN_Msk

/********************  Bit definition for RCC_AHB5LPENR register  *************/
#define RCC_AHB5LPENR_HPDMA1LPEN_Pos   (0U)
#define RCC_AHB5LPENR_HPDMA1LPEN_Msk   (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB5LPENR_HPDMA1LPEN       RCC_AHB5LPENR_HPDMA1LPEN_Msk
#define RCC_AHB5LPENR_DMA2DLPEN_Pos    (1U)
#define RCC_AHB5LPENR_DMA2DLPEN_Msk    (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)  /*!< 0x00000002 */
#define RCC_AHB5LPENR_DMA2DLPEN        RCC_AHB5LPENR_DMA2DLPEN_Msk
#define RCC_AHB5LPENR_FLASHLPEN_Pos    (2U)
#define RCC_AHB5LPENR_FLASHLPEN_Msk    (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos)  /*!< 0x00000004 */
#define RCC_AHB5LPENR_FLASHLPEN        RCC_AHB5LPENR_FLASHLPEN_Msk
#define RCC_AHB5LPENR_JPEGLPEN_Pos     (3U)
#define RCC_AHB5LPENR_JPEGLPEN_Msk     (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos)   /*!< 0x00000008 */
#define RCC_AHB5LPENR_JPEGLPEN         RCC_AHB5LPENR_JPEGLPEN_Msk
#define RCC_AHB5LPENR_FMCLPEN_Pos      (4U)
#define RCC_AHB5LPENR_FMCLPEN_Msk      (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos)    /*!< 0x00000010 */
#define RCC_AHB5LPENR_FMCLPEN          RCC_AHB5LPENR_FMCLPEN_Msk
#define RCC_AHB5LPENR_XSPI1LPEN_Pos    (5U)
#define RCC_AHB5LPENR_XSPI1LPEN_Msk    (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)  /*!< 0x00000020 */
#define RCC_AHB5LPENR_XSPI1LPEN        RCC_AHB5LPENR_XSPI1LPEN_Msk
#define RCC_AHB5LPENR_SDMMC1LPEN_Pos   (8U)
#define RCC_AHB5LPENR_SDMMC1LPEN_Msk   (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
#define RCC_AHB5LPENR_SDMMC1LPEN       RCC_AHB5LPENR_SDMMC1LPEN_Msk
#define RCC_AHB5LPENR_XSPI2LPEN_Pos    (12U)
#define RCC_AHB5LPENR_XSPI2LPEN_Msk    (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)  /*!< 0x00001000 */
#define RCC_AHB5LPENR_XSPI2LPEN        RCC_AHB5LPENR_XSPI2LPEN_Msk
#define RCC_AHB5LPENR_XSPIMLPEN_Pos    (14U)
#define RCC_AHB5LPENR_XSPIMLPEN_Msk    (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)  /*!< 0x00004000 */
#define RCC_AHB5LPENR_XSPIMLPEN        RCC_AHB5LPENR_XSPIMLPEN_Msk
#define RCC_AHB5LPENR_GFXMMULPEN_Pos   (19U)
#define RCC_AHB5LPENR_GFXMMULPEN_Msk   (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
#define RCC_AHB5LPENR_GFXMMULPEN       RCC_AHB5LPENR_GFXMMULPEN_Msk
#define RCC_AHB5LPENR_DTCM1LPEN_Pos    (28U)
#define RCC_AHB5LPENR_DTCM1LPEN_Msk    (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos)  /*!< 0x10000000 */
#define RCC_AHB5LPENR_DTCM1LPEN        RCC_AHB5LPENR_DTCM1LPEN_Msk
#define RCC_AHB5LPENR_DTCM2LPEN_Pos    (29U)
#define RCC_AHB5LPENR_DTCM2LPEN_Msk    (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos)  /*!< 0x20000000 */
#define RCC_AHB5LPENR_DTCM2LPEN        RCC_AHB5LPENR_DTCM2LPEN_Msk
#define RCC_AHB5LPENR_ITCMLPEN_Pos     (30U)
#define RCC_AHB5LPENR_ITCMLPEN_Msk     (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos)   /*!< 0x40000000 */
#define RCC_AHB5LPENR_ITCMLPEN         RCC_AHB5LPENR_ITCMLPEN_Msk
#define RCC_AHB5LPENR_AXISRAMLPEN_Pos  (31U)
#define RCC_AHB5LPENR_AXISRAMLPEN_Msk  (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
#define RCC_AHB5LPENR_AXISRAMLPEN      RCC_AHB5LPENR_AXISRAMLPEN_Msk

/********************  Bit definition for RCC_APB1LPENR1 register  ************/
#define RCC_APB1LPENR1_TIM2LPEN_Pos    (0U)
#define RCC_APB1LPENR1_TIM2LPEN_Msk    (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)  /*!< 0x00000001 */
#define RCC_APB1LPENR1_TIM2LPEN        RCC_APB1LPENR1_TIM2LPEN_Msk
#define RCC_APB1LPENR1_TIM3LPEN_Pos    (1U)
#define RCC_APB1LPENR1_TIM3LPEN_Msk    (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)  /*!< 0x00000002 */
#define RCC_APB1LPENR1_TIM3LPEN        RCC_APB1LPENR1_TIM3LPEN_Msk
#define RCC_APB1LPENR1_TIM4LPEN_Pos    (2U)
#define RCC_APB1LPENR1_TIM4LPEN_Msk    (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)  /*!< 0x00000004 */
#define RCC_APB1LPENR1_TIM4LPEN        RCC_APB1LPENR1_TIM4LPEN_Msk
#define RCC_APB1LPENR1_TIM5LPEN_Pos    (3U)
#define RCC_APB1LPENR1_TIM5LPEN_Msk    (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)  /*!< 0x00000008 */
#define RCC_APB1LPENR1_TIM5LPEN        RCC_APB1LPENR1_TIM5LPEN_Msk
#define RCC_APB1LPENR1_TIM6LPEN_Pos    (4U)
#define RCC_APB1LPENR1_TIM6LPEN_Msk    (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)  /*!< 0x00000010 */
#define RCC_APB1LPENR1_TIM6LPEN        RCC_APB1LPENR1_TIM6LPEN_Msk
#define RCC_APB1LPENR1_TIM7LPEN_Pos    (5U)
#define RCC_APB1LPENR1_TIM7LPEN_Msk    (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)  /*!< 0x00000020 */
#define RCC_APB1LPENR1_TIM7LPEN        RCC_APB1LPENR1_TIM7LPEN_Msk
#define RCC_APB1LPENR1_TIM12LPEN_Pos   (6U)
#define RCC_APB1LPENR1_TIM12LPEN_Msk   (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
#define RCC_APB1LPENR1_TIM12LPEN       RCC_APB1LPENR1_TIM12LPEN_Msk
#define RCC_APB1LPENR1_TIM13LPEN_Pos   (7U)
#define RCC_APB1LPENR1_TIM13LPEN_Msk   (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
#define RCC_APB1LPENR1_TIM13LPEN       RCC_APB1LPENR1_TIM13LPEN_Msk
#define RCC_APB1LPENR1_TIM14LPEN_Pos   (8U)
#define RCC_APB1LPENR1_TIM14LPEN_Msk   (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENR1_TIM14LPEN       RCC_APB1LPENR1_TIM14LPEN_Msk
#define RCC_APB1LPENR1_LPTIM1LPEN_Pos  (9U)
#define RCC_APB1LPENR1_LPTIM1LPEN_Msk  (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */
#define RCC_APB1LPENR1_LPTIM1LPEN      RCC_APB1LPENR1_LPTIM1LPEN_Msk
#define RCC_APB1LPENR1_WWDGLPEN_Pos    (11U)
#define RCC_APB1LPENR1_WWDGLPEN_Msk    (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)  /*!< 0x00000800 */
#define RCC_APB1LPENR1_WWDGLPEN        RCC_APB1LPENR1_WWDGLPEN_Msk
#define RCC_APB1LPENR1_SPI2LPEN_Pos    (14U)
#define RCC_APB1LPENR1_SPI2LPEN_Msk    (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)  /*!< 0x00004000 */
#define RCC_APB1LPENR1_SPI2LPEN        RCC_APB1LPENR1_SPI2LPEN_Msk
#define RCC_APB1LPENR1_SPI3LPEN_Pos    (15U)
#define RCC_APB1LPENR1_SPI3LPEN_Msk    (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)  /*!< 0x00008000 */
#define RCC_APB1LPENR1_SPI3LPEN        RCC_APB1LPENR1_SPI3LPEN_Msk
#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U)
#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */
#define RCC_APB1LPENR1_SPDIFRXLPEN     RCC_APB1LPENR1_SPDIFRXLPEN_Msk
#define RCC_APB1LPENR1_USART2LPEN_Pos  (17U)
#define RCC_APB1LPENR1_USART2LPEN_Msk  (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */
#define RCC_APB1LPENR1_USART2LPEN      RCC_APB1LPENR1_USART2LPEN_Msk
#define RCC_APB1LPENR1_USART3LPEN_Pos  (18U)
#define RCC_APB1LPENR1_USART3LPEN_Msk  (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */
#define RCC_APB1LPENR1_USART3LPEN      RCC_APB1LPENR1_USART3LPEN_Msk
#define RCC_APB1LPENR1_UART4LPEN_Pos   (19U)
#define RCC_APB1LPENR1_UART4LPEN_Msk   (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
#define RCC_APB1LPENR1_UART4LPEN       RCC_APB1LPENR1_UART4LPEN_Msk
#define RCC_APB1LPENR1_UART5LPEN_Pos   (20U)
#define RCC_APB1LPENR1_UART5LPEN_Msk   (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
#define RCC_APB1LPENR1_UART5LPEN       RCC_APB1LPENR1_UART5LPEN_Msk
#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U)
#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos)  /*!< 0x00200000 */
#define RCC_APB1LPENR1_I2C1_I3C1LPEN   RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk
#define RCC_APB1LPENR1_I2C2LPEN_Pos    (22U)
#define RCC_APB1LPENR1_I2C2LPEN_Msk    (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)  /*!< 0x00400000 */
#define RCC_APB1LPENR1_I2C2LPEN        RCC_APB1LPENR1_I2C2LPEN_Msk
#define RCC_APB1LPENR1_I2C3LPEN_Pos    (23U)
#define RCC_APB1LPENR1_I2C3LPEN_Msk    (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)  /*!< 0x00800000 */
#define RCC_APB1LPENR1_I2C3LPEN        RCC_APB1LPENR1_I2C3LPEN_Msk
#define RCC_APB1LPENR1_CECLPEN_Pos     (27U)
#define RCC_APB1LPENR1_CECLPEN_Msk     (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos)   /*!< 0x08000000 */
#define RCC_APB1LPENR1_CECLPEN         RCC_APB1LPENR1_CECLPEN_Msk
#define RCC_APB1LPENR1_UART7LPEN_Pos   (30U)
#define RCC_APB1LPENR1_UART7LPEN_Msk   (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
#define RCC_APB1LPENR1_UART7LPEN       RCC_APB1LPENR1_UART7LPEN_Msk
#define RCC_APB1LPENR1_UART8LPEN_Pos   (31U)
#define RCC_APB1LPENR1_UART8LPEN_Msk   (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
#define RCC_APB1LPENR1_UART8LPEN       RCC_APB1LPENR1_UART8LPEN_Msk

/********************  Bit definition for RCC_PB1LPENR2 register  ************/
#define RCC_APB1LPENR2_CRSLPEN_Pos     (1U)
#define RCC_APB1LPENR2_CRSLPEN_Msk     (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos)   /*!< 0x00000002 */
#define RCC_APB1LPENR2_CRSLPEN         RCC_APB1LPENR2_CRSLPEN_Msk
#define RCC_APB1LPENR2_MDIOSLPEN_Pos   (5U)
#define RCC_APB1LPENR2_MDIOSLPEN_Msk   (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
#define RCC_APB1LPENR2_MDIOSLPEN       RCC_APB1LPENR2_MDIOSLPEN_Msk
#define RCC_APB1LPENR2_FDCANLPEN_Pos   (8U)
#define RCC_APB1LPENR2_FDCANLPEN_Msk   (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENR2_FDCANLPEN       RCC_APB1LPENR2_FDCANLPEN_Msk
#define RCC_APB1LPENR2_UCPD1LPEN_Pos   (27U)
#define RCC_APB1LPENR2_UCPD1LPEN_Msk   (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */
#define RCC_APB1LPENR2_UCPD1LPEN       RCC_APB1LPENR2_UCPD1LPEN_Msk

/********************  Bit definition for RCC_APB2LPENR register  *************/
#define RCC_APB2LPENR_TIM1LPEN_Pos     (0U)
#define RCC_APB2LPENR_TIM1LPEN_Msk     (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)   /*!< 0x00000001 */
#define RCC_APB2LPENR_TIM1LPEN         RCC_APB2LPENR_TIM1LPEN_Msk
#define RCC_APB2LPENR_USART1LPEN_Pos   (4U)
#define RCC_APB2LPENR_USART1LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
#define RCC_APB2LPENR_USART1LPEN       RCC_APB2LPENR_USART1LPEN_Msk
#define RCC_APB2LPENR_SPI1LPEN_Pos     (12U)
#define RCC_APB2LPENR_SPI1LPEN_Msk     (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)   /*!< 0x00001000 */
#define RCC_APB2LPENR_SPI1LPEN         RCC_APB2LPENR_SPI1LPEN_Msk
#define RCC_APB2LPENR_SPI4LPEN_Pos     (13U)
#define RCC_APB2LPENR_SPI4LPEN_Msk     (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)   /*!< 0x00002000 */
#define RCC_APB2LPENR_SPI4LPEN         RCC_APB2LPENR_SPI4LPEN_Msk
#define RCC_APB2LPENR_TIM15LPEN_Pos    (16U)
#define RCC_APB2LPENR_TIM15LPEN_Msk    (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)  /*!< 0x00010000 */
#define RCC_APB2LPENR_TIM15LPEN        RCC_APB2LPENR_TIM15LPEN_Msk
#define RCC_APB2LPENR_TIM16LPEN_Pos    (17U)
#define RCC_APB2LPENR_TIM16LPEN_Msk    (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)  /*!< 0x00020000 */
#define RCC_APB2LPENR_TIM16LPEN        RCC_APB2LPENR_TIM16LPEN_Msk
#define RCC_APB2LPENR_TIM17LPEN_Pos    (18U)
#define RCC_APB2LPENR_TIM17LPEN_Msk    (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)  /*!< 0x00040000 */
#define RCC_APB2LPENR_TIM17LPEN        RCC_APB2LPENR_TIM17LPEN_Msk
#define RCC_APB2LPENR_TIM9LPEN_Pos     (19U)
#define RCC_APB2LPENR_TIM9LPEN_Msk     (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)   /*!< 0x00080000 */
#define RCC_APB2LPENR_TIM9LPEN         RCC_APB2LPENR_TIM9LPEN_Msk
#define RCC_APB2LPENR_SPI5LPEN_Pos     (20U)
#define RCC_APB2LPENR_SPI5LPEN_Msk     (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)   /*!< 0x00100000 */
#define RCC_APB2LPENR_SPI5LPEN         RCC_APB2LPENR_SPI5LPEN_Msk
#define RCC_APB2LPENR_SAI1LPEN_Pos     (22U)
#define RCC_APB2LPENR_SAI1LPEN_Msk     (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)   /*!< 0x00400000 */
#define RCC_APB2LPENR_SAI1LPEN         RCC_APB2LPENR_SAI1LPEN_Msk
#define RCC_APB2LPENR_SAI2LPEN_Pos     (23U)
#define RCC_APB2LPENR_SAI2LPEN_Msk     (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)   /*!< 0x00800000 */
#define RCC_APB2LPENR_SAI2LPEN         RCC_APB2LPENR_SAI2LPEN_Msk

/********************  Bit definition for RCC_APB4LPENR register  *************/
#define RCC_APB4LPENR_SBSLPEN_Pos      (1U)
#define RCC_APB4LPENR_SBSLPEN_Msk      (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos)    /*!< 0x00000002 */
#define RCC_APB4LPENR_SBSLPEN          RCC_APB4LPENR_SBSLPEN_Msk
#define RCC_APB4LPENR_LPUART1LPEN_Pos  (3U)
#define RCC_APB4LPENR_LPUART1LPEN_Msk  (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */
#define RCC_APB4LPENR_LPUART1LPEN      RCC_APB4LPENR_LPUART1LPEN_Msk
#define RCC_APB4LPENR_SPI6LPEN_Pos     (5U)
#define RCC_APB4LPENR_SPI6LPEN_Msk     (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)   /*!< 0x00000020 */
#define RCC_APB4LPENR_SPI6LPEN         RCC_APB4LPENR_SPI6LPEN_Msk
#define RCC_APB4LPENR_LPTIM2LPEN_Pos   (9U)
#define RCC_APB4LPENR_LPTIM2LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
#define RCC_APB4LPENR_LPTIM2LPEN       RCC_APB4LPENR_LPTIM2LPEN_Msk
#define RCC_APB4LPENR_LPTIM3LPEN_Pos   (10U)
#define RCC_APB4LPENR_LPTIM3LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
#define RCC_APB4LPENR_LPTIM3LPEN       RCC_APB4LPENR_LPTIM3LPEN_Msk
#define RCC_APB4LPENR_LPTIM4LPEN_Pos   (11U)
#define RCC_APB4LPENR_LPTIM4LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
#define RCC_APB4LPENR_LPTIM4LPEN       RCC_APB4LPENR_LPTIM4LPEN_Msk
#define RCC_APB4LPENR_LPTIM5LPEN_Pos   (12U)
#define RCC_APB4LPENR_LPTIM5LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
#define RCC_APB4LPENR_LPTIM5LPEN       RCC_APB4LPENR_LPTIM5LPEN_Msk
#define RCC_APB4LPENR_VREFLPEN_Pos     (15U)
#define RCC_APB4LPENR_VREFLPEN_Msk     (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)   /*!< 0x00008000 */
#define RCC_APB4LPENR_VREFLPEN         RCC_APB4LPENR_VREFLPEN_Msk
#define RCC_APB4LPENR_RTCAPBLPEN_Pos   (16U)
#define RCC_APB4LPENR_RTCAPBLPEN_Msk   (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
#define RCC_APB4LPENR_RTCAPBLPEN       RCC_APB4LPENR_RTCAPBLPEN_Msk
#define RCC_APB4LPENR_DTSLPEN_Pos      (26U)
#define RCC_APB4LPENR_DTSLPEN_Msk      (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos)    /*!< 0x04000000 */
#define RCC_APB4LPENR_DTSLPEN          RCC_APB4LPENR_DTSLPEN_Msk

/********************  Bit definition for RCC_APB5LPENR register  *************/
#define RCC_APB5LPENR_DCMIPPLPEN_Pos   (2U)
#define RCC_APB5LPENR_DCMIPPLPEN_Msk   (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
#define RCC_APB5LPENR_DCMIPPLPEN       RCC_APB5LPENR_DCMIPPLPEN_Msk
#define RCC_APB5LPENR_GFXTIMLPEN_Pos   (4U)
#define RCC_APB5LPENR_GFXTIMLPEN_Msk   (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
#define RCC_APB5LPENR_GFXTIMLPEN       RCC_APB5LPENR_GFXTIMLPEN_Msk


/******************************************************************************/
/*                                                                            */
/*                                    RNG                                     */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RNG_CR register  *******************/
#define RNG_CR_RNGEN_Pos               (2U)
#define RNG_CR_RNGEN_Msk               (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
#define RNG_CR_RNGEN                   RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos                  (3U)
#define RNG_CR_IE_Msk                  (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
#define RNG_CR_IE                      RNG_CR_IE_Msk
#define RNG_CR_CED_Pos                 (5U)
#define RNG_CR_CED_Msk                 (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
#define RNG_CR_CED                     RNG_CR_CED_Msk
#define RNG_CR_ARDIS_Pos               (7U)
#define RNG_CR_ARDIS_Msk               (0x1UL << RNG_CR_ARDIS_Pos)
#define RNG_CR_ARDIS                   RNG_CR_ARDIS_Msk
#define RNG_CR_RNG_CONFIG3_Pos         (8U)
#define RNG_CR_RNG_CONFIG3_Msk         (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
#define RNG_CR_RNG_CONFIG3             RNG_CR_RNG_CONFIG3_Msk
#define RNG_CR_NISTC_Pos               (12U)
#define RNG_CR_NISTC_Msk               (0x1UL << RNG_CR_NISTC_Pos)
#define RNG_CR_NISTC                   RNG_CR_NISTC_Msk
#define RNG_CR_RNG_CONFIG2_Pos         (13U)
#define RNG_CR_RNG_CONFIG2_Msk         (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
#define RNG_CR_RNG_CONFIG2             RNG_CR_RNG_CONFIG2_Msk
#define RNG_CR_CLKDIV_Pos              (16U)
#define RNG_CR_CLKDIV_Msk              (0xFUL << RNG_CR_CLKDIV_Pos)
#define RNG_CR_CLKDIV                  RNG_CR_CLKDIV_Msk
#define RNG_CR_CLKDIV_0                (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
#define RNG_CR_CLKDIV_1                (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
#define RNG_CR_CLKDIV_2                (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
#define RNG_CR_CLKDIV_3                (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
#define RNG_CR_RNG_CONFIG1_Pos         (20U)
#define RNG_CR_RNG_CONFIG1_Msk         (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
#define RNG_CR_RNG_CONFIG1             RNG_CR_RNG_CONFIG1_Msk
#define RNG_CR_CONDRST_Pos             (30U)
#define RNG_CR_CONDRST_Msk             (0x1UL << RNG_CR_CONDRST_Pos)
#define RNG_CR_CONDRST                 RNG_CR_CONDRST_Msk
#define RNG_CR_CONFIGLOCK_Pos          (31U)
#define RNG_CR_CONFIGLOCK_Msk          (0x1UL << RNG_CR_CONFIGLOCK_Pos)
#define RNG_CR_CONFIGLOCK              RNG_CR_CONFIGLOCK_Msk

/********************  Bits definition for RNG_SR register  *******************/
#define RNG_SR_DRDY_Pos                (0U)
#define RNG_SR_DRDY_Msk                (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
#define RNG_SR_DRDY                    RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos                (1U)
#define RNG_SR_CECS_Msk                (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
#define RNG_SR_CECS                    RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos                (2U)
#define RNG_SR_SECS_Msk                (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
#define RNG_SR_SECS                    RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos                (5U)
#define RNG_SR_CEIS_Msk                (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
#define RNG_SR_CEIS                    RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos                (6U)
#define RNG_SR_SEIS_Msk                (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
#define RNG_SR_SEIS                    RNG_SR_SEIS_Msk

/********************  Bits definition for RNG_HTCR register  *******************/
#define RNG_HTCR_HTCFG_Pos             (0U)
#define RNG_HTCR_HTCFG_Msk             (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG                 RNG_HTCR_HTCFG_Msk


/******************************************************************************/
/*                                                                            */
/*                           Real-Time Clock (RTC)                            */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RTC_TR register  *******************/
#define RTC_TR_SU_Pos                       (0U)
#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
#define RTC_TR_SU                           RTC_TR_SU_Msk
#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
#define RTC_TR_ST_Pos                       (4U)
#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
#define RTC_TR_ST                           RTC_TR_ST_Msk
#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
#define RTC_TR_MNU_Pos                      (8U)
#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
#define RTC_TR_MNU                          RTC_TR_MNU_Msk
#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
#define RTC_TR_MNT_Pos                      (12U)
#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
#define RTC_TR_MNT                          RTC_TR_MNT_Msk
#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
#define RTC_TR_HU_Pos                       (16U)
#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
#define RTC_TR_HU                           RTC_TR_HU_Msk
#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
#define RTC_TR_HT_Pos                       (20U)
#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
#define RTC_TR_HT                           RTC_TR_HT_Msk
#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
#define RTC_TR_PM_Pos                       (22U)
#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
#define RTC_TR_PM                           RTC_TR_PM_Msk

/********************  Bits definition for RTC_DR register  *******************/
#define RTC_DR_DU_Pos                       (0U)
#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
#define RTC_DR_DU                           RTC_DR_DU_Msk
#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
#define RTC_DR_DT_Pos                       (4U)
#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
#define RTC_DR_DT                           RTC_DR_DT_Msk
#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
#define RTC_DR_MU_Pos                       (8U)
#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
#define RTC_DR_MU                           RTC_DR_MU_Msk
#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
#define RTC_DR_MT_Pos                       (12U)
#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
#define RTC_DR_MT                           RTC_DR_MT_Msk
#define RTC_DR_WDU_Pos                      (13U)
#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
#define RTC_DR_WDU                          RTC_DR_WDU_Msk
#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
#define RTC_DR_YU_Pos                       (16U)
#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
#define RTC_DR_YU                           RTC_DR_YU_Msk
#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
#define RTC_DR_YT_Pos                       (20U)
#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
#define RTC_DR_YT                           RTC_DR_YT_Msk
#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */

/********************  Bits definition for RTC_SSR register  ******************/
#define RTC_SSR_SS_Pos                      (0U)
#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
#define RTC_SSR_SS                          RTC_SSR_SS_Msk

/********************  Bits definition for RTC_ICSR register  ******************/
#define RTC_ICSR_WUTWF_Pos                  (2U)
#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_SHPF_Pos                   (3U)
#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
#define RTC_ICSR_INITS_Pos                  (4U)
#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
#define RTC_ICSR_RSF_Pos                    (5U)
#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITF_Pos                  (6U)
#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
#define RTC_ICSR_INIT_Pos                   (7U)
#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
#define RTC_ICSR_BIN_Pos                    (8U)
#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
#define RTC_ICSR_BCDU_Pos                   (10U)
#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
#define RTC_ICSR_RECALPF_Pos                (16U)
#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk

/********************  Bits definition for RTC_PRER register  *****************/
#define RTC_PRER_PREDIV_S_Pos               (0U)
#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
#define RTC_PRER_PREDIV_A_Pos               (16U)
#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk

/********************  Bits definition for RTC_WUTR register  *****************/
#define RTC_WUTR_WUT_Pos                    (0U)
#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
#define RTC_WUTR_WUTOCLR_Pos                (16U)
#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk

/********************  Bits definition for RTC_CR register  *******************/
#define RTC_CR_WUCKSEL_Pos                  (0U)
#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
#define RTC_CR_TSEDGE_Pos                   (3U)
#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
#define RTC_CR_REFCKON_Pos                  (4U)
#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
#define RTC_CR_BYPSHAD_Pos                  (5U)
#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
#define RTC_CR_FMT_Pos                      (6U)
#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
#define RTC_CR_FMT                          RTC_CR_FMT_Msk
#define RTC_CR_SSRUIE_Pos                   (7U)
#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
#define RTC_CR_ALRAE_Pos                    (8U)
#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
#define RTC_CR_ALRBE_Pos                    (9U)
#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
#define RTC_CR_WUTE_Pos                     (10U)
#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
#define RTC_CR_TSE_Pos                      (11U)
#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
#define RTC_CR_TSE                          RTC_CR_TSE_Msk
#define RTC_CR_ALRAIE_Pos                   (12U)
#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
#define RTC_CR_ALRBIE_Pos                   (13U)
#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
#define RTC_CR_WUTIE_Pos                    (14U)
#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
#define RTC_CR_TSIE_Pos                     (15U)
#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
#define RTC_CR_ADD1H_Pos                    (16U)
#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
#define RTC_CR_SUB1H_Pos                    (17U)
#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
#define RTC_CR_BKP_Pos                      (18U)
#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
#define RTC_CR_BKP                          RTC_CR_BKP_Msk
#define RTC_CR_COSEL_Pos                    (19U)
#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
#define RTC_CR_POL_Pos                      (20U)
#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
#define RTC_CR_POL                          RTC_CR_POL_Msk
#define RTC_CR_OSEL_Pos                     (21U)
#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
#define RTC_CR_COE_Pos                      (23U)
#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
#define RTC_CR_COE                          RTC_CR_COE_Msk
#define RTC_CR_ITSE_Pos                     (24U)
#define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
#define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
#define RTC_CR_TAMPTS_Pos                   (25U)
#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
#define RTC_CR_TAMPOE_Pos                   (26U)
#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
#define RTC_CR_ALRAFCLR_Pos                 (27U)
#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
#define RTC_CR_ALRBFCLR_Pos                 (28U)
#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
#define RTC_CR_TAMPALRM_PU_Pos              (29U)
#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
#define RTC_CR_OUT2EN_Pos                   (31U)
#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */

/********************  Bits definition for RTC_PRIVCFGR register  *****************/
#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
#define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
#define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
#define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
#define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
#define RTC_PRIVCFGR_PRIV_Pos               (15U)
#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk

/********************  Bits definition for RTC_WPR register  ******************/
#define RTC_WPR_KEY_Pos                     (0U)
#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk

/********************  Bits definition for RTC_CALR register  *****************/
#define RTC_CALR_CALM_Pos                   (0U)
#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
#define RTC_CALR_LPCAL_Pos                  (12U)
#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
#define RTC_CALR_CALW16_Pos                 (13U)
#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
#define RTC_CALR_CALW8_Pos                  (14U)
#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
#define RTC_CALR_CALP_Pos                   (15U)
#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk

/********************  Bits definition for RTC_SHIFTR register  ***************/
#define RTC_SHIFTR_SUBFS_Pos                (0U)
#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos                (31U)
#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk

/********************  Bits definition for RTC_TSTR register  *****************/
#define RTC_TSTR_SU_Pos                     (0U)
#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
#define RTC_TSTR_ST_Pos                     (4U)
#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
#define RTC_TSTR_MNU_Pos                    (8U)
#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
#define RTC_TSTR_MNT_Pos                    (12U)
#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
#define RTC_TSTR_HU_Pos                     (16U)
#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
#define RTC_TSTR_HT_Pos                     (20U)
#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
#define RTC_TSTR_PM_Pos                     (22U)
#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk

/********************  Bits definition for RTC_TSDR register  *****************/
#define RTC_TSDR_DU_Pos                     (0U)
#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
#define RTC_TSDR_DT_Pos                     (4U)
#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
#define RTC_TSDR_MU_Pos                     (8U)
#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
#define RTC_TSDR_MT_Pos                     (12U)
#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
#define RTC_TSDR_WDU_Pos                    (13U)
#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */

/********************  Bits definition for RTC_TSSSR register  ****************/
#define RTC_TSSSR_SS_Pos                    (0U)
#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */

/********************  Bits definition for RTC_ALRMAR register  ***************/
#define RTC_ALRMAR_SU_Pos                   (0U)
#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
#define RTC_ALRMAR_ST_Pos                   (4U)
#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
#define RTC_ALRMAR_MSK1_Pos                 (7U)
#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_MNU_Pos                  (8U)
#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
#define RTC_ALRMAR_MNT_Pos                  (12U)
#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
#define RTC_ALRMAR_MSK2_Pos                 (15U)
#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_HU_Pos                   (16U)
#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
#define RTC_ALRMAR_HT_Pos                   (20U)
#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
#define RTC_ALRMAR_PM_Pos                   (22U)
#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_MSK3_Pos                 (23U)
#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_DU_Pos                   (24U)
#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
#define RTC_ALRMAR_DT_Pos                   (28U)
#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
#define RTC_ALRMAR_WDSEL_Pos                (30U)
#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_MSK4_Pos                 (31U)
#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk

/********************  Bits definition for RTC_ALRMASSR register  *************/
#define RTC_ALRMASSR_SS_Pos                 (0U)
#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
#define RTC_ALRMASSR_MASKSS_Pos             (24U)
#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
#define RTC_ALRMASSR_SSCLR_Pos              (31U)
#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk

/********************  Bits definition for RTC_ALRMBR register  ***************/
#define RTC_ALRMBR_SU_Pos                   (0U)
#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
#define RTC_ALRMBR_ST_Pos                   (4U)
#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
#define RTC_ALRMBR_MSK1_Pos                 (7U)
#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_MNU_Pos                  (8U)
#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
#define RTC_ALRMBR_MNT_Pos                  (12U)
#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
#define RTC_ALRMBR_MSK2_Pos                 (15U)
#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_HU_Pos                   (16U)
#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
#define RTC_ALRMBR_HT_Pos                   (20U)
#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
#define RTC_ALRMBR_PM_Pos                   (22U)
#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_MSK3_Pos                 (23U)
#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_DU_Pos                   (24U)
#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
#define RTC_ALRMBR_DT_Pos                   (28U)
#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
#define RTC_ALRMBR_WDSEL_Pos                (30U)
#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_MSK4_Pos                 (31U)
#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk

/********************  Bits definition for RTC_ALRMBSSR register  *************/
#define RTC_ALRMBSSR_SS_Pos                 (0U)
#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
#define RTC_ALRMBSSR_MASKSS_Pos             (24U)
#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
#define RTC_ALRMBSSR_SSCLR_Pos              (31U)
#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk

/********************  Bits definition for RTC_SR register  *******************/
#define RTC_SR_ALRAF_Pos                    (0U)
#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
#define RTC_SR_ALRBF_Pos                    (1U)
#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
#define RTC_SR_WUTF_Pos                     (2U)
#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
#define RTC_SR_TSF_Pos                      (3U)
#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
#define RTC_SR_TSF                          RTC_SR_TSF_Msk
#define RTC_SR_TSOVF_Pos                    (4U)
#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
#define RTC_SR_ITSF_Pos                     (5U)
#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
#define RTC_SR_SSRUF_Pos                    (6U)
#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk

/********************  Bits definition for RTC_MISR register  *****************/
#define RTC_MISR_ALRAMF_Pos                 (0U)
#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
#define RTC_MISR_ALRBMF_Pos                 (1U)
#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
#define RTC_MISR_WUTMF_Pos                  (2U)
#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
#define RTC_MISR_TSMF_Pos                   (3U)
#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
#define RTC_MISR_TSOVMF_Pos                 (4U)
#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
#define RTC_MISR_ITSMF_Pos                  (5U)
#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
#define RTC_MISR_SSRUMF_Pos                 (6U)
#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk

/********************  Bits definition for RTC_SCR register  ******************/
#define RTC_SCR_CALRAF_Pos                  (0U)
#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
#define RTC_SCR_CALRBF_Pos                  (1U)
#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
#define RTC_SCR_CWUTF_Pos                   (2U)
#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
#define RTC_SCR_CTSF_Pos                    (3U)
#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
#define RTC_SCR_CTSOVF_Pos                  (4U)
#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CITSF_Pos                   (5U)
#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
#define RTC_SCR_CSSRUF_Pos                  (6U)
#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk

/********************  Bits definition for RTC_ALRABINR register  ******************/
#define RTC_ALRABINR_SS_Pos                 (0U)
#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk

/********************  Bits definition for RTC_ALRBBINR register  ******************/
#define RTC_ALRBBINR_SS_Pos                 (0U)
#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk


/******************************************************************************/
/*                                                                            */
/*               Secure Advanced Encryption Standard (SAES)                   */
/*                                                                            */
/******************************************************************************/
/*******************  Bits definition for SAES_CR register  *********************/
#define SAES_CR_EN_Pos                       (0U)
#define SAES_CR_EN_Msk                       (0x1UL << SAES_CR_EN_Pos)                /*!< 0x00000001 */
#define SAES_CR_EN                           SAES_CR_EN_Msk                           /*!< SAES Enable */
#define SAES_CR_DATATYPE_Pos                 (1U)
#define SAES_CR_DATATYPE_Msk                 (0x3UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
#define SAES_CR_DATATYPE                     SAES_CR_DATATYPE_Msk                     /*!< Data type selection */
#define SAES_CR_DATATYPE_0                   (0x1UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
#define SAES_CR_DATATYPE_1                   (0x2UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
#define SAES_CR_MODE_Pos                     (3U)
#define SAES_CR_MODE_Msk                     (0x3UL << SAES_CR_MODE_Pos)              /*!< 0x00000018 */
#define SAES_CR_MODE                         SAES_CR_MODE_Msk                         /*!< SAES Mode Of Operation */
#define SAES_CR_MODE_0                       (0x1UL << SAES_CR_MODE_Pos)              /*!< 0x00000008 */
#define SAES_CR_MODE_1                       (0x2UL << SAES_CR_MODE_Pos)              /*!< 0x00000010 */
#define SAES_CR_CHMOD_Pos                    (5U)
#define SAES_CR_CHMOD_Msk                    (0x803UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010060 */
#define SAES_CR_CHMOD                        SAES_CR_CHMOD_Msk                        /*!< SAES Chaining Mode */
#define SAES_CR_CHMOD_0                      (0x001UL << SAES_CR_CHMOD_Pos)           /*!< 0x00000020 */
#define SAES_CR_CHMOD_1                      (0x002UL << SAES_CR_CHMOD_Pos)           /*!< 0x00000040 */
#define SAES_CR_CHMOD_2                      (0x800UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010000 */
#define SAES_CR_DMAINEN_Pos                  (11U)
#define SAES_CR_DMAINEN_Msk                  (0x1UL << SAES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
#define SAES_CR_DMAINEN                      SAES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
#define SAES_CR_DMAOUTEN_Pos                 (12U)
#define SAES_CR_DMAOUTEN_Msk                 (0x1UL << SAES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
#define SAES_CR_DMAOUTEN                     SAES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
#define SAES_CR_GCMPH_Pos                    (13U)
#define SAES_CR_GCMPH_Msk                    (0x3UL << SAES_CR_GCMPH_Pos)             /*!< 0x00006000 */
#define SAES_CR_GCMPH                        SAES_CR_GCMPH_Msk                        /*!< GCM Phase */
#define SAES_CR_GCMPH_0                      (0x1UL << SAES_CR_GCMPH_Pos)             /*!< 0x00002000 */
#define SAES_CR_GCMPH_1                      (0x2UL << SAES_CR_GCMPH_Pos)             /*!< 0x00004000 */
#define SAES_CR_KEYSIZE_Pos                  (18U)
#define SAES_CR_KEYSIZE_Msk                  (0x1UL << SAES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
#define SAES_CR_KEYSIZE                      SAES_CR_KEYSIZE_Msk                      /*!< Key size selection */
#define SAES_CR_NPBLB_Pos                    (20U)
#define SAES_CR_NPBLB_Msk                    (0xFUL << SAES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
#define SAES_CR_NPBLB                        SAES_CR_NPBLB_Msk                        /*!< Number of padding bytes in payload last block */
#define SAES_CR_NPBLB_0                      (0x1UL << SAES_CR_NPBLB_Pos)             /*!< 0x00100000 */
#define SAES_CR_NPBLB_1                      (0x2UL << SAES_CR_NPBLB_Pos)             /*!< 0x00200000 */
#define SAES_CR_NPBLB_2                      (0x4UL << SAES_CR_NPBLB_Pos)             /*!< 0x00400000 */
#define SAES_CR_NPBLB_3                      (0x8UL << SAES_CR_NPBLB_Pos)             /*!< 0x00800000 */
#define SAES_CR_KMOD_Pos                     (24U)
#define SAES_CR_KMOD_Msk                     (0x3UL << SAES_CR_KMOD_Pos)              /*!< 0x00000006 */
#define SAES_CR_KMOD                         SAES_CR_KMOD_Msk                         /*!< Key mode selection */
#define SAES_CR_KMOD_0                       (0x1UL << SAES_CR_KMOD_Pos)              /*!< 0x01000000 */
#define SAES_CR_KMOD_1                       (0x2UL << SAES_CR_KMOD_Pos)              /*!< 0x02000000 */
#define SAES_CR_KSHAREID_Pos                 (26U)
#define SAES_CR_KSHAREID_Msk                (0x3UL << SAES_CR_KSHAREID_Pos)           /*!< 0x00000006 */
#define SAES_CR_KSHAREID                     SAES_CR_KSHAREID_Msk                      /*!< Key Shared ID */
#define SAES_CR_KEYSEL_Pos                  (28U)
#define SAES_CR_KEYSEL_Msk                  (0x7UL << SAES_CR_KEYSEL_Pos)             /*!< 0x00000006 */
#define SAES_CR_KEYSEL                       SAES_CR_KEYSEL_Msk                        /*!< Key Selection */
#define SAES_CR_KEYSEL_0                    (0x1UL << SAES_CR_KEYSEL_Pos)             /*!< 0x02000000 */
#define SAES_CR_KEYSEL_1                    (0x2UL << SAES_CR_KEYSEL_Pos)             /*!< 0x02000000 */
#define SAES_CR_KEYSEL_2                    (0x4UL << SAES_CR_KEYSEL_Pos)             /*!< 0x02000000 */
#define SAES_CR_IPRST_Pos                    (31U)
#define SAES_CR_IPRST_Msk                    (0x1UL << SAES_CR_IPRST_Pos)             /*!< 0x80000001 */
#define SAES_CR_IPRST                        SAES_CR_IPRST_Msk                        /*!< SAES IP software reset */

/*******************  Bits definition for SAES_SR register  *********************/
#define SAES_SR_CCF_Pos                      (0U)
#define SAES_SR_CCF_Msk                      (0x1UL << SAES_SR_CCF_Pos)               /*!< 0x00000001 */
#define SAES_SR_CCF                          SAES_SR_CCF_Msk                          /*!< Computation Complete Flag */
#define SAES_SR_RDERR_Pos                    (1U)
#define SAES_SR_RDERR_Msk                    (0x1UL << SAES_SR_RDERR_Pos)             /*!< 0x00000002 */
#define SAES_SR_RDERR                        SAES_SR_RDERR_Msk                        /*!< Read Error Flag */
#define SAES_SR_WRERR_Pos                    (2U)
#define SAES_SR_WRERR_Msk                    (0x1UL << SAES_SR_WRERR_Pos)             /*!< 0x00000004 */
#define SAES_SR_WRERR                        SAES_SR_WRERR_Msk                        /*!< Write Error Flag */
#define SAES_SR_BUSY_Pos                     (3U)
#define SAES_SR_BUSY_Msk                     (0x1UL << SAES_SR_BUSY_Pos)              /*!< 0x00000008 */
#define SAES_SR_BUSY                         SAES_SR_BUSY_Msk                         /*!< Busy Flag */
#define SAES_SR_KEYVALID_Pos                 (7U)
#define SAES_SR_KEYVALID_Msk                 (0x1UL << SAES_SR_KEYVALID_Pos)          /*!< 0x00000008 */
#define SAES_SR_KEYVALID                     SAES_SR_KEYVALID_Msk                     /*!< KEYVALID Flag */

/*******************  Bits definition for SAES_DINR register  *******************/
#define SAES_DINR_Pos                        (0U)
#define SAES_DINR_Msk                        (0xFFFFFFFFUL << SAES_DINR_Pos)          /*!< 0xFFFFFFFF */
#define SAES_DINR                            SAES_DINR_Msk                            /*!< SAES Data Input Register */

/*******************  Bits definition for SAES_DOUTR register  ******************/
#define SAES_DOUTR_Pos                       (0U)
#define SAES_DOUTR_Msk                       (0xFFFFFFFFUL << SAES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
#define SAES_DOUTR                           SAES_DOUTR_Msk                           /*!< SAES Data Output Register */

/*******************  Bits definition for SAES_KEYR0 register  ******************/
#define SAES_KEYR0_Pos                       (0U)
#define SAES_KEYR0_Msk                       (0xFFFFFFFFUL << SAES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR0                           SAES_KEYR0_Msk                           /*!< SAES Key Register 0 */

/*******************  Bits definition for SAES_KEYR1 register  ******************/
#define SAES_KEYR1_Pos                       (0U)
#define SAES_KEYR1_Msk                       (0xFFFFFFFFUL << SAES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR1                           SAES_KEYR1_Msk                           /*!< SAES Key Register 1 */

/*******************  Bits definition for SAES_KEYR2 register  ******************/
#define SAES_KEYR2_Pos                       (0U)
#define SAES_KEYR2_Msk                       (0xFFFFFFFFUL << SAES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR2                           SAES_KEYR2_Msk                           /*!< SAES Key Register 2 */

/*******************  Bits definition for SAES_KEYR3 register  ******************/
#define SAES_KEYR3_Pos                       (0U)
#define SAES_KEYR3_Msk                       (0xFFFFFFFFUL << SAES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR3                           SAES_KEYR3_Msk                           /*!< SAES Key Register 3 */

/*******************  Bits definition for SAES_KEYR4 register  ******************/
#define SAES_KEYR4_Pos                       (0U)
#define SAES_KEYR4_Msk                       (0xFFFFFFFFUL << SAES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR4                           SAES_KEYR4_Msk                           /*!< SAES Key Register 4 */

/*******************  Bits definition for SAES_KEYR5 register  ******************/
#define SAES_KEYR5_Pos                       (0U)
#define SAES_KEYR5_Msk                       (0xFFFFFFFFUL << SAES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR5                           SAES_KEYR5_Msk                           /*!< SAES Key Register 5 */

/*******************  Bits definition for SAES_KEYR6 register  ******************/
#define SAES_KEYR6_Pos                       (0U)
#define SAES_KEYR6_Msk                       (0xFFFFFFFFUL << SAES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR6                           SAES_KEYR6_Msk                           /*!< SAES Key Register 6 */

/*******************  Bits definition for SAES_KEYR7 register  ******************/
#define SAES_KEYR7_Pos                       (0U)
#define SAES_KEYR7_Msk                       (0xFFFFFFFFUL << SAES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
#define SAES_KEYR7                           SAES_KEYR7_Msk                           /*!< SAES Key Register 7 */

/*******************  Bits definition for SAES_IVR0 register   ******************/
#define SAES_IVR0_Pos                        (0U)
#define SAES_IVR0_Msk                        (0xFFFFFFFFUL << SAES_IVR0_Pos)          /*!< 0xFFFFFFFF */
#define SAES_IVR0                            SAES_IVR0_Msk                            /*!< SAES Initialization Vector Register 0 */

/*******************  Bits definition for SAES_IVR1 register   ******************/
#define SAES_IVR1_Pos                        (0U)
#define SAES_IVR1_Msk                        (0xFFFFFFFFUL << SAES_IVR1_Pos)          /*!< 0xFFFFFFFF */
#define SAES_IVR1                            SAES_IVR1_Msk                            /*!< SAES Initialization Vector Register 1 */

/*******************  Bits definition for SAES_IVR2 register   ******************/
#define SAES_IVR2_Pos                        (0U)
#define SAES_IVR2_Msk                        (0xFFFFFFFFUL << SAES_IVR2_Pos)          /*!< 0xFFFFFFFF */
#define SAES_IVR2                            SAES_IVR2_Msk                            /*!< SAES Initialization Vector Register 2 */

/*******************  Bits definition for SAES_IVR3 register   ******************/
#define SAES_IVR3_Pos                        (0U)
#define SAES_IVR3_Msk                        (0xFFFFFFFFUL << SAES_IVR3_Pos)          /*!< 0xFFFFFFFF */
#define SAES_IVR3                            SAES_IVR3_Msk                            /*!< SAES Initialization Vector Register 3 */

/*******************  Bit definition for SAES_SUSP0R register  ******************/
#define SAES_SUSP0R_Pos                      (0U)
#define SAES_SUSP0R_Msk                      (0xFFFFFFFFUL << SAES_SUSP0R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP0R                          SAES_SUSP0R_Msk                          /*!< SAES Suspend registers 0 */

/*******************  Bit definition for SAES_SUSP1R register  ******************/
#define SAES_SUSP1R_Pos                      (0U)
#define SAES_SUSP1R_Msk                      (0xFFFFFFFFUL << SAES_SUSP1R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP1R                          SAES_SUSP1R_Msk                          /*!< SAES Suspend registers 1 */

/*******************  Bit definition for SAES_SUSP2R register  ******************/
#define SAES_SUSP2R_Pos                      (0U)
#define SAES_SUSP2R_Msk                      (0xFFFFFFFFUL << SAES_SUSP2R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP2R                          SAES_SUSP2R_Msk                          /*!< SAES Suspend registers 2 */

/*******************  Bit definition for SAES_SUSP3R register  ******************/
#define SAES_SUSP3R_Pos                      (0U)
#define SAES_SUSP3R_Msk                      (0xFFFFFFFFUL << SAES_SUSP3R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP3R                          SAES_SUSP3R_Msk                          /*!< SAES Suspend registers 3 */

/*******************  Bit definition for SAES_SUSP4R register  ******************/
#define SAES_SUSP4R_Pos                      (0U)
#define SAES_SUSP4R_Msk                      (0xFFFFFFFFUL << SAES_SUSP4R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP4R                          SAES_SUSP4R_Msk                          /*!< SAES Suspend registers 4 */

/*******************  Bit definition for SAES_SUSP5R register  ******************/
#define SAES_SUSP5R_Pos                      (0U)
#define SAES_SUSP5R_Msk                      (0xFFFFFFFFUL << SAES_SUSP5R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP5R                          SAES_SUSP5R_Msk                          /*!< AES Suspend registers 5 */

/*******************  Bit definition for SAES_SUSP6R register  ******************/
#define SAES_SUSP6R_Pos                      (0U)
#define SAES_SUSP6R_Msk                      (0xFFFFFFFFUL << SAES_SUSP6R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP6R                          SAES_SUSP6R_Msk                          /*!< SAES Suspend registers 6 */

/*******************  Bit definition for SAES_SUSP7R register  ******************/
#define SAES_SUSP7R_Pos                      (0U)
#define SAES_SUSP7R_Msk                      (0xFFFFFFFFUL << SAES_SUSP7R_Pos)        /*!< 0xFFFFFFFF */
#define SAES_SUSP7R                          SAES_SUSP7R_Msk                          /*!< SAES Suspend registers 7 */

/*******************  Bits definition for SAES_IER register     ******************/
#define SAES_IER_CCFIE_Pos                   (0U)
#define SAES_IER_CCFIE_Msk                   (0x1UL << SAES_IER_CCFIE_Pos)            /*!< 0x00000001 */
#define SAES_IER_CCFIE                       SAES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
#define SAES_IER_RWEIE_Pos                   (1U)
#define SAES_IER_RWEIE_Msk                   (0x1UL << SAES_IER_RWEIE_Pos)            /*!< 0x00000002 */
#define SAES_IER_RWEIE                       SAES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
#define SAES_IER_KEIE_Pos                    (2U)
#define SAES_IER_KEIE_Msk                    (0x1UL << SAES_IER_KEIE_Pos)             /*!< 0x00000004 */
#define SAES_IER_KEIE                        SAES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
#define SAES_IER_RNGEIE_Pos                  (3U)
#define SAES_IER_RNGEIE_Msk                  (0x1UL << SAES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
#define SAES_IER_RNGEIE                      SAES_IER_RNGEIE_Msk                      /*!< Rng error interrupt enable */

/*******************  Bits definition for SAES_ISR register     ******************/
#define SAES_ISR_CCF_Pos                     (0U)
#define SAES_ISR_CCF_Msk                     (0x1UL << SAES_ISR_CCF_Pos)              /*!< 0x00000001 */
#define SAES_ISR_CCF                         SAES_ISR_CCF_Msk                         /*!< Computation complete flag */
#define SAES_ISR_RWEIF_Pos                   (1U)
#define SAES_ISR_RWEIF_Msk                   (0x1UL << SAES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
#define SAES_ISR_RWEIF                       SAES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
#define SAES_ISR_KEIF_Pos                    (2U)
#define SAES_ISR_KEIF_Msk                    (0x1UL << SAES_ISR_KEIF_Pos)             /*!< 0x00000004 */
#define SAES_ISR_KEIF                        SAES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
#define SAES_ISR_RNGEIF_Pos                  (3U)
#define SAES_ISR_RNGEIF_Msk                  (0x1UL << SAES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
#define SAES_ISR_RNGEIF                      SAES_ISR_RNGEIF_Msk                      /*!< Rng error interrupt flag */

/*******************  Bits definition for SAES_ICR register     ******************/
#define SAES_ICR_CCF_Pos                     (0U)
#define SAES_ICR_CCF_Msk                     (0x1UL << SAES_ICR_CCF_Pos)              /*!< 0x00000001 */
#define SAES_ICR_CCF                         SAES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
#define SAES_ICR_RWEIF_Pos                   (1U)
#define SAES_ICR_RWEIF_Msk                   (0x1UL << SAES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
#define SAES_ICR_RWEIF                       SAES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
#define SAES_ICR_KEIF_Pos                    (2U)
#define SAES_ICR_KEIF_Msk                    (0x1UL << SAES_ICR_KEIF_Pos)             /*!< 0x00000004 */
#define SAES_ICR_KEIF                        SAES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
#define SAES_ICR_RNGEIF_Pos                  (3U)
#define SAES_ICR_RNGEIF_Msk                  (0x1UL << SAES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
#define SAES_ICR_RNGEIF                       SAES_ICR_RNGEIF_Msk                     /*!< Rng error interrupt flag clear */

/******************************************************************************/
/*                                                                            */
/*                          Serial Audio Interface                            */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for SAI_GCR register  *******************/
#define SAI_GCR_SYNCIN_Pos                  (0U)
#define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
#define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
#define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos                 (4U)
#define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */

/*******************  Bit definition for SAI_xCR1 register  *******************/
#define SAI_xCR1_MODE_Pos                   (0U)
#define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
#define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
#define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
#define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos                 (2U)
#define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
#define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos                     (5U)
#define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
#define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
#define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
#define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos               (8U)
#define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
#define SAI_xCR1_CKSTR_Pos                  (9U)
#define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
#define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
#define SAI_xCR1_SYNCEN_Pos                 (10U)
#define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos                   (12U)
#define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
#define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
#define SAI_xCR1_OUTDRIV_Pos                (13U)
#define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
#define SAI_xCR1_SAIEN_Pos                  (16U)
#define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
#define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
#define SAI_xCR1_DMAEN_Pos                  (17U)
#define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
#define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
#define SAI_xCR1_NODIV_Pos                  (19U)
#define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
#define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
#define SAI_xCR1_MCKDIV_Pos                 (20U)
#define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
#define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
#define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
#define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
#define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
#define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
#define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
#define SAI_xCR1_OSR_Pos                    (26U)
#define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
#define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos                  (27U)
#define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
#define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */

/*******************  Bit definition for SAI_xCR2 register  *******************/
#define SAI_xCR2_FTH_Pos                    (0U)
#define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
#define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
#define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
#define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
#define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos                 (3U)
#define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
#define SAI_xCR2_TRIS_Pos                   (4U)
#define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
#define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos                   (5U)
#define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
#define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
#define SAI_xCR2_MUTEVAL_Pos                (6U)
#define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
#define SAI_xCR2_MUTECNT_Pos                (7U)
#define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos                    (13U)
#define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
#define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
#define SAI_xCR2_COMP_Pos                   (14U)
#define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
#define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
#define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */

/******************  Bit definition for SAI_xFRCR register  *******************/
#define SAI_xFRCR_FRL_Pos                   (0U)
#define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
#define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
#define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos                 (8U)
#define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
#define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos                 (16U)
#define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos                 (17U)
#define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
#define SAI_xFRCR_FSOFF_Pos                 (18U)
#define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */

/******************  Bit definition for SAI_xSLOTR register  *******************/
#define SAI_xSLOTR_FBOFF_Pos                (0U)
#define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
#define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos               (6U)
#define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
#define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos               (8U)
#define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
#define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos               (16U)
#define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */

/*******************  Bit definition for SAI_xIMR register  *******************/
#define SAI_xIMR_OVRUDRIE_Pos               (0U)
#define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
#define SAI_xIMR_MUTEDETIE_Pos              (1U)
#define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
#define SAI_xIMR_WCKCFGIE_Pos               (2U)
#define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
#define SAI_xIMR_FREQIE_Pos                 (3U)
#define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
#define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
#define SAI_xIMR_CNRDYIE_Pos                (4U)
#define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
#define SAI_xIMR_AFSDETIE_Pos               (5U)
#define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
#define SAI_xIMR_LFSDETIE_Pos               (6U)
#define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */

/********************  Bit definition for SAI_xSR register  *******************/
#define SAI_xSR_OVRUDR_Pos                  (0U)
#define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
#define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
#define SAI_xSR_MUTEDET_Pos                 (1U)
#define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
#define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
#define SAI_xSR_WCKCFG_Pos                  (2U)
#define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
#define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
#define SAI_xSR_FREQ_Pos                    (3U)
#define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
#define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
#define SAI_xSR_CNRDY_Pos                   (4U)
#define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
#define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
#define SAI_xSR_AFSDET_Pos                  (5U)
#define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
#define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
#define SAI_xSR_LFSDET_Pos                  (6U)
#define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
#define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
#define SAI_xSR_FLVL_Pos                    (16U)
#define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
#define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
#define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
#define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
#define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */

/******************  Bit definition for SAI_xCLRFR register  ******************/
#define SAI_xCLRFR_COVRUDR_Pos              (0U)
#define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
#define SAI_xCLRFR_CMUTEDET_Pos             (1U)
#define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
#define SAI_xCLRFR_CWCKCFG_Pos              (2U)
#define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
#define SAI_xCLRFR_CCNRDY_Pos               (4U)
#define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
#define SAI_xCLRFR_CAFSDET_Pos              (5U)
#define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
#define SAI_xCLRFR_CLFSDET_Pos              (6U)
#define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */

/******************  Bit definition for SAI_xDR register  ******************/
#define SAI_xDR_DATA_Pos                    (0U)
#define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA                        SAI_xDR_DATA_Msk

/******************  Bit definition for SAI_PDMCR register  *******************/
#define SAI_PDMCR_PDMEN_Pos                 (0U)
#define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos                (4U)
#define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos                 (8U)
#define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos                 (9U)
#define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */

/******************  Bit definition for SAI_PDMDLY register  ******************/
#define SAI_PDMDLY_DLYM1L_Pos               (0U)
#define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos               (4U)
#define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos               (8U)
#define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos               (12U)
#define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos               (16U)
#define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos               (20U)
#define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos               (24U)
#define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos               (28U)
#define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */


/******************************************************************************/
/*                                                                            */
/*                                 SBS                                        */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SBS_BOOTSR register  ******************/
#define SBS_BOOTSR_INITVTOR_Pos          (0U)
#define SBS_BOOTSR_INITVTOR_Msk          (0xFFFFFFFFUL << SBS_BOOTSR_INITVTOR_Pos)   /*!< 0xFFFFFFFF */
#define SBS_BOOTSR_INITVTOR              SBS_BOOTSR_INITVTOR_Msk                     /*!< Initial vector for Cortex-M7 */

/******************  Bit definition for SBS_HDPLCR register  ******************/
#define SBS_HDPLCR_INCR_HDPL_Pos         (0U)
#define SBS_HDPLCR_INCR_HDPL_Msk         (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos)        /*!< 0x000000FF */
#define SBS_HDPLCR_INCR_HDPL             SBS_HDPLCR_INCR_HDPL_Msk                    /*!< Increment HDPL */

/******************  Bit definition for SBS_HDPLSR register  ******************/
#define SBS_HDPLSR_HDPL_Pos              (0U)
#define SBS_HDPLSR_HDPL_Msk              (0xFFUL << SBS_HDPLSR_HDPL_Pos)             /*!< 0x000000FF */
#define SBS_HDPLSR_HDPL                  SBS_HDPLSR_HDPL_Msk                         /*!< Hide protection level */

/******************  Bit definition for SBS_DBGCR register  *******************/
#define SBS_DBGCR_AP_UNLOCK_Pos          (0U)
#define SBS_DBGCR_AP_UNLOCK_Msk          (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos)         /*!< 0x000000FF */
#define SBS_DBGCR_AP_UNLOCK              SBS_DBGCR_AP_UNLOCK_Msk                     /*!< Access port unlock */
#define SBS_DBGCR_DBG_UNLOCK_Pos         (8U)
#define SBS_DBGCR_DBG_UNLOCK_Msk         (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos)        /*!< 0x0000FF00 */
#define SBS_DBGCR_DBG_UNLOCK             SBS_DBGCR_DBG_UNLOCK_Msk                    /*!< Debug unlock */
#define SBS_DBGCR_DBG_AUTH_HDPL_Pos      (16U)
#define SBS_DBGCR_DBG_AUTH_HDPL_Msk      (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos)     /*!< 0x00FF0000 */
#define SBS_DBGCR_DBG_AUTH_HDPL          SBS_DBGCR_DBG_AUTH_HDPL_Msk                 /*!< Authenticated debug hide protection level */

/*****************  Bit definition for SBS_DBGLOCKR register  *****************/
#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos     (0U)
#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk     (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos)    /*!< 0x000000FF */
#define SBS_DBGLOCKR_DBGCFG_LOCK         SBS_DBGLOCKR_DBGCFG_LOCK_Msk                /*!< Debug configuration lock */

/******************  Bit definition for SBS_RSSCMDR register  *****************/
#define SBS_RSSCMDR_RSSCMD_Pos           (0U)
#define SBS_RSSCMDR_RSSCMD_Msk           (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos)        /*!< 0x0000FFFF */
#define SBS_RSSCMDR_RSSCMD               SBS_RSSCMDR_RSSCMD_Msk                      /*!< RSS command */

/******************  Bit definition for SBS_PMCR register  ********************/
#define SBS_PMCR_BOOSTEN_Pos             (8U)
#define SBS_PMCR_BOOSTEN_Msk             (0x1UL << SBS_PMCR_BOOSTEN_Pos)             /*!< 0x00000100 */
#define SBS_PMCR_BOOSTEN                 SBS_PMCR_BOOSTEN_Msk                        /*!< Booster enable */
#define SBS_PMCR_BOOSTVDDSEL_Pos         (9U)
#define SBS_PMCR_BOOSTVDDSEL_Msk         (0x1UL << SBS_PMCR_BOOSTVDDSEL_Pos)         /*!< 0x00000200 */
#define SBS_PMCR_BOOSTVDDSEL             SBS_PMCR_BOOSTVDDSEL_Msk                    /*!< Booster Vdd selection */
#define SBS_PMCR_ETH_PHYSEL_Pos          (21U)
#define SBS_PMCR_ETH_PHYSEL_Msk          (0x7UL << SBS_PMCR_ETH_PHYSEL_Pos)          /*!< 0x00E00000 */
#define SBS_PMCR_ETH_PHYSEL              SBS_PMCR_ETH_PHYSEL_Msk                     /*!< Ethernet PHY interface selection */
#define SBS_PMCR_ETH_PHYSEL_0            (0x1UL << SBS_PMCR_ETH_PHYSEL_Pos)          /*!< 0x00200000 */
#define SBS_PMCR_ETH_PHYSEL_1            (0x2UL << SBS_PMCR_ETH_PHYSEL_Pos)          /*!< 0x00400000 */
#define SBS_PMCR_ETH_PHYSEL_2            (0x4UL << SBS_PMCR_ETH_PHYSEL_Pos)          /*!< 0x00800000 */
#define SBS_PMCR_AXISRAM_WS_Pos          (28U)
#define SBS_PMCR_AXISRAM_WS_Msk          (0x1UL << SBS_PMCR_AXISRAM_WS_Pos)          /*!< 0x10000000 */
#define SBS_PMCR_AXISRAM_WS              SBS_PMCR_AXISRAM_WS_Msk                     /*!< AXISRAM wait state */

/******************  Bit definition for SBS_FPUIMR register  ******************/
#define SBS_FPUIMR_FPU_IE_Pos            (0U)
#define SBS_FPUIMR_FPU_IE_Msk            (0x3FUL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x0000003F */
#define SBS_FPUIMR_FPU_IE                SBS_FPUIMR_FPU_IE_Msk                       /*!<  All FPU interrupts enable */
#define SBS_FPUIMR_FPU_IE_0_Pos          (0U)
#define SBS_FPUIMR_FPU_IE_0_Msk          (0x1UL << SBS_FPUIMR_FPU_IE_0_Pos)          /*!< 0x00000001 */
#define SBS_FPUIMR_FPU_IE_0              SBS_FPUIMR_FPU_IE_0_Msk                     /*!< Invalid operation Interrupt enable */
#define SBS_FPUIMR_FPU_IE_1_Pos          (1U)
#define SBS_FPUIMR_FPU_IE_1_Msk          (0x1UL << SBS_FPUIMR_FPU_IE_1_Pos)          /*!< 0x00000002 */
#define SBS_FPUIMR_FPU_IE_1              SBS_FPUIMR_FPU_IE_1_Msk                     /*!< Divide-by-zero Interrupt enable */
#define SBS_FPUIMR_FPU_IE_2_Pos          (2U)
#define SBS_FPUIMR_FPU_IE_2_Msk          (0x1UL << SBS_FPUIMR_FPU_IE_2_Pos)          /*!< 0x00000004 */
#define SBS_FPUIMR_FPU_IE_2              SBS_FPUIMR_FPU_IE_2_Msk                     /*!< Underflow Interrupt enable */
#define SBS_FPUIMR_FPU_IE_3_Pos          (3U)
#define SBS_FPUIMR_FPU_IE_3_Msk          (0x1UL << SBS_FPUIMR_FPU_IE_3_Pos)          /*!< 0x00000008 */
#define SBS_FPUIMR_FPU_IE_3              SBS_FPUIMR_FPU_IE_3_Msk                     /*!< Overflow Interrupt enable */
#define SBS_FPUIMR_FPU_IE_4_Pos          (4U)
#define SBS_FPUIMR_FPU_IE_4_Msk          (0x1UL << SBS_FPUIMR_FPU_IE_4_Pos)          /*!< 0x00000010 */
#define SBS_FPUIMR_FPU_IE_4              SBS_FPUIMR_FPU_IE_4_Msk                     /*!< Input denormal Interrupt enable */
#define SBS_FPUIMR_FPU_IE_5_Pos          (5U)
#define SBS_FPUIMR_FPU_IE_5_Msk          (0x1UL << SBS_FPUIMR_FPU_IE_5_Pos)          /*!< 0x00000020 */
#define SBS_FPUIMR_FPU_IE_5              SBS_FPUIMR_FPU_IE_5_Msk                     /*!< Inexact Interrupt enable */

/******************  Bit definition for SBS_MESR register  ********************/
#define SBS_MESR_MEF_Pos                 (0U)
#define SBS_MESR_MEF_Msk                 (0x1UL << SBS_MESR_MEF_Pos)                 /*!< 0x00000001 */
#define SBS_MESR_MEF                     SBS_MESR_MEF_Msk                            /*!< Memory erase flag */

/******************  Bit definition for SBS_CCCSR register  *******************/
#define SBS_CCCSR_COMP_EN_Pos            (0U)
#define SBS_CCCSR_COMP_EN_Msk            (0x1UL << SBS_CCCSR_COMP_EN_Pos)            /*!< 0x00000001 */
#define SBS_CCCSR_COMP_EN                SBS_CCCSR_COMP_EN_Msk                       /*!< Compensation cell enable */
#define SBS_CCCSR_COMP_CODESEL_Pos       (1U)
#define SBS_CCCSR_COMP_CODESEL_Msk       (0x1UL << SBS_CCCSR_COMP_CODESEL_Pos)       /*!< 0x00000002 */
#define SBS_CCCSR_COMP_CODESEL           SBS_CCCSR_COMP_CODESEL_Msk                  /*!< Compensation cell code selection */
#define SBS_CCCSR_XSPI1_COMP_EN_Pos      (2U)
#define SBS_CCCSR_XSPI1_COMP_EN_Msk      (0x1UL << SBS_CCCSR_XSPI1_COMP_EN_Pos)      /*!< 0x00000004 */
#define SBS_CCCSR_XSPI1_COMP_EN          SBS_CCCSR_XSPI1_COMP_EN_Msk                 /*!< XSPIM_P1 compensation cell enable */
#define SBS_CCCSR_XSPI1_COMP_CODESEL_Pos (3U)
#define SBS_CCCSR_XSPI1_COMP_CODESEL_Msk (0x1UL << SBS_CCCSR_XSPI1_COMP_CODESEL_Pos) /*!< 0x00000008 */
#define SBS_CCCSR_XSPI1_COMP_CODESEL     SBS_CCCSR_XSPI1_COMP_CODESEL_Msk            /*!< XSPIM_P1 compensation cell code selection */
#define SBS_CCCSR_XSPI2_COMP_EN_Pos      (4U)
#define SBS_CCCSR_XSPI2_COMP_EN_Msk      (0x1UL << SBS_CCCSR_XSPI2_COMP_EN_Pos)      /*!< 0x00000010 */
#define SBS_CCCSR_XSPI2_COMP_EN          SBS_CCCSR_XSPI2_COMP_EN_Msk                 /*!< XSPIM_P2 compensation cell enable */
#define SBS_CCCSR_XSPI2_COMP_CODESEL_Pos (5U)
#define SBS_CCCSR_XSPI2_COMP_CODESEL_Msk (0x1UL << SBS_CCCSR_XSPI2_COMP_CODESEL_Pos) /*!< 0x00000020 */
#define SBS_CCCSR_XSPI2_COMP_CODESEL     SBS_CCCSR_XSPI2_COMP_CODESEL_Msk            /*!< XSPIM_P2 compensation cell code selection */
#define SBS_CCCSR_COMP_RDY_Pos           (8U)
#define SBS_CCCSR_COMP_RDY_Msk           (0x1UL << SBS_CCCSR_COMP_RDY_Pos)           /*!< 0x00000100 */
#define SBS_CCCSR_COMP_RDY               SBS_CCCSR_COMP_RDY_Msk                      /*!< Compensation cell ready */
#define SBS_CCCSR_XSPI1_COMP_RDY_Pos     (9U)
#define SBS_CCCSR_XSPI1_COMP_RDY_Msk     (0x1UL << SBS_CCCSR_XSPI1_COMP_RDY_Pos)     /*!< 0x00000200 */
#define SBS_CCCSR_XSPI1_COMP_RDY         SBS_CCCSR_XSPI1_COMP_RDY_Msk                /*!< XSPIM_P1 compensation cell ready */
#define SBS_CCCSR_XSPI2_COMP_RDY_Pos     (10U)
#define SBS_CCCSR_XSPI2_COMP_RDY_Msk     (0x1UL << SBS_CCCSR_XSPI2_COMP_RDY_Pos)     /*!< 0x00000400 */
#define SBS_CCCSR_XSPI2_COMP_RDY         SBS_CCCSR_XSPI2_COMP_RDY_Msk                /*!< XSPIM_P2 compensation cell ready */
#define SBS_CCCSR_IOHSLV_Pos             (16U)
#define SBS_CCCSR_IOHSLV_Msk             (0x1UL << SBS_CCCSR_IOHSLV_Pos)             /*!< 0x00010000 */
#define SBS_CCCSR_IOHSLV                 SBS_CCCSR_IOHSLV_Msk                        /*!< I/O high speed at low voltage */
#define SBS_CCCSR_XSPI1_IOHSLV_Pos       (17U)
#define SBS_CCCSR_XSPI1_IOHSLV_Msk       (0x1UL << SBS_CCCSR_XSPI1_IOHSLV_Pos)       /*!< 0x00020000 */
#define SBS_CCCSR_XSPI1_IOHSLV           SBS_CCCSR_XSPI1_IOHSLV_Msk                  /*!< XSPIM_P1 I/O high speed at low voltage */
#define SBS_CCCSR_XSPI2_IOHSLV_Pos       (18U)
#define SBS_CCCSR_XSPI2_IOHSLV_Msk       (0x1UL << SBS_CCCSR_XSPI2_IOHSLV_Pos)       /*!< 0x00040000 */
#define SBS_CCCSR_XSPI2_IOHSLV           SBS_CCCSR_XSPI2_IOHSLV_Msk                  /*!< XSPIM_P2 I/O high speed at low voltage */

/*****************  Bit definition for SBS_CCVALR register  *******************/
#define SBS_CCVALR_NSRC_Pos              (0U)
#define SBS_CCVALR_NSRC_Msk              (0xFUL << SBS_CCVALR_NSRC_Pos)              /*!< 0x0000000F */
#define SBS_CCVALR_NSRC                  SBS_CCVALR_NSRC_Msk                         /*!< NMOS transistors slew-rate compensation */
#define SBS_CCVALR_PSRC_Pos              (4U)
#define SBS_CCVALR_PSRC_Msk              (0xFUL << SBS_CCVALR_PSRC_Pos)              /*!< 0x000000F0 */
#define SBS_CCVALR_PSRC                  SBS_CCVALR_PSRC_Msk                         /*!< PMOS transistors slew-rate compensation */
#define SBS_CCVALR_XSPI1_NSRC_Pos        (8U)
#define SBS_CCVALR_XSPI1_NSRC_Msk        (0xFUL << SBS_CCVALR_XSPI1_NSRC_Pos)        /*!< 0x00000F00 */
#define SBS_CCVALR_XSPI1_NSRC            SBS_CCVALR_XSPI1_NSRC_Msk                   /*!< XSPIM_P1 NMOS transistors slew-rate compensation */
#define SBS_CCVALR_XSPI1_PSRC_Pos        (12U)
#define SBS_CCVALR_XSPI1_PSRC_Msk        (0xFUL << SBS_CCVALR_XSPI1_PSRC_Pos)        /*!< 0x0000F000 */
#define SBS_CCVALR_XSPI1_PSRC            SBS_CCVALR_XSPI1_PSRC_Msk                   /*!< XSPIM_P1 PMOS transistors slew-rate compensation */
#define SBS_CCVALR_XSPI2_NSRC_Pos        (16U)
#define SBS_CCVALR_XSPI2_NSRC_Msk        (0xFUL << SBS_CCVALR_XSPI2_NSRC_Pos)        /*!< 0x000F0000 */
#define SBS_CCVALR_XSPI2_NSRC            SBS_CCVALR_XSPI2_NSRC_Msk                   /*!< XSPIM_P2 NMOS transistors slew-rate compensation */
#define SBS_CCVALR_XSPI2_PSRC_Pos        (20U)
#define SBS_CCVALR_XSPI2_PSRC_Msk        (0xFUL << SBS_CCVALR_XSPI2_PSRC_Pos)        /*!< 0x00F00000 */
#define SBS_CCVALR_XSPI2_PSRC            SBS_CCVALR_XSPI2_PSRC_Msk                   /*!< XSPIM_P2 PMOS transistors slew-rate compensation */

/****************  Bit definition for SBS_CCSWVALR register  *******************/
#define SBS_CCSWVALR_SW_NSRC_Pos         (0U)
#define SBS_CCSWVALR_SW_NSRC_Msk         (0xFUL << SBS_CCSWVALR_SW_NSRC_Pos)         /*!< 0x0000000F */
#define SBS_CCSWVALR_SW_NSRC             SBS_CCSWVALR_SW_NSRC_Msk                    /*!< Software NMOS transistors slew-rate compensation */
#define SBS_CCSWVALR_SW_PSRC_Pos         (4U)
#define SBS_CCSWVALR_SW_PSRC_Msk         (0xFUL << SBS_CCSWVALR_SW_PSRC_Pos)         /*!< 0x000000F0 */
#define SBS_CCSWVALR_SW_PSRC             SBS_CCSWVALR_SW_PSRC_Msk                    /*!< Software PMOS transistors slew-rate compensation */
#define SBS_CCSWVALR_XSPI1_SW_NSRC_Pos   (8U)
#define SBS_CCSWVALR_XSPI1_SW_NSRC_Msk   (0xFUL << SBS_CCSWVALR_XSPI1_SW_NSRC_Pos)   /*!< 0x00000F00 */
#define SBS_CCSWVALR_XSPI1_SW_NSRC       SBS_CCSWVALR_XSPI1_SW_NSRC_Msk              /*!< XSPIM_P1 software NMOS transistors slew-rate compensation */
#define SBS_CCSWVALR_XSPI1_SW_PSRC_Pos   (12U)
#define SBS_CCSWVALR_XSPI1_SW_PSRC_Msk   (0xFUL << SBS_CCSWVALR_XSPI1_SW_PSRC_Pos)   /*!< 0x0000F000 */
#define SBS_CCSWVALR_XSPI1_SW_PSRC       SBS_CCSWVALR_XSPI1_SW_PSRC_Msk              /*!< XSPIM_P1 software PMOS transistors slew-rate compensation */
#define SBS_CCSWVALR_XSPI2_SW_NSRC_Pos   (16U)
#define SBS_CCSWVALR_XSPI2_SW_NSRC_Msk   (0xFUL << SBS_CCSWVALR_XSPI2_SW_NSRC_Pos)   /*!< 0x000F0000 */
#define SBS_CCSWVALR_XSPI2_SW_NSRC       SBS_CCSWVALR_XSPI2_SW_NSRC_Msk              /*!< XSPIM_P2 software NMOS transistors slew-rate compensation */
#define SBS_CCSWVALR_XSPI2_SW_PSRC_Pos   (20U)
#define SBS_CCSWVALR_XSPI2_SW_PSRC_Msk   (0xFUL << SBS_CCSWVALR_XSPI2_SW_PSRC_Pos)   /*!< 0x00F00000 */
#define SBS_CCSWVALR_XSPI2_SW_PSRC       SBS_CCSWVALR_XSPI2_SW_PSRC_Msk              /*!< XSPIM_P2 software PMOS transistors slew-rate compensation */

/********************  Bit definition for SBS_BKLOCKR register  ****************/
#define SBS_BKLOCKR_PVD_BL_Pos           (2U)
#define SBS_BKLOCKR_PVD_BL_Msk           (0x1UL << SBS_BKLOCKR_PVD_BL_Pos)           /*!< 0x00000004 */
#define SBS_BKLOCKR_PVD_BL               SBS_BKLOCKR_PVD_BL_Msk                      /*!< PVD break lock */
#define SBS_BKLOCKR_FLASHECC_BL_Pos      (3U)
#define SBS_BKLOCKR_FLASHECC_BL_Msk      (0x1UL << SBS_BKLOCKR_FLASHECC_BL_Pos)      /*!< 0x00000008 */
#define SBS_BKLOCKR_FLASHECC_BL          SBS_BKLOCKR_FLASHECC_BL_Msk                 /*!< Flash ECC error break lock */
#define SBS_BKLOCKR_CM7LCKUP_BL_Pos      (6U)
#define SBS_BKLOCKR_CM7LCKUP_BL_Msk      (0x1UL << SBS_BKLOCKR_CM7LCKUP_BL_Pos)      /*!< 0x00000040 */
#define SBS_BKLOCKR_CM7LCKUP_BL          SBS_BKLOCKR_CM7LCKUP_BL_Msk                 /*!< Cortex-M7 lockup break lock */
#define SBS_BKLOCKR_BKRAMECC_BL_Pos      (7U)
#define SBS_BKLOCKR_BKRAMECC_BL_Msk      (0x1UL << SBS_BKLOCKR_BKRAMECC_BL_Pos)      /*!< 0x00000080 */
#define SBS_BKLOCKR_BKRAMECC_BL          SBS_BKLOCKR_BKRAMECC_BL_Msk                 /*!< Backup RAM ECC error break lock */
#define SBS_BKLOCKR_DTCMECC_BL_Pos       (13U)
#define SBS_BKLOCKR_DTCMECC_BL_Msk       (0x1UL << SBS_BKLOCKR_DTCMECC_BL_Pos)       /*!< 0x00002000 */
#define SBS_BKLOCKR_DTCMECC_BL           SBS_BKLOCKR_DTCMECC_BL_Msk                  /*!< DTCM ECC error break lock */
#define SBS_BKLOCKR_ITCMECC_BL_Pos       (14U)
#define SBS_BKLOCKR_ITCMECC_BL_Msk       (0x1UL << SBS_BKLOCKR_ITCMECC_BL_Pos)       /*!< 0x00004000 */
#define SBS_BKLOCKR_ITCMECC_BL           SBS_BKLOCKR_ITCMECC_BL_Msk                  /*!< ITCM ECC error break lock */
#define SBS_BKLOCKR_ARAM3ECC_BL_Pos      (21U)
#define SBS_BKLOCKR_ARAM3ECC_BL_Msk      (0x1UL << SBS_BKLOCKR_ARAM3ECC_BL_Pos)      /*!< 0x00200000 */
#define SBS_BKLOCKR_ARAM3ECC_BL          SBS_BKLOCKR_ARAM3ECC_BL_Msk                 /*!< AXIRAM3 ECC error break lock */
#define SBS_BKLOCKR_ARAM1ECC_BL_Pos      (23U)
#define SBS_BKLOCKR_ARAM1ECC_BL_Msk      (0x1UL << SBS_BKLOCKR_ARAM1ECC_BL_Pos)      /*!< 0x00800000 */
#define SBS_BKLOCKR_ARAM1ECC_BL          SBS_BKLOCKR_ARAM1ECC_BL_Msk                 /*!< AXIRAM1 ECC error break lock */

/*****************  Bit definition for SBS_EXTICR1 register  ******************/
#define SBS_EXTICR1_PC_EXTI0_Pos         (0U)
#define SBS_EXTICR1_PC_EXTI0_Msk         (0xFUL << SBS_EXTICR1_PC_EXTI0_Pos)         /*!< 0x0000000F */
#define SBS_EXTICR1_PC_EXTI0             SBS_EXTICR1_PC_EXTI0_Msk                    /*!< Port configuration EXTI 0 */
#define SBS_EXTICR1_PC_EXTI0_0           (0x1UL << SBS_EXTICR1_PC_EXTI0_Pos)         /*!< 0x00000001 */
#define SBS_EXTICR1_PC_EXTI0_1           (0x2UL << SBS_EXTICR1_PC_EXTI0_Pos)         /*!< 0x00000002 */
#define SBS_EXTICR1_PC_EXTI0_2           (0x4UL << SBS_EXTICR1_PC_EXTI0_Pos)         /*!< 0x00000004 */
#define SBS_EXTICR1_PC_EXTI0_3           (0x8UL << SBS_EXTICR1_PC_EXTI0_Pos)         /*!< 0x00000008 */
#define SBS_EXTICR1_PC_EXTI1_Pos         (4U)
#define SBS_EXTICR1_PC_EXTI1_Msk         (0xFUL << SBS_EXTICR1_PC_EXTI1_Pos)         /*!< 0x000000F0 */
#define SBS_EXTICR1_PC_EXTI1             SBS_EXTICR1_PC_EXTI1_Msk                    /*!< Port configuration EXTI 1 */
#define SBS_EXTICR1_PC_EXTI1_0           (0x1UL << SBS_EXTICR1_PC_EXTI1_Pos)         /*!< 0x00000010 */
#define SBS_EXTICR1_PC_EXTI1_1           (0x2UL << SBS_EXTICR1_PC_EXTI1_Pos)         /*!< 0x00000020 */
#define SBS_EXTICR1_PC_EXTI1_2           (0x4UL << SBS_EXTICR1_PC_EXTI1_Pos)         /*!< 0x00000040 */
#define SBS_EXTICR1_PC_EXTI1_3           (0x8UL << SBS_EXTICR1_PC_EXTI1_Pos)         /*!< 0x00000080 */
#define SBS_EXTICR1_PC_EXTI2_Pos         (8U)
#define SBS_EXTICR1_PC_EXTI2_Msk         (0xFUL << SBS_EXTICR1_PC_EXTI2_Pos)         /*!< 0x00000F00 */
#define SBS_EXTICR1_PC_EXTI2             SBS_EXTICR1_PC_EXTI2_Msk                    /*!< Port configuration EXTI 2 */
#define SBS_EXTICR1_PC_EXTI2_0           (0x1UL << SBS_EXTICR1_PC_EXTI2_Pos)         /*!< 0x00000100 */
#define SBS_EXTICR1_PC_EXTI2_1           (0x2UL << SBS_EXTICR1_PC_EXTI2_Pos)         /*!< 0x00000200 */
#define SBS_EXTICR1_PC_EXTI2_2           (0x4UL << SBS_EXTICR1_PC_EXTI2_Pos)         /*!< 0x00000400 */
#define SBS_EXTICR1_PC_EXTI2_3           (0x8UL << SBS_EXTICR1_PC_EXTI2_Pos)         /*!< 0x00000800 */
#define SBS_EXTICR1_PC_EXTI3_Pos         (12U)
#define SBS_EXTICR1_PC_EXTI3_Msk         (0xFUL << SBS_EXTICR1_PC_EXTI3_Pos)         /*!< 0x0000F000 */
#define SBS_EXTICR1_PC_EXTI3             SBS_EXTICR1_PC_EXTI3_Msk                    /*!< Port configuration EXTI 3 */
#define SBS_EXTICR1_PC_EXTI3_0           (0x1UL << SBS_EXTICR1_PC_EXTI3_Pos)         /*!< 0x00001000 */
#define SBS_EXTICR1_PC_EXTI3_1           (0x2UL << SBS_EXTICR1_PC_EXTI3_Pos)         /*!< 0x00002000 */
#define SBS_EXTICR1_PC_EXTI3_2           (0x4UL << SBS_EXTICR1_PC_EXTI3_Pos)         /*!< 0x00004000 */
#define SBS_EXTICR1_PC_EXTI3_3           (0x8UL << SBS_EXTICR1_PC_EXTI3_Pos)         /*!< 0x00008000 */

/*****************  Bit definition for SBS_EXTICR2 register  ******************/
#define SBS_EXTICR2_PC_EXTI4_Pos         (0U)
#define SBS_EXTICR2_PC_EXTI4_Msk         (0xFUL << SBS_EXTICR2_PC_EXTI4_Pos)         /*!< 0x0000000F */
#define SBS_EXTICR2_PC_EXTI4             SBS_EXTICR2_PC_EXTI4_Msk                    /*!< Port configuration EXTI 4 */
#define SBS_EXTICR2_PC_EXTI4_0           (0x1UL << SBS_EXTICR2_PC_EXTI4_Pos)         /*!< 0x00000001 */
#define SBS_EXTICR2_PC_EXTI4_1           (0x2UL << SBS_EXTICR2_PC_EXTI4_Pos)         /*!< 0x00000002 */
#define SBS_EXTICR2_PC_EXTI4_2           (0x4UL << SBS_EXTICR2_PC_EXTI4_Pos)         /*!< 0x00000004 */
#define SBS_EXTICR2_PC_EXTI4_3           (0x8UL << SBS_EXTICR2_PC_EXTI4_Pos)         /*!< 0x00000008 */
#define SBS_EXTICR2_PC_EXTI5_Pos         (4U)
#define SBS_EXTICR2_PC_EXTI5_Msk         (0xFUL << SBS_EXTICR2_PC_EXTI5_Pos)         /*!< 0x000000F0 */
#define SBS_EXTICR2_PC_EXTI5             SBS_EXTICR2_PC_EXTI5_Msk                    /*!< Port configuration EXTI 5 */
#define SBS_EXTICR2_PC_EXTI5_0           (0x1UL << SBS_EXTICR2_PC_EXTI5_Pos)         /*!< 0x00000010 */
#define SBS_EXTICR2_PC_EXTI5_1           (0x2UL << SBS_EXTICR2_PC_EXTI5_Pos)         /*!< 0x00000020 */
#define SBS_EXTICR2_PC_EXTI5_2           (0x4UL << SBS_EXTICR2_PC_EXTI5_Pos)         /*!< 0x00000040 */
#define SBS_EXTICR2_PC_EXTI5_3           (0x8UL << SBS_EXTICR2_PC_EXTI5_Pos)         /*!< 0x00000080 */
#define SBS_EXTICR2_PC_EXTI6_Pos         (8U)
#define SBS_EXTICR2_PC_EXTI6_Msk         (0xFUL << SBS_EXTICR2_PC_EXTI6_Pos)         /*!< 0x00000F00 */
#define SBS_EXTICR2_PC_EXTI6             SBS_EXTICR2_PC_EXTI6_Msk                    /*!< Port configuration EXTI 6 */
#define SBS_EXTICR2_PC_EXTI6_0           (0x1UL << SBS_EXTICR2_PC_EXTI6_Pos)         /*!< 0x00000100 */
#define SBS_EXTICR2_PC_EXTI6_1           (0x2UL << SBS_EXTICR2_PC_EXTI6_Pos)         /*!< 0x00000200 */
#define SBS_EXTICR2_PC_EXTI6_2           (0x4UL << SBS_EXTICR2_PC_EXTI6_Pos)         /*!< 0x00000400 */
#define SBS_EXTICR2_PC_EXTI6_3           (0x8UL << SBS_EXTICR2_PC_EXTI6_Pos)         /*!< 0x00000800 */
#define SBS_EXTICR2_PC_EXTI7_Pos         (12U)
#define SBS_EXTICR2_PC_EXTI7_Msk         (0xFUL << SBS_EXTICR2_PC_EXTI7_Pos)         /*!< 0x0000F000 */
#define SBS_EXTICR2_PC_EXTI7             SBS_EXTICR2_PC_EXTI7_Msk                    /*!< Port configuration EXTI 7 */
#define SBS_EXTICR2_PC_EXTI7_0           (0x1UL << SBS_EXTICR2_PC_EXTI7_Pos)         /*!< 0x00001000 */
#define SBS_EXTICR2_PC_EXTI7_1           (0x2UL << SBS_EXTICR2_PC_EXTI7_Pos)         /*!< 0x00002000 */
#define SBS_EXTICR2_PC_EXTI7_2           (0x4UL << SBS_EXTICR2_PC_EXTI7_Pos)         /*!< 0x00004000 */
#define SBS_EXTICR2_PC_EXTI7_3           (0x8UL << SBS_EXTICR2_PC_EXTI7_Pos)         /*!< 0x00008000 */

/*****************  Bit definition for SBS_EXTICR3 register  ******************/
#define SBS_EXTICR3_PC_EXTI8_Pos         (0U)
#define SBS_EXTICR3_PC_EXTI8_Msk         (0xFUL << SBS_EXTICR3_PC_EXTI8_Pos)         /*!< 0x0000000F */
#define SBS_EXTICR3_PC_EXTI8             SBS_EXTICR3_PC_EXTI8_Msk                    /*!< Port configuration EXTI 8 */
#define SBS_EXTICR3_PC_EXTI8_0           (0x1UL << SBS_EXTICR3_PC_EXTI8_Pos)         /*!< 0x00000001 */
#define SBS_EXTICR3_PC_EXTI8_1           (0x2UL << SBS_EXTICR3_PC_EXTI8_Pos)         /*!< 0x00000002 */
#define SBS_EXTICR3_PC_EXTI8_2           (0x4UL << SBS_EXTICR3_PC_EXTI8_Pos)         /*!< 0x00000004 */
#define SBS_EXTICR3_PC_EXTI8_3           (0x8UL << SBS_EXTICR3_PC_EXTI8_Pos)         /*!< 0x00000008 */
#define SBS_EXTICR3_PC_EXTI9_Pos         (4U)
#define SBS_EXTICR3_PC_EXTI9_Msk         (0xFUL << SBS_EXTICR3_PC_EXTI9_Pos)         /*!< 0x000000F0 */
#define SBS_EXTICR3_PC_EXTI9             SBS_EXTICR3_PC_EXTI9_Msk                    /*!< Port configuration EXTI 9 */
#define SBS_EXTICR3_PC_EXTI9_0           (0x1UL << SBS_EXTICR3_PC_EXTI9_Pos)         /*!< 0x00000010 */
#define SBS_EXTICR3_PC_EXTI9_1           (0x2UL << SBS_EXTICR3_PC_EXTI9_Pos)         /*!< 0x00000020 */
#define SBS_EXTICR3_PC_EXTI9_2           (0x4UL << SBS_EXTICR3_PC_EXTI9_Pos)         /*!< 0x00000040 */
#define SBS_EXTICR3_PC_EXTI9_3           (0x8UL << SBS_EXTICR3_PC_EXTI9_Pos)         /*!< 0x00000080 */
#define SBS_EXTICR3_PC_EXTI10_Pos        (8U)
#define SBS_EXTICR3_PC_EXTI10_Msk        (0xFUL << SBS_EXTICR3_PC_EXTI10_Pos)        /*!< 0x00000F00 */
#define SBS_EXTICR3_PC_EXTI10            SBS_EXTICR3_PC_EXTI10_Msk                   /*!< Port configuration EXTI 10 */
#define SBS_EXTICR3_PC_EXTI10_0          (0x1UL << SBS_EXTICR3_PC_EXTI10_Pos)        /*!< 0x00000100 */
#define SBS_EXTICR3_PC_EXTI10_1          (0x2UL << SBS_EXTICR3_PC_EXTI10_Pos)        /*!< 0x00000200 */
#define SBS_EXTICR3_PC_EXTI10_2          (0x4UL << SBS_EXTICR3_PC_EXTI10_Pos)        /*!< 0x00000400 */
#define SBS_EXTICR3_PC_EXTI10_3          (0x8UL << SBS_EXTICR3_PC_EXTI10_Pos)        /*!< 0x00000800 */
#define SBS_EXTICR3_PC_EXTI11_Pos        (12U)
#define SBS_EXTICR3_PC_EXTI11_Msk        (0xFUL << SBS_EXTICR3_PC_EXTI11_Pos)        /*!< 0x0000F000 */
#define SBS_EXTICR3_PC_EXTI11            SBS_EXTICR3_PC_EXTI11_Msk                   /*!< Port configuration EXTI 11 */
#define SBS_EXTICR3_PC_EXTI11_0          (0x1UL << SBS_EXTICR3_PC_EXTI11_Pos)        /*!< 0x00001000 */
#define SBS_EXTICR3_PC_EXTI11_1          (0x2UL << SBS_EXTICR3_PC_EXTI11_Pos)        /*!< 0x00002000 */
#define SBS_EXTICR3_PC_EXTI11_2          (0x4UL << SBS_EXTICR3_PC_EXTI11_Pos)        /*!< 0x00004000 */
#define SBS_EXTICR3_PC_EXTI11_3          (0x8UL << SBS_EXTICR3_PC_EXTI11_Pos)        /*!< 0x00008000 */

/*****************  Bit definition for SBS_EXTICR4 register  ******************/
#define SBS_EXTICR4_PC_EXTI12_Pos        (0U)
#define SBS_EXTICR4_PC_EXTI12_Msk        (0xFUL << SBS_EXTICR4_PC_EXTI12_Pos)        /*!< 0x0000000F */
#define SBS_EXTICR4_PC_EXTI12            SBS_EXTICR4_PC_EXTI12_Msk                   /*!< Port configuration EXTI 12 */
#define SBS_EXTICR4_PC_EXTI12_0          (0x1UL << SBS_EXTICR4_PC_EXTI12_Pos)        /*!< 0x00000001 */
#define SBS_EXTICR4_PC_EXTI12_1          (0x2UL << SBS_EXTICR4_PC_EXTI12_Pos)        /*!< 0x00000002 */
#define SBS_EXTICR4_PC_EXTI12_2          (0x4UL << SBS_EXTICR4_PC_EXTI12_Pos)        /*!< 0x00000004 */
#define SBS_EXTICR4_PC_EXTI12_3          (0x8UL << SBS_EXTICR4_PC_EXTI12_Pos)        /*!< 0x00000008 */
#define SBS_EXTICR4_PC_EXTI13_Pos        (4U)
#define SBS_EXTICR4_PC_EXTI13_Msk        (0xFUL << SBS_EXTICR4_PC_EXTI13_Pos)        /*!< 0x000000F0 */
#define SBS_EXTICR4_PC_EXTI13            SBS_EXTICR4_PC_EXTI13_Msk                   /*!< Port configuration EXTI 13 */
#define SBS_EXTICR4_PC_EXTI13_0          (0x1UL << SBS_EXTICR4_PC_EXTI13_Pos)        /*!< 0x00000010 */
#define SBS_EXTICR4_PC_EXTI13_1          (0x2UL << SBS_EXTICR4_PC_EXTI13_Pos)        /*!< 0x00000020 */
#define SBS_EXTICR4_PC_EXTI13_2          (0x4UL << SBS_EXTICR4_PC_EXTI13_Pos)        /*!< 0x00000040 */
#define SBS_EXTICR4_PC_EXTI13_3          (0x8UL << SBS_EXTICR4_PC_EXTI13_Pos)        /*!< 0x00000080 */
#define SBS_EXTICR4_PC_EXTI14_Pos        (8U)
#define SBS_EXTICR4_PC_EXTI14_Msk        (0xFUL << SBS_EXTICR4_PC_EXTI14_Pos)        /*!< 0x00000F00 */
#define SBS_EXTICR4_PC_EXTI14            SBS_EXTICR4_PC_EXTI14_Msk                   /*!< Port configuration EXTI 14 */
#define SBS_EXTICR4_PC_EXTI14_0          (0x1UL << SBS_EXTICR4_PC_EXTI14_Pos)        /*!< 0x00000100 */
#define SBS_EXTICR4_PC_EXTI14_1          (0x2UL << SBS_EXTICR4_PC_EXTI14_Pos)        /*!< 0x00000200 */
#define SBS_EXTICR4_PC_EXTI14_2          (0x4UL << SBS_EXTICR4_PC_EXTI14_Pos)        /*!< 0x00000400 */
#define SBS_EXTICR4_PC_EXTI14_3          (0x8UL << SBS_EXTICR4_PC_EXTI14_Pos)        /*!< 0x00000800 */
#define SBS_EXTICR4_PC_EXTI15_Pos        (12U)
#define SBS_EXTICR4_PC_EXTI15_Msk        (0xFUL << SBS_EXTICR4_PC_EXTI15_Pos)        /*!< 0x0000F000 */
#define SBS_EXTICR4_PC_EXTI15            SBS_EXTICR4_PC_EXTI15_Msk                   /*!< Port configuration EXTI 15 */
#define SBS_EXTICR4_PC_EXTI15_0          (0x1UL << SBS_EXTICR4_PC_EXTI15_Pos)        /*!< 0x00001000 */
#define SBS_EXTICR4_PC_EXTI15_1          (0x2UL << SBS_EXTICR4_PC_EXTI15_Pos)        /*!< 0x00002000 */
#define SBS_EXTICR4_PC_EXTI15_2          (0x4UL << SBS_EXTICR4_PC_EXTI15_Pos)        /*!< 0x00004000 */
#define SBS_EXTICR4_PC_EXTI15_3          (0x8UL << SBS_EXTICR4_PC_EXTI15_Pos)        /*!< 0x00008000 */


/******************************************************************************/
/*                                                                            */
/*                           SDMMC Interface                                  */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SDMMC_POWER register  *****************/
#define SDMMC_POWER_PWRCTRL_Pos             (0U)
#define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)              /*!< 0x00000003 */
#define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                         /*!< SDMMC state control bits */
#define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)              /*!< 0x00000001 */
#define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)              /*!< 0x00000002 */
#define SDMMC_POWER_VSWITCH_Pos             (2U)
#define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)              /*!< 0x00000004 */
#define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                         /*!< Voltage switch sequence start */
#define SDMMC_POWER_VSWITCHEN_Pos           (3U)
#define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)            /*!< 0x00000008 */
#define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk                       /*!< Voltage switch procedure enable */
#define SDMMC_POWER_DIRPOL_Pos              (4U)
#define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)               /*!< 0x00000010 */
#define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                          /*!< Data and command direction signals polarity selection */

/******************  Bit definition for SDMMC_CLKCR register  *****************/
#define SDMMC_CLKCR_CLKDIV_Pos              (0U)
#define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)             /*!< 0x000003FF */
#define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                          /*!< Clock divide factor */
#define SDMMC_CLKCR_PWRSAV_Pos              (12U)
#define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)               /*!< 0x00001000 */
#define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                          /*!< Power saving configuration bit */
#define SDMMC_CLKCR_WIDBUS_Pos              (14U)
#define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)               /*!< 0x0000C000 */
#define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                          /*!< Wide bus mode enable bit */
#define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)               /*!< 0x00004000 */
#define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)               /*!< 0x00008000 */
#define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
#define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)              /*!< 0x00010000 */
#define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                         /*!< SDMMC_CK dephasing selection bit */
#define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
#define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)              /*!< 0x00020000 */
#define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                         /*!< Hardware flow control enable */
#define SDMMC_CLKCR_DDR_Pos                 (18U)
#define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)                  /*!< 0x00040000 */
#define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                             /*!< Data rate signal selection */
#define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
#define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)             /*!< 0x00080000 */
#define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                        /*!< Bus speed mode selection */
#define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
#define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)             /*!< 0x00300000 */
#define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                        /*!< Receive clock selection */
#define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)             /*!< 0x00100000 */
#define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)             /*!< 0x00200000 */

/*******************  Bit definition for SDMMC_ARG register  ******************/
#define SDMMC_ARG_CMDARG_Pos                (0U)
#define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)          /*!< 0xFFFFFFFF */
#define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                            /*!< Command argument */

/*******************  Bit definition for SDMMC_CMD register  ******************/
#define SDMMC_CMD_CMDINDEX_Pos              (0U)
#define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)              /*!< 0x0000003F */
#define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                          /*!< Command index */
#define SDMMC_CMD_CMDTRANS_Pos              (6U)
#define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)               /*!< 0x00000040 */
#define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                          /*!< CPSM treats the command as a data transfer command */
#define SDMMC_CMD_CMDSTOP_Pos               (7U)
#define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)                /*!< 0x00000080 */
#define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                           /*!< CPSM treats the command as a stop transmission command */
#define SDMMC_CMD_WAITRESP_Pos              (8U)
#define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)               /*!< 0x00000300 */
#define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                          /*!< Wait for response bits */
#define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)               /*!< 0x00000100 */
#define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)               /*!< 0x00000200 */
#define SDMMC_CMD_WAITINT_Pos               (10U)
#define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)                /*!< 0x00000400 */
#define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                           /*!< CPSM waits for interrupt request */
#define SDMMC_CMD_WAITPEND_Pos              (11U)
#define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)               /*!< 0x00000800 */
#define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                          /*!< CPSM waits for end of data transfer from DPSM */
#define SDMMC_CMD_CPSMEN_Pos                (12U)
#define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)                 /*!< 0x00001000 */
#define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                            /*!< Command path state machine enable bit */
#define SDMMC_CMD_DTHOLD_Pos                (13U)
#define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)                 /*!< 0x00002000 */
#define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                            /*!< Hold new data block transmission and reception in DPSM */
#define SDMMC_CMD_BOOTMODE_Pos              (14U)
#define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)               /*!< 0x00004000 */
#define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                          /*!< Select the boot mode procedure to be used */
#define SDMMC_CMD_BOOTEN_Pos                (15U)
#define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)                 /*!< 0x00008000 */
#define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                            /*!< Enable boot mode procedure */
#define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
#define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)             /*!< 0x00010000 */
#define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                        /*!< CPSM treats the command as a suspend or resume command */

/*****************  Bit definition for SDMMC_RESPCMD register  ****************/
#define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
#define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)           /*!< 0x0000003F */
#define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk                       /*!< Response command index */

/******************  Bit definition for SDMMC_RESP1 register  *****************/
#define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
#define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)   /*!< 0xFFFFFFFF */
#define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk                     /*!< Card status [31:0] (short response) or [127:96] (long response) */

/******************  Bit definition for SDMMC_RESP2 register  *****************/
#define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
#define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)   /*!< 0xFFFFFFFF */
#define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk                     /*!< Card status [95:64] (long response) */

/******************  Bit definition for SDMMC_RESP3 register  *****************/
#define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
#define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)   /*!< 0xFFFFFFFF */
#define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk                     /*!< Card status [63:32] (long response) */

/******************  Bit definition for SDMMC_RESP4 register  *****************/
#define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
#define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)   /*!< 0xFFFFFFFF */
#define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk                     /*!< Card status [31:0] (long response) */

/******************  Bit definition for SDMMC_DTIMER register  ****************/
#define SDMMC_DTIMER_DATATIME_Pos           (0U)
#define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)     /*!< 0xFFFFFFFF */
#define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk                       /*!< Data and R1b busy timeout period */

/******************  Bit definition for SDMMC_DLEN register  ******************/
#define SDMMC_DLEN_DATALENGTH_Pos           (0U)
#define SDMMC_DLEN_DATALENGTH_Msk           (0x07FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)     /*!< 0x07FFFFFF */
#define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk                       /*!< Data length value */

/******************  Bit definition for SDMMC_DCTRL register  *****************/
#define SDMMC_DCTRL_DTEN_Pos                (0U)
#define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)                 /*!< 0x00000001 */
#define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                            /*!< Data transfer enable bit */
#define SDMMC_DCTRL_DTDIR_Pos               (1U)
#define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)                /*!< 0x00000002 */
#define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                           /*!< Data transfer direction selection */
#define SDMMC_DCTRL_DTMODE_Pos              (2U)
#define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)               /*!< 0x0000000C */
#define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                          /*!< Data transfer mode selection */
#define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)               /*!< 0x00000004 */
#define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)               /*!< 0x00000008 */
#define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
#define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)           /*!< 0x000000F0 */
#define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk                      /*!< Data block size */
#define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)           /*!< 0x00000010 */
#define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)           /*!< 0x00000020 */
#define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)           /*!< 0x00000040 */
#define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)           /*!< 0x00000080 */
#define SDMMC_DCTRL_RWSTART_Pos             (8U)
#define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)              /*!< 0x00000100 */
#define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                         /*!< Read wait start */
#define SDMMC_DCTRL_RWSTOP_Pos              (9U)
#define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)               /*!< 0x00000200 */
#define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                          /*!< Read wait stop */
#define SDMMC_DCTRL_RWMOD_Pos               (10U)
#define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)                /*!< 0x00000400 */
#define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                           /*!< Read wait mode */
#define SDMMC_DCTRL_SDIOEN_Pos              (11U)
#define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)               /*!< 0x00000800 */
#define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                          /*!< SD I/O interrupt enable functions */
#define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
#define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)            /*!< 0x00001000 */
#define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk                       /*!< Enable the reception of the boot acknowledgement */
#define SDMMC_DCTRL_FIFORST_Pos             (13U)
#define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)              /*!< 0x00002000 */
#define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                         /*!< FIFO reset (flush any remaining data) */

/*****************  Bit definition for SDMMC_DCOUNT register  *****************/
#define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
#define SDMMC_DCOUNT_DATACOUNT_Msk          (0x07FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)    /*!< 0x07FFFFFF */
#define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk                      /*!< Data count value */

/*******************  Bit definition for SDMMC_STA register  ******************/
#define SDMMC_STA_CCRCFAIL_Pos              (0U)
#define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)               /*!< 0x00000001 */
#define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                          /*!< Command response received (CRC check failed) */
#define SDMMC_STA_DCRCFAIL_Pos              (1U)
#define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)               /*!< 0x00000002 */
#define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                          /*!< Data block sent/received (CRC check failed) */
#define SDMMC_STA_CTIMEOUT_Pos              (2U)
#define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)               /*!< 0x00000004 */
#define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                          /*!< Command response timeout */
#define SDMMC_STA_DTIMEOUT_Pos              (3U)
#define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)               /*!< 0x00000008 */
#define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                          /*!< Data timeout */
#define SDMMC_STA_TXUNDERR_Pos              (4U)
#define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)               /*!< 0x00000010 */
#define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                          /*!< Transmit FIFO underrun error */
#define SDMMC_STA_RXOVERR_Pos               (5U)
#define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)                /*!< 0x00000020 */
#define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                           /*!< Received FIFO overrun error */
#define SDMMC_STA_CMDREND_Pos               (6U)
#define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)                /*!< 0x00000040 */
#define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                           /*!< Command response received (CRC check passed or no CRC) */
#define SDMMC_STA_CMDSENT_Pos               (7U)
#define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)                /*!< 0x00000080 */
#define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                           /*!< Command sent (no response required) */
#define SDMMC_STA_DATAEND_Pos               (8U)
#define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)                /*!< 0x00000100 */
#define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                           /*!< Data transfer ended correctly */
#define SDMMC_STA_DHOLD_Pos                 (9U)
#define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)                  /*!< 0x00000200 */
#define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                             /*!< Data transfer hold */
#define SDMMC_STA_DBCKEND_Pos               (10U)
#define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)                /*!< 0x00000400 */
#define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                           /*!< Data block sent/received */
#define SDMMC_STA_DABORT_Pos                (11U)
#define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)                 /*!< 0x00000800 */
#define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                            /*!< Data transfer aborted by CMD12 */
#define SDMMC_STA_DPSMACT_Pos               (12U)
#define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)                /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                           /*!< Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos               (13U)
#define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)                /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                           /*!< Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos              (14U)
#define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)               /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                          /*!< Transmit FIFO half empty */
#define SDMMC_STA_RXFIFOHF_Pos              (15U)
#define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)               /*!< 0x00008000 */
#define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                          /*!< Receive FIFO half full */
#define SDMMC_STA_TXFIFOF_Pos               (16U)
#define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)                /*!< 0x00010000 */
#define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                           /*!< Transmit FIFO full */
#define SDMMC_STA_RXFIFOF_Pos               (17U)
#define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)                /*!< 0x00020000 */
#define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                           /*!< Receive FIFO full */
#define SDMMC_STA_TXFIFOE_Pos               (18U)
#define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)                /*!< 0x00040000 */
#define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                           /*!< Transmit FIFO empty */
#define SDMMC_STA_RXFIFOE_Pos               (19U)
#define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)                /*!< 0x00080000 */
#define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                           /*!< Receive FIFO empty */
#define SDMMC_STA_BUSYD0_Pos                (20U)
#define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)                 /*!< 0x00100000 */
#define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                            /*!< Inverted value of SDMMC_D0 line (busy) */
#define SDMMC_STA_BUSYD0END_Pos             (21U)
#define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)              /*!< 0x00200000 */
#define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                         /*!< End of SDMMC_D0 busy following a CMD response detected */
#define SDMMC_STA_SDIOIT_Pos                (22U)
#define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)                 /*!< 0x00400000 */
#define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                            /*!< SDIO interrupt received */
#define SDMMC_STA_ACKFAIL_Pos               (23U)
#define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)                /*!< 0x00800000 */
#define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                           /*!< Boot acknowledgement received (boot acknowledgement check fail) */
#define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
#define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)             /*!< 0x01000000 */
#define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                        /*!< Boot acknowledgement timeout */
#define SDMMC_STA_VSWEND_Pos                (25U)
#define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)                 /*!< 0x02000000 */
#define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                            /*!< Voltage switch critical timing section completion */
#define SDMMC_STA_CKSTOP_Pos                (26U)
#define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)                 /*!< 0x04000000 */
#define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                            /*!< SDMMC_CK stopped in voltage switch procedure */
#define SDMMC_STA_IDMATE_Pos                (27U)
#define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)                 /*!< 0x08000000 */
#define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                            /*!< IDMA transfer error */
#define SDMMC_STA_IDMABTC_Pos               (28U)
#define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)                /*!< 0x10000000 */
#define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                           /*!< IDMA buffer transfer complete */

/*******************  Bit definition for SDMMC_ICR register  ******************/
#define SDMMC_ICR_CCRCFAILC_Pos             (0U)
#define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)              /*!< 0x00000001 */
#define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                         /*!< Command response received (CRC check failed) clear bit */
#define SDMMC_ICR_DCRCFAILC_Pos             (1U)
#define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)              /*!< 0x00000002 */
#define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                         /*!< Data block sent/received (CRC check failed) clear bit */
#define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
#define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)              /*!< 0x00000004 */
#define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                         /*!< Command response timeout clear bit */
#define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
#define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)              /*!< 0x00000008 */
#define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                         /*!< Data timeout clear bit */
#define SDMMC_ICR_TXUNDERRC_Pos             (4U)
#define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)              /*!< 0x00000010 */
#define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                         /*!< Transmit FIFO underrun error clear bit */
#define SDMMC_ICR_RXOVERRC_Pos              (5U)
#define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)               /*!< 0x00000020 */
#define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                          /*!< Received FIFO overrun error clear bit */
#define SDMMC_ICR_CMDRENDC_Pos              (6U)
#define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)               /*!< 0x00000040 */
#define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                          /*!< Command response received (CRC check passed or no CRC) clear bit */
#define SDMMC_ICR_CMDSENTC_Pos              (7U)
#define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)               /*!< 0x00000080 */
#define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                          /*!< Command sent (no response required) clear bit */
#define SDMMC_ICR_DATAENDC_Pos              (8U)
#define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)               /*!< 0x00000100 */
#define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                          /*!< Data transfer ended correctly clear bit */
#define SDMMC_ICR_DHOLDC_Pos                (9U)
#define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)                 /*!< 0x00000200 */
#define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                            /*!< Data transfer hold clear bit */
#define SDMMC_ICR_DBCKENDC_Pos              (10U)
#define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)               /*!< 0x00000400 */
#define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                          /*!< Data block sent/received clear bit */
#define SDMMC_ICR_DABORTC_Pos               (11U)
#define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)                /*!< 0x00000800 */
#define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                           /*!< Data transfer aborted by CMD12 clear bit */
#define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
#define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)             /*!< 0x00200000 */
#define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                        /*!< End of SDMMC_D0 busy following a CMD response detected clear bit */
#define SDMMC_ICR_SDIOITC_Pos               (22U)
#define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)                /*!< 0x00400000 */
#define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                           /*!< SDIO interrupt received clear bit */
#define SDMMC_ICR_ACKFAILC_Pos              (23U)
#define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)               /*!< 0x00800000 */
#define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                          /*!< Boot acknowledgement received (boot acknowledgement check fail) clear bit */
#define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
#define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)            /*!< 0x01000000 */
#define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk                       /*!< Boot acknowledgement timeout clear bit */
#define SDMMC_ICR_VSWENDC_Pos               (25U)
#define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)                /*!< 0x02000000 */
#define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                           /*!< Voltage switch critical timing section completion clear bit */
#define SDMMC_ICR_CKSTOPC_Pos               (26U)
#define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)                /*!< 0x04000000 */
#define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                           /*!< SDMMC_CK stopped in voltage switch procedure clear bit */
#define SDMMC_ICR_IDMATEC_Pos               (27U)
#define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)                /*!< 0x08000000 */
#define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                           /*!< IDMA transfer error */
#define SDMMC_ICR_IDMABTCC_Pos              (28U)
#define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)               /*!< 0x10000000 */
#define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                          /*!< IDMA buffer transfer complete clear bit */

/*******************  Bit definition for SDMMC_MASK register  *****************/
#define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
#define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)            /*!< 0x00000001 */
#define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk                       /*!< Command response received (CRC check failed) interrupt enable */
#define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
#define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)            /*!< 0x00000002 */
#define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk                       /*!< Data block sent/received (CRC check failed) interrupt enable */
#define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
#define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)            /*!< 0x00000004 */
#define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk                       /*!< Command response timeout interrupt enable */
#define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
#define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)            /*!< 0x00000008 */
#define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk                       /*!< Data timeout interrupt enable */
#define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
#define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)            /*!< 0x00000010 */
#define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk                       /*!< Transmit FIFO underrun error interrupt enable */
#define SDMMC_MASK_RXOVERRIE_Pos            (5U)
#define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)             /*!< 0x00000020 */
#define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                        /*!< Received FIFO overrun error interrupt enable */
#define SDMMC_MASK_CMDRENDIE_Pos            (6U)
#define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)             /*!< 0x00000040 */
#define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                        /*!< Command response received (CRC check passed or no CRC) interrupt enable */
#define SDMMC_MASK_CMDSENTIE_Pos            (7U)
#define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)             /*!< 0x00000080 */
#define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                        /*!< Command sent (no response required) interrupt enable */
#define SDMMC_MASK_DATAENDIE_Pos            (8U)
#define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)             /*!< 0x00000100 */
#define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                        /*!< Data transfer ended correctly interrupt enable */
#define SDMMC_MASK_DHOLDIE_Pos              (9U)
#define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)               /*!< 0x00000200 */
#define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                          /*!< Data transfer hold interrupt enable */
#define SDMMC_MASK_DBCKENDIE_Pos            (10U)
#define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)             /*!< 0x00000400 */
#define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                        /*!< Data block sent/received interrupt enable */
#define SDMMC_MASK_DABORTIE_Pos             (11U)
#define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)              /*!< 0x00000800 */
#define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                         /*!< Data transfer aborted by CMD12 interrupt enable */
#define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
#define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)            /*!< 0x00004000 */
#define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk                       /*!< Transmit FIFO half empty interrupt enable */
#define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
#define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)            /*!< 0x00008000 */
#define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk                       /*!< Receive FIFO half full interrupt enable */
#define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
#define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)             /*!< 0x00020000 */
#define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                        /*!< Receive FIFO full interrupt enable */
#define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)             /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                        /*!< Transmit FIFO empty interrupt enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)           /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk                      /*!< End of SDMMC_D0 busy following a CMD response detected interrupt enable */
#define SDMMC_MASK_SDIOITIE_Pos             (22U)
#define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)              /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                         /*!< SDIO interrupt received interrupt enable */
#define SDMMC_MASK_ACKFAILIE_Pos            (23U)
#define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)             /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                        /*!< Boot acknowledgement received (boot acknowledgement check fail) interrupt enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)          /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk                     /*!< Boot acknowledgement timeout interrupt enable */
#define SDMMC_MASK_VSWENDIE_Pos             (25U)
#define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)              /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                         /*!< Voltage switch critical timing section completion interrupt enable */
#define SDMMC_MASK_CKSTOPIE_Pos             (26U)
#define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)              /*!< 0x04000000 */
#define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                         /*!< SDMMC_CK stopped in voltage switch procedure interrupt enable */
#define SDMMC_MASK_IDMABTCIE_Pos            (28U)
#define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)             /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                        /*!< IDMA buffer transfer complete interrupt enable */

/****************  Bit definition for SDMMC_ACKTIMER register  ****************/
#define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
#define SDMMC_ACKTIME_ACKTIME_Msk           (0x07FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)     /*!< 0x07FFFFFF */
#define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk                       /*!< Boot acknowledgement timeout period */

/******************  Bit definition for SDMMC_FIFO register  ******************/
#define SDMMC_FIFO_FIFODATA_Pos             (0U)
#define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)       /*!< 0xFFFFFFFF */
#define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                         /*!< Receive and transmit FIFO data */

/******************  Bit definition for SDMMC_IDMACTRL register ***************/
#define SDMMC_IDMA_IDMAEN_Pos               (0U)
#define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)                /*!< 0x00000001 */
#define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                           /*!< IDMA enable */
#define SDMMC_IDMA_IDMABMODE_Pos            (1U)
#define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)             /*!< 0x00000002 */
#define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                        /*!< Buffer mode selection*/

/******************  Bit definition for SDMMC_IDMABSIZE register  *************/
#define SDMMC_IDMABSIZE_IDMABNDT_Pos        (5U)
#define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0xFFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)       /*!< 0x0001FFE0 */
#define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk                    /*!< Number of bytes per buffer */

/******************  Bit definition for SDMMC_IDMABASER register  *************/
#define SDMMC_IDMABASER_IDMABASER_Pos       (0U)
#define SDMMC_IDMABASER_IDMABASER_Msk       (0xFFFFFFFFUL << SDMMC_IDMABASER_IDMABASER_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_IDMABASER_IDMABASER           SDMMC_IDMABASER_IDMABASER_Msk                   /*!< Buffer memory base address */

/*****************  Bit definition for SDMMC_IDMALAR register  ****************/
#define SDMMC_IDMALAR_IDMALA_Pos            (2U)
#define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)          /*!< 0x0000FFFC */
#define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                        /*!< Linked list item address offset */
#define SDMMC_IDMALAR_ABR_Pos               (29U)
#define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)                /*!< 0x20000000 */
#define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                           /*!< Acknowledge linked list buffer ready */
#define SDMMC_IDMALAR_ULS_Pos               (30U)
#define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)                /*!< 0x40000000 */
#define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                           /*!< Update Size from linked list */
#define SDMMC_IDMALAR_ULA_Pos               (31U)
#define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)                /*!< 0x80000000 */
#define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                           /*!< Update Address from linked list */

/*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
#define SDMMC_IDMABAR_IDMABAR_Pos           (2U)
#define SDMMC_IDMABAR_IDMABAR_Msk           (0x3FFFFFFFUL << SDMMC_IDMABAR_IDMABAR_Pos)     /*!< 0xFFFFFFFC */
#define SDMMC_IDMABAR_IDMABAR               SDMMC_IDMABAR_IDMABAR_Msk                       /*!< Linked list memory base address */


/******************************************************************************/
/*                                                                            */
/*                              SPDIF-RX Interface                            */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for SPDIFRX_CR register  ****************/
#define SPDIFRX_CR_SPDIFRXEN_Pos    (0U)
#define SPDIFRX_CR_SPDIFRXEN_Msk    (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos)        /*!< 0x00000003 */
#define SPDIFRX_CR_SPDIFRXEN        SPDIFRX_CR_SPDIFRXEN_Msk                   /*!<Peripheral Block Enable                      */
#define SPDIFRX_CR_SPDIFRXEN_0      (0x1UL << SPDIFRX_CR_SPDIFRXEN_Pos)        /*!< 0x00000001 */
#define SPDIFRX_CR_SPDIFRXEN_1      (0x2UL << SPDIFRX_CR_SPDIFRXEN_Pos)        /*!< 0x00000002 */
#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
#define SPDIFRX_CR_RXSTEO_Pos       (3U)
#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
#define SPDIFRX_CR_DRFMT_Pos        (4U)
#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
#define SPDIFRX_CR_DRFMT_0          (0x1UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000010 */
#define SPDIFRX_CR_DRFMT_1          (0x2UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000020 */
#define SPDIFRX_CR_PMSK_Pos         (6U)
#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
#define SPDIFRX_CR_VMSK_Pos         (7U)
#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
#define SPDIFRX_CR_CUMSK_Pos        (8U)
#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
#define SPDIFRX_CR_PTMSK_Pos        (9U)
#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
#define SPDIFRX_CR_CHSEL_Pos        (11U)
#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
#define SPDIFRX_CR_NBTR_Pos         (12U)
#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
#define SPDIFRX_CR_NBTR_0           (0x1UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00001000 */
#define SPDIFRX_CR_NBTR_1           (0x2UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00002000 */
#define SPDIFRX_CR_WFA_Pos          (14U)
#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
#define SPDIFRX_CR_INSEL_Pos        (16U)
#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
#define SPDIFRX_CR_INSEL_0          (0x1UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00010000 */
#define SPDIFRX_CR_INSEL_1          (0x2UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00020000 */
#define SPDIFRX_CR_INSEL_2          (0x4UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00040000 */
#define SPDIFRX_CR_CKSEN_Pos        (20U)
#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

/*******************  Bit definition for SPDIFRX_IMR register  *******************/
#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
#define SPDIFRX_IMR_PERRIE_Pos      (2U)
#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
#define SPDIFRX_IMR_OVRIE_Pos       (3U)
#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
#define SPDIFRX_IMR_IFEIE_Pos       (6U)
#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

/*******************  Bit definition for SPDIFRX_SR register  *******************/
#define SPDIFRX_SR_RXNE_Pos         (0U)
#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
#define SPDIFRX_SR_CSRNE_Pos        (1U)
#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
#define SPDIFRX_SR_PERR_Pos         (2U)
#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
#define SPDIFRX_SR_OVR_Pos          (3U)
#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
#define SPDIFRX_SR_SBD_Pos          (4U)
#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
#define SPDIFRX_SR_SYNCD_Pos        (5U)
#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
#define SPDIFRX_SR_FERR_Pos         (6U)
#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
#define SPDIFRX_SR_SERR_Pos         (7U)
#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
#define SPDIFRX_SR_TERR_Pos         (8U)
#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
#define SPDIFRX_SR_WIDTH5_Pos       (16U)
#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
#define SPDIFRX_DR0_DR_Pos          (0U)
#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
#define SPDIFRX_DR0_PE_Pos          (24U)
#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
#define SPDIFRX_DR0_V_Pos           (25U)
#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
#define SPDIFRX_DR0_U_Pos           (26U)
#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
#define SPDIFRX_DR0_C_Pos           (27U)
#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
#define SPDIFRX_DR0_PT_Pos          (28U)
#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
#define SPDIFRX_DR1_DR_Pos          (8U)
#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
#define SPDIFRX_DR1_PT_Pos          (4U)
#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
#define SPDIFRX_DR1_C_Pos           (3U)
#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
#define SPDIFRX_DR1_U_Pos           (2U)
#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
#define SPDIFRX_DR1_V_Pos           (1U)
#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
#define SPDIFRX_DR1_PE_Pos          (0U)
#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
#define SPDIFRX_DR1_DRNL1_Pos       (16U)
#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
#define SPDIFRX_DR1_DRNL2_Pos       (0U)
#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

/*******************  Bit definition for SPDIFRX_CSR register   *******************/
#define SPDIFRX_CSR_USR_Pos         (0U)
#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
#define SPDIFRX_CSR_CS_Pos          (16U)
#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
#define SPDIFRX_CSR_SOB_Pos         (24U)
#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

/*******************  Bit definition for SPDIFRX_DIR register    *******************/
#define SPDIFRX_DIR_THI_Pos         (0U)
#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
#define SPDIFRX_DIR_TLO_Pos         (16U)
#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */


/******************************************************************************/
/*                                                                            */
/*                   Serial Peripheral Interface (SPI)                        */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for SPI_CR1 register  ********************/
#define SPI_CR1_SPE_Pos                     (0U)
#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
#define SPI_CR1_MASRX_Pos                   (8U)
#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
#define SPI_CR1_CSTART_Pos                  (9U)
#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
#define SPI_CR1_CSUSP_Pos                   (10U)
#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
#define SPI_CR1_HDDIR_Pos                   (11U)
#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
#define SPI_CR1_SSI_Pos                     (12U)
#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
#define SPI_CR1_CRC33_17_Pos                (13U)
#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
#define SPI_CR1_RCRCINI_Pos                 (14U)
#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
#define SPI_CR1_TCRCINI_Pos                 (15U)
#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
#define SPI_CR1_IOLOCK_Pos                  (16U)
#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */

/*******************  Bit definition for SPI_CR2 register  ********************/
#define SPI_CR2_TSIZE_Pos                   (0U)
#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */

/*******************  Bit definition for SPI_CFG1 register  ********************/
#define SPI_CFG1_DSIZE_Pos                  (0U)
#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
#define SPI_CFG1_FTHLV_Pos                  (5U)
#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
#define SPI_CFG1_UDRCFG_Pos                 (9U)
#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
#define SPI_CFG1_RXDMAEN_Pos                (14U)
#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
#define SPI_CFG1_TXDMAEN_Pos                (15U)
#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
#define SPI_CFG1_CRCSIZE_Pos                (16U)
#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
#define SPI_CFG1_CRCEN_Pos                  (22U)
#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
#define SPI_CFG1_MBR_Pos                    (28U)
#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
#define SPI_CFG1_BPASS_Pos                  (31U)
#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */

/*******************  Bit definition for SPI_CFG2 register  ********************/
#define SPI_CFG2_MSSI_Pos                   (0U)
#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
#define SPI_CFG2_MIDI_Pos                   (4U)
#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
#define SPI_CFG2_RDIOM_Pos                  (13U)
#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
#define SPI_CFG2_RDIOP_Pos                  (14U)
#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
#define SPI_CFG2_IOSWP_Pos                  (15U)
#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
#define SPI_CFG2_COMM_Pos                   (17U)
#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
#define SPI_CFG2_SP_Pos                     (19U)
#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
#define SPI_CFG2_MASTER_Pos                 (22U)
#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
#define SPI_CFG2_LSBFRST_Pos                (23U)
#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
#define SPI_CFG2_CPHA_Pos                   (24U)
#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
#define SPI_CFG2_CPOL_Pos                   (25U)
#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
#define SPI_CFG2_SSM_Pos                    (26U)
#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
#define SPI_CFG2_SSIOP_Pos                  (28U)
#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
#define SPI_CFG2_SSOE_Pos                   (29U)
#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
#define SPI_CFG2_SSOM_Pos                   (30U)
#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
#define SPI_CFG2_AFCNTR_Pos                 (31U)
#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */

/*******************  Bit definition for SPI_IER register  ********************/
#define SPI_IER_RXPIE_Pos                   (0U)
#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
#define SPI_IER_TXPIE_Pos                   (1U)
#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
#define SPI_IER_DXPIE_Pos                   (2U)
#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
#define SPI_IER_EOTIE_Pos                   (3U)
#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
#define SPI_IER_TXTFIE_Pos                  (4U)
#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
#define SPI_IER_UDRIE_Pos                   (5U)
#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
#define SPI_IER_OVRIE_Pos                   (6U)
#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
#define SPI_IER_CRCEIE_Pos                  (7U)
#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
#define SPI_IER_TIFREIE_Pos                 (8U)
#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
#define SPI_IER_MODFIE_Pos                  (9U)
#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */

/*******************  Bit definition for SPI_SR register  ********************/
#define SPI_SR_RXP_Pos                      (0U)
#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
#define SPI_SR_TXP_Pos                      (1U)
#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
#define SPI_SR_DXP_Pos                      (2U)
#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
#define SPI_SR_EOT_Pos                      (3U)
#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
#define SPI_SR_TXTF_Pos                     (4U)
#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
#define SPI_SR_UDR_Pos                      (5U)
#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
#define SPI_SR_OVR_Pos                      (6U)
#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
#define SPI_SR_CRCE_Pos                     (7U)
#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
#define SPI_SR_TIFRE_Pos                    (8U)
#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
#define SPI_SR_MODF_Pos                     (9U)
#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
#define SPI_SR_TSERF_Pos                    (10U)
#define SPI_SR_TSERF_Msk                    (0x1UL << SPI_SR_TSERF_Pos)             /*!< 0x00000400 */
#define SPI_SR_TSERF                        SPI_SR_TSERF_Msk                        /*!<Number of SPI data to be transacted reloaded */
#define SPI_SR_SUSP_Pos                     (11U)
#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
#define SPI_SR_TXC_Pos                      (12U)
#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
#define SPI_SR_RXPLVL_Pos                   (13U)
#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
#define SPI_SR_RXWNE_Pos                    (15U)
#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
#define SPI_SR_CTSIZE_Pos                   (16U)
#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */

/*******************  Bit definition for SPI_IFCR register  ********************/
#define SPI_IFCR_EOTC_Pos                   (3U)
#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
#define SPI_IFCR_TXTFC_Pos                  (4U)
#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
#define SPI_IFCR_UDRC_Pos                   (5U)
#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
#define SPI_IFCR_OVRC_Pos                   (6U)
#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
#define SPI_IFCR_CRCEC_Pos                  (7U)
#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
#define SPI_IFCR_TIFREC_Pos                 (8U)
#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
#define SPI_IFCR_MODFC_Pos                  (9U)
#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
#define SPI_IFCR_SUSPC_Pos                  (11U)
#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */

/*******************  Bit definition for SPI_TXDR register  ********************/
#define SPI_TXDR_TXDR_Pos                   (0U)
#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */

/*******************  Bit definition for SPI_RXDR register  ********************/
#define SPI_RXDR_RXDR_Pos                   (0U)
#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */

/*******************  Bit definition for SPI_CRCPOLY register  ********************/
#define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */

/*******************  Bit definition for SPI_TXCRC register  ********************/
#define SPI_TXCRC_TXCRC_Pos                 (0U)
#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */

/*******************  Bit definition for SPI_RXCRC register  ********************/
#define SPI_RXCRC_RXCRC_Pos                 (0U)
#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */

/*******************  Bit definition for SPI_UDRDR register  ********************/
#define SPI_UDRDR_UDRDR_Pos                 (0U)
#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */

/******************  Bit definition for SPI_I2SCFGR register  *****************/
#define SPI_I2SCFGR_I2SMOD_Pos              (0U)
#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)       /*!< 0x00000001 */
#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk                  /*!<I2S mode selection */
#define SPI_I2SCFGR_I2SCFG_Pos              (1U)
#define SPI_I2SCFGR_I2SCFG_Msk              (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)       /*!< 0x0000000E */
#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk                  /*!<I2SCFG[2:0] I2S configuration mode */
#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)       /*!< 0x00000002 */
#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)       /*!< 0x00000004 */
#define SPI_I2SCFGR_I2SCFG_2                (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)       /*!< 0x00000008 */
#define SPI_I2SCFGR_I2SSTD_Pos              (4U)
#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)       /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk                  /*!<I2SSTD[1:0] I2S standard selection */
#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)       /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)       /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)      /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk                 /*!<PCM frame synchronization */
#define SPI_I2SCFGR_DATLEN_Pos              (8U)
#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)       /*!< 0x00000300 */
#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk                  /*!<DATLEN[1:0] Data length to be transferred */
#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)       /*!< 0x00000100 */
#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)       /*!< 0x00000200 */
#define SPI_I2SCFGR_CHLEN_Pos               (10U)
#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)        /*!< 0x00000400 */
#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk                   /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_CKPOL_Pos               (11U)
#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)        /*!< 0x00000800 */
#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk                   /*!<Steady state clock polarity */
#define SPI_I2SCFGR_FIXCH_Pos               (12U)
#define SPI_I2SCFGR_FIXCH_Msk               (0x1UL << SPI_I2SCFGR_FIXCH_Pos)        /*!< 0x00001000 */
#define SPI_I2SCFGR_FIXCH                   SPI_I2SCFGR_FIXCH_Msk                   /*!<Fixed channel length in SLAVE */
#define SPI_I2SCFGR_WSINV_Pos               (13U)
#define SPI_I2SCFGR_WSINV_Msk               (0x1UL << SPI_I2SCFGR_WSINV_Pos)        /*!< 0x00002000 */
#define SPI_I2SCFGR_WSINV                   SPI_I2SCFGR_WSINV_Msk                   /*!<Word select inversion */
#define SPI_I2SCFGR_DATFMT_Pos              (14U)
#define SPI_I2SCFGR_DATFMT_Msk              (0x1UL << SPI_I2SCFGR_DATFMT_Pos)       /*!< 0x00004000 */
#define SPI_I2SCFGR_DATFMT                  SPI_I2SCFGR_DATFMT_Msk                  /*!<Data format */
#define SPI_I2SCFGR_I2SDIV_Pos              (16U)
#define SPI_I2SCFGR_I2SDIV_Msk              (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)      /*!< 0x00FF0000 */
#define SPI_I2SCFGR_I2SDIV                  SPI_I2SCFGR_I2SDIV_Msk                  /*!<I2S Linear prescaler */
#define SPI_I2SCFGR_ODD_Pos                 (24U)
#define SPI_I2SCFGR_ODD_Msk                 (0x1UL << SPI_I2SCFGR_ODD_Pos)          /*!< 0x01000000 */
#define SPI_I2SCFGR_ODD                     SPI_I2SCFGR_ODD_Msk                     /*!<Odd factor for the prescaler */
#define SPI_I2SCFGR_MCKOE_Pos               (25U)
#define SPI_I2SCFGR_MCKOE_Msk               (0x1UL << SPI_I2SCFGR_MCKOE_Pos)        /*!< 0x02000000 */
#define SPI_I2SCFGR_MCKOE                   SPI_I2SCFGR_MCKOE_Msk                   /*!<Master Clock Output Enable */


/******************************************************************************/
/*                                                                            */
/*                     Tamper and backup register (TAMP)                      */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for TAMP_CR1 register  *****************/
#define TAMP_CR1_TAMP1E_Pos                 (0U)
#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos                 (1U)
#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos                 (2U)
#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_TAMP4E_Pos                 (3U)
#define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
#define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
#define TAMP_CR1_TAMP5E_Pos                 (4U)
#define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
#define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
#define TAMP_CR1_TAMP6E_Pos                 (5U)
#define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
#define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
#define TAMP_CR1_TAMP7E_Pos                 (6U)
#define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
#define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
#define TAMP_CR1_TAMP8E_Pos                 (7U)
#define TAMP_CR1_TAMP8E_Msk                 (0x1UL << TAMP_CR1_TAMP8E_Pos)          /*!< 0x00000080 */
#define TAMP_CR1_TAMP8E                     TAMP_CR1_TAMP8E_Msk
#define TAMP_CR1_ITAMP1E_Pos                (16U)
#define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
#define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
#define TAMP_CR1_ITAMP2E_Pos                (17U)
#define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
#define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
#define TAMP_CR1_ITAMP3E_Pos                (18U)
#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos                (19U)
#define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos                (20U)
#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos                (21U)
#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
#define TAMP_CR1_ITAMP7E_Pos                (22U)
#define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
#define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
#define TAMP_CR1_ITAMP8E_Pos                (23U)
#define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
#define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
#define TAMP_CR1_ITAMP9E_Pos                (24U)
#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
#define TAMP_CR1_ITAMP11E_Pos               (26U)
#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
#define TAMP_CR1_ITAMP15E_Pos               (30U)
#define TAMP_CR1_ITAMP15E_Msk               (0x1UL << TAMP_CR1_ITAMP15E_Pos)        /*!< 0x40000000 */
#define TAMP_CR1_ITAMP15E                   TAMP_CR1_ITAMP15E_Msk

/********************  Bits definition for TAMP_CR2 register  *****************/
#define TAMP_CR2_TAMP1POM_Pos               (0U)
#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
#define TAMP_CR2_TAMP2POM_Pos               (1U)
#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
#define TAMP_CR2_TAMP3POM_Pos               (2U)
#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
#define TAMP_CR2_TAMP4POM_Pos               (3U)
#define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
#define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
#define TAMP_CR2_TAMP5POM_Pos               (4U)
#define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
#define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
#define TAMP_CR2_TAMP6POM_Pos               (5U)
#define TAMP_CR2_TAMP6POM_Msk               (0x1UL << TAMP_CR2_TAMP6POM_Pos)        /*!< 0x00000020 */
#define TAMP_CR2_TAMP6POM                   TAMP_CR2_TAMP6POM_Msk
#define TAMP_CR2_TAMP7POM_Pos               (6U)
#define TAMP_CR2_TAMP7POM_Msk               (0x1UL << TAMP_CR2_TAMP7POM_Pos)        /*!< 0x00000040 */
#define TAMP_CR2_TAMP7POM                   TAMP_CR2_TAMP7POM_Msk
#define TAMP_CR2_TAMP8POM_Pos               (7U)
#define TAMP_CR2_TAMP8POM_Msk               (0x1UL << TAMP_CR2_TAMP8POM_Pos)        /*!< 0x00000080 */
#define TAMP_CR2_TAMP8POM                   TAMP_CR2_TAMP8POM_Msk
#define TAMP_CR2_TAMP1MSK_Pos               (16U)
#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
#define TAMP_CR2_TAMP2MSK_Pos               (17U)
#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
#define TAMP_CR2_TAMP3MSK_Pos               (18U)
#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
#define TAMP_CR2_BKBLOCK_Pos                (22U)
#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
#define TAMP_CR2_BKERASE_Pos                (23U)
#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
#define TAMP_CR2_TAMP1TRG_Pos               (24U)
#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos               (25U)
#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos               (26U)
#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
#define TAMP_CR2_TAMP4TRG_Pos               (27U)
#define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
#define TAMP_CR2_TAMP5TRG_Pos               (28U)
#define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
#define TAMP_CR2_TAMP6TRG_Pos               (29U)
#define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
#define TAMP_CR2_TAMP7TRG_Pos               (30U)
#define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
#define TAMP_CR2_TAMP8TRG_Pos               (31U)
#define TAMP_CR2_TAMP8TRG_Msk               (0x1UL << TAMP_CR2_TAMP8TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP8TRG                   TAMP_CR2_TAMP8TRG_Msk

/********************  Bits definition for TAMP_CR3 register  *****************/
#define TAMP_CR3_ITAMP1POM_Pos             (0U)
#define TAMP_CR3_ITAMP1POM_Msk             (0x1UL << TAMP_CR3_ITAMP1POM_Pos)        /*!< 0x00000001 */
#define TAMP_CR3_ITAMP1POM                 TAMP_CR3_ITAMP1POM_Msk
#define TAMP_CR3_ITAMP2POM_Pos             (1U)
#define TAMP_CR3_ITAMP2POM_Msk             (0x1UL << TAMP_CR3_ITAMP2POM_Pos)        /*!< 0x00000002 */
#define TAMP_CR3_ITAMP2POM                 TAMP_CR3_ITAMP2POM_Msk
#define TAMP_CR3_ITAMP3POM_Pos             (2U)
#define TAMP_CR3_ITAMP3POM_Msk             (0x1UL << TAMP_CR3_ITAMP3POM_Pos)        /*!< 0x00000004 */
#define TAMP_CR3_ITAMP3POM                 TAMP_CR3_ITAMP3POM_Msk
#define TAMP_CR3_ITAMP4POM_Pos             (3U)
#define TAMP_CR3_ITAMP4POM_Msk             (0x1UL << TAMP_CR3_ITAMP4POM_Pos)        /*!< 0x00000008 */
#define TAMP_CR3_ITAMP4POM                 TAMP_CR3_ITAMP4POM_Msk
#define TAMP_CR3_ITAMP5POM_Pos             (4U)
#define TAMP_CR3_ITAMP5POM_Msk             (0x1UL << TAMP_CR3_ITAMP5POM_Pos)        /*!< 0x00000010 */
#define TAMP_CR3_ITAMP5POM                 TAMP_CR3_ITAMP5POM_Msk
#define TAMP_CR3_ITAMP6POM_Pos             (5U)
#define TAMP_CR3_ITAMP6POM_Msk             (0x1UL << TAMP_CR3_ITAMP6POM_Pos)        /*!< 0x00000020 */
#define TAMP_CR3_ITAMP6POM                 TAMP_CR3_ITAMP6POM_Msk
#define TAMP_CR3_ITAMP7POM_Pos             (6U)
#define TAMP_CR3_ITAMP7POM_Msk             (0x1UL << TAMP_CR3_ITAMP7POM_Pos)        /*!< 0x00000040 */
#define TAMP_CR3_ITAMP7POM                 TAMP_CR3_ITAMP7POM_Msk
#define TAMP_CR3_ITAMP8POM_Pos             (7U)
#define TAMP_CR3_ITAMP8POM_Msk             (0x1UL << TAMP_CR3_ITAMP8POM_Pos)        /*!< 0x00000080 */
#define TAMP_CR3_ITAMP8POM                 TAMP_CR3_ITAMP8POM_Msk
#define TAMP_CR3_ITAMP9POM_Pos             (8U)
#define TAMP_CR3_ITAMP9POM_Msk             (0x1UL << TAMP_CR3_ITAMP9POM_Pos)        /*!< 0x00000100 */
#define TAMP_CR3_ITAMP9POM                 TAMP_CR3_ITAMP9POM_Msk
#define TAMP_CR3_ITAMP11POM_Pos            (10U)
#define TAMP_CR3_ITAMP11POM_Msk            (0x1UL << TAMP_CR3_ITAMP11POM_Pos)       /*!< 0x00000400 */
#define TAMP_CR3_ITAMP11POM                TAMP_CR3_ITAMP11POM_Msk
#define TAMP_CR3_ITAMP15POM_Pos            (14U)
#define TAMP_CR3_ITAMP15POM_Msk            (0x1UL << TAMP_CR3_ITAMP15POM_Pos)       /*!< 0x00004000 */
#define TAMP_CR3_ITAMP15POM                TAMP_CR3_ITAMP15POM_Msk

/********************  Bits definition for TAMP_FLTCR register  ***************/
#define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
#define TAMP_FLTCR_TAMPFLT_Pos              (3U)
#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
#define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
#define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk

/********************  Bits definition for TAMP_ATCR1 register  ***************/
#define TAMP_ATCR1_TAMP1AM_Pos              (0U)
#define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
#define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
#define TAMP_ATCR1_TAMP2AM_Pos              (1U)
#define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
#define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
#define TAMP_ATCR1_TAMP3AM_Pos              (2U)
#define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
#define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
#define TAMP_ATCR1_TAMP4AM_Pos              (3U)
#define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
#define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
#define TAMP_ATCR1_TAMP5AM_Pos              (4U)
#define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
#define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
#define TAMP_ATCR1_TAMP6AM_Pos              (5U)
#define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
#define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
#define TAMP_ATCR1_TAMP7AM_Pos              (6U)
#define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
#define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
#define TAMP_ATCR1_TAMP8AM_Pos              (7U)
#define TAMP_ATCR1_TAMP8AM_Msk              (0x1UL << TAMP_ATCR1_TAMP8AM_Pos)       /*!< 0x00000080 */
#define TAMP_ATCR1_TAMP8AM                  TAMP_ATCR1_TAMP8AM_Msk
#define TAMP_ATCR1_ATOSEL1_Pos              (8U)
#define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
#define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
#define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
#define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
#define TAMP_ATCR1_ATOSEL2_Pos              (10U)
#define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
#define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
#define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
#define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
#define TAMP_ATCR1_ATOSEL3_Pos              (12U)
#define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
#define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
#define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
#define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
#define TAMP_ATCR1_ATOSEL4_Pos              (14U)
#define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
#define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
#define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
#define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
#define TAMP_ATCR1_ATCKSEL_Pos              (16U)
#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
#define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
#define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
#define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
#define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
#define TAMP_ATCR1_ATPER_Pos                (24U)
#define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
#define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
#define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
#define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
#define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
#define TAMP_ATCR1_ATOSHARE_Pos             (30U)
#define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
#define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
#define TAMP_ATCR1_FLTEN_Pos                (31U)
#define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
#define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk

/********************  Bits definition for TAMP_ATSEEDR register  ******************/
#define TAMP_ATSEEDR_SEED_Pos               (0U)
#define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
#define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk

/********************  Bits definition for TAMP_ATOR register  ******************/
#define TAMP_ATOR_PRNG_Pos                  (0U)
#define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)          /*!< 0x000000FF */
#define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
#define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
#define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
#define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
#define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
#define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
#define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
#define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
#define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
#define TAMP_ATOR_SEEDF_Pos                 (14U)
#define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
#define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
#define TAMP_ATOR_INITS_Pos                 (15U)
#define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
#define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk

/********************  Bits definition for TAMP_ATCR2 register  ***************/
#define TAMP_ATCR2_ATOSEL1_Pos              (8U)
#define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
#define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
#define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
#define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
#define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
#define TAMP_ATCR2_ATOSEL2_Pos              (11U)
#define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
#define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
#define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
#define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
#define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
#define TAMP_ATCR2_ATOSEL3_Pos              (14U)
#define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
#define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
#define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
#define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
#define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
#define TAMP_ATCR2_ATOSEL4_Pos              (17U)
#define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
#define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
#define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
#define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
#define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
#define TAMP_ATCR2_ATOSEL5_Pos              (20U)
#define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
#define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
#define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
#define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
#define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
#define TAMP_ATCR2_ATOSEL6_Pos              (23U)
#define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
#define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
#define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
#define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
#define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
#define TAMP_ATCR2_ATOSEL7_Pos              (26U)
#define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
#define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
#define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
#define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
#define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
#define TAMP_ATCR2_ATOSEL8_Pos              (29U)
#define TAMP_ATCR2_ATOSEL8_Msk              (0x7UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0xE0000000 */
#define TAMP_ATCR2_ATOSEL8                  TAMP_ATCR2_ATOSEL8_Msk
#define TAMP_ATCR2_ATOSEL8_0                (0x1UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x20000000 */
#define TAMP_ATCR2_ATOSEL8_1                (0x2UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x40000000 */
#define TAMP_ATCR2_ATOSEL8_2                (0x4UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x80000000 */

/********************  Bits definition for TAMP_CFGR register  *************/
#define TAMP_CFGR_BKPRW_Pos                 (0U)
#define TAMP_CFGR_BKPRW_Msk                 (0xFFUL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x000000FF */
#define TAMP_CFGR_BKPRW                     TAMP_CFGR_BKPRW_Msk
#define TAMP_CFGR_BKPRW_0                   (0x1UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000001 */
#define TAMP_CFGR_BKPRW_1                   (0x2UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000002 */
#define TAMP_CFGR_BKPRW_2                   (0x4UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000004 */
#define TAMP_CFGR_BKPRW_3                   (0x8UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000008 */
#define TAMP_CFGR_BKPRW_4                   (0x10UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000010 */
#define TAMP_CFGR_BKPRW_5                   (0x20UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000020 */
#define TAMP_CFGR_BKPRW_6                   (0x40UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000040 */
#define TAMP_CFGR_BKPRW_7                   (0x80UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000080 */
#define TAMP_CFGR_BKPW_Pos                  (16U)
#define TAMP_CFGR_BKPW_Msk                  (0xFFUL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00FF0000 */
#define TAMP_CFGR_BKPW                      TAMP_CFGR_BKPW_Msk
#define TAMP_CFGR_BKPW_0                    (0x1UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00010000 */
#define TAMP_CFGR_BKPW_1                    (0x2UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00020000 */
#define TAMP_CFGR_BKPW_2                    (0x4UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00040000 */
#define TAMP_CFGR_BKPW_3                    (0x8UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00080000 */
#define TAMP_CFGR_BKPW_4                    (0x10UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00100000 */
#define TAMP_CFGR_BKPW_5                    (0x20UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00200000 */
#define TAMP_CFGR_BKPW_6                    (0x40UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00400000 */
#define TAMP_CFGR_BKPW_7                    (0x80UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00800000 */
#define TAMP_CFGR_BHKLOCK_Pos               (30U)
#define TAMP_CFGR_BHKLOCK_Msk               (0x1UL << TAMP_CFGR_BHKLOCK_Pos)        /*!< 0x40000000 */
#define TAMP_CFGR_BHKLOCK                   TAMP_CFGR_BHKLOCK_Msk

/********************  Bits definition for TAMP_PRIVCFGR register  ************/
#define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
#define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x00008000 */
#define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk

/********************  Bits definition for TAMP_IER register  *****************/
#define TAMP_IER_TAMP1IE_Pos                (0U)
#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos                (1U)
#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos                (2U)
#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_TAMP4IE_Pos                (3U)
#define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
#define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
#define TAMP_IER_TAMP5IE_Pos                (4U)
#define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
#define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
#define TAMP_IER_TAMP6IE_Pos                (5U)
#define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
#define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
#define TAMP_IER_TAMP7IE_Pos                (6U)
#define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
#define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
#define TAMP_IER_TAMP8IE_Pos                (7U)
#define TAMP_IER_TAMP8IE_Msk                (0x1UL << TAMP_IER_TAMP8IE_Pos)         /*!< 0x00000080 */
#define TAMP_IER_TAMP8IE                    TAMP_IER_TAMP8IE_Msk
#define TAMP_IER_ITAMP1IE_Pos               (16U)
#define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
#define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
#define TAMP_IER_ITAMP2IE_Pos               (17U)
#define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
#define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
#define TAMP_IER_ITAMP3IE_Pos               (18U)
#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos               (19U)
#define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos               (20U)
#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos               (21U)
#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
#define TAMP_IER_ITAMP7IE_Pos               (22U)
#define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
#define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
#define TAMP_IER_ITAMP8IE_Pos               (23U)
#define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
#define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
#define TAMP_IER_ITAMP9IE_Pos               (24U)
#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
#define TAMP_IER_ITAMP11IE_Pos              (26U)
#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
#define TAMP_IER_ITAMP15IE_Pos              (30U)
#define TAMP_IER_ITAMP15IE_Msk              (0x1UL << TAMP_IER_ITAMP15IE_Pos)       /*!< 0x40000000 */
#define TAMP_IER_ITAMP15IE                  TAMP_IER_ITAMP15IE_Msk

/********************  Bits definition for TAMP_SR register  *****************/
#define TAMP_SR_TAMP1F_Pos                  (0U)
#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos                  (1U)
#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos                  (2U)
#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
#define TAMP_SR_TAMP4F_Pos                  (3U)
#define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
#define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
#define TAMP_SR_TAMP5F_Pos                  (4U)
#define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
#define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
#define TAMP_SR_TAMP6F_Pos                  (5U)
#define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
#define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
#define TAMP_SR_TAMP7F_Pos                  (6U)
#define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
#define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
#define TAMP_SR_TAMP8F_Pos                  (7U)
#define TAMP_SR_TAMP8F_Msk                  (0x1UL << TAMP_SR_TAMP8F_Pos)           /*!< 0x00000080 */
#define TAMP_SR_TAMP8F                      TAMP_SR_TAMP8F_Msk
#define TAMP_SR_ITAMP1F_Pos                 (16U)
#define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
#define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
#define TAMP_SR_ITAMP2F_Pos                 (17U)
#define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
#define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
#define TAMP_SR_ITAMP3F_Pos                 (18U)
#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos                 (19U)
#define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos                 (20U)
#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos                 (21U)
#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
#define TAMP_SR_ITAMP7F_Pos                 (22U)
#define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
#define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
#define TAMP_SR_ITAMP8F_Pos                 (23U)
#define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
#define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
#define TAMP_SR_ITAMP9F_Pos                 (24U)
#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
#define TAMP_SR_ITAMP11F_Pos                (26U)
#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
#define TAMP_SR_ITAMP15F_Pos                (30U)
#define TAMP_SR_ITAMP15F_Msk                (0x1UL << TAMP_SR_ITAMP15F_Pos)         /*!< 0x40000000 */
#define TAMP_SR_ITAMP15F                    TAMP_SR_ITAMP15F_Msk

/********************  Bits definition for TAMP_MISR register  ****************/
#define TAMP_MISR_TAMP1MF_Pos               (0U)
#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos               (1U)
#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos               (2U)
#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_TAMP4MF_Pos               (3U)
#define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
#define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
#define TAMP_MISR_TAMP5MF_Pos               (4U)
#define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
#define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
#define TAMP_MISR_TAMP6MF_Pos               (5U)
#define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
#define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
#define TAMP_MISR_TAMP7MF_Pos               (6U)
#define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
#define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
#define TAMP_MISR_TAMP8MF_Pos               (7U)
#define TAMP_MISR_TAMP8MF_Msk               (0x1UL << TAMP_MISR_TAMP8MF_Pos)        /*!< 0x00000080 */
#define TAMP_MISR_TAMP8MF                   TAMP_MISR_TAMP8MF_Msk
#define TAMP_MISR_ITAMP1MF_Pos              (16U)
#define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
#define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
#define TAMP_MISR_ITAMP2MF_Pos              (17U)
#define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
#define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos              (18U)
#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos              (19U)
#define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos              (20U)
#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos              (21U)
#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
#define TAMP_MISR_ITAMP7MF_Pos              (22U)
#define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
#define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
#define TAMP_MISR_ITAMP8MF_Pos              (23U)
#define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
#define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
#define TAMP_MISR_ITAMP9MF_Pos              (24U)
#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
#define TAMP_MISR_ITAMP11MF_Pos             (26U)
#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
#define TAMP_MISR_ITAMP15MF_Pos             (30U)
#define TAMP_MISR_ITAMP15MF_Msk             (0x1UL << TAMP_MISR_ITAMP15MF_Pos)      /*!< 0x40000000 */
#define TAMP_MISR_ITAMP15MF                 TAMP_MISR_ITAMP15MF_Msk

/********************  Bits definition for TAMP_SCR register  *****************/
#define TAMP_SCR_CTAMP1F_Pos                (0U)
#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos                (1U)
#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos                (2U)
#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CTAMP4F_Pos                (3U)
#define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
#define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
#define TAMP_SCR_CTAMP5F_Pos                (4U)
#define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
#define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
#define TAMP_SCR_CTAMP6F_Pos                (5U)
#define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
#define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
#define TAMP_SCR_CTAMP7F_Pos                (6U)
#define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
#define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
#define TAMP_SCR_CTAMP8F_Pos                (7U)
#define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
#define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
#define TAMP_SCR_CITAMP1F_Pos               (16U)
#define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
#define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
#define TAMP_SCR_CITAMP2F_Pos               (17U)
#define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
#define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
#define TAMP_SCR_CITAMP3F_Pos               (18U)
#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos               (19U)
#define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos               (20U)
#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos               (21U)
#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
#define TAMP_SCR_CITAMP7F_Pos               (22U)
#define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
#define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
#define TAMP_SCR_CITAMP8F_Pos               (23U)
#define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
#define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
#define TAMP_SCR_CITAMP9F_Pos               (24U)
#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x01000000 */
#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
#define TAMP_SCR_CITAMP11F_Pos              (26U)
#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x04000000 */
#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
#define TAMP_SCR_CITAMP15F_Pos              (30U)
#define TAMP_SCR_CITAMP15F_Msk              (0x1UL << TAMP_SCR_CITAMP15F_Pos)       /*!< 0x40000000 */
#define TAMP_SCR_CITAMP15F                  TAMP_SCR_CITAMP15F_Msk

/********************  Bits definition for TAMP_COUNT1R register  ***************/
#define TAMP_COUNT1R_COUNT_Pos              (0U)
#define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
#define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk

/********************  Bits definition for TAMP_RPCFGR register  ***************/
#define TAMP_RPCFGR_RPCFG0_Pos              (0U)
#define TAMP_RPCFGR_RPCFG0_Msk              (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)       /*!< 0x00000001 */
#define TAMP_RPCFGR_RPCFG0                  TAMP_RPCFGR_RPCFG0_Msk

/********************  Bits definition for TAMP_BKP0R register  ***************/
#define TAMP_BKP0R_Pos                      (0U)
#define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP0R                          TAMP_BKP0R_Msk

/********************  Bits definition for TAMP_BKP1R register  ****************/
#define TAMP_BKP1R_Pos                      (0U)
#define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP1R                          TAMP_BKP1R_Msk

/********************  Bits definition for TAMP_BKP2R register  ****************/
#define TAMP_BKP2R_Pos                      (0U)
#define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP2R                          TAMP_BKP2R_Msk

/********************  Bits definition for TAMP_BKP3R register  ****************/
#define TAMP_BKP3R_Pos                      (0U)
#define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP3R                          TAMP_BKP3R_Msk

/********************  Bits definition for TAMP_BKP4R register  ****************/
#define TAMP_BKP4R_Pos                      (0U)
#define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP4R                          TAMP_BKP4R_Msk

/********************  Bits definition for TAMP_BKP5R register  ****************/
#define TAMP_BKP5R_Pos                      (0U)
#define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP5R                          TAMP_BKP5R_Msk

/********************  Bits definition for TAMP_BKP6R register  ****************/
#define TAMP_BKP6R_Pos                      (0U)
#define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP6R                          TAMP_BKP6R_Msk

/********************  Bits definition for TAMP_BKP7R register  ****************/
#define TAMP_BKP7R_Pos                      (0U)
#define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP7R                          TAMP_BKP7R_Msk

/********************  Bits definition for TAMP_BKP8R register  ****************/
#define TAMP_BKP8R_Pos                      (0U)
#define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP8R                          TAMP_BKP8R_Msk

/********************  Bits definition for TAMP_BKP9R register  ****************/
#define TAMP_BKP9R_Pos                      (0U)
#define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP9R                          TAMP_BKP9R_Msk

/********************  Bits definition for TAMP_BKP10R register  ***************/
#define TAMP_BKP10R_Pos                     (0U)
#define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP10R                         TAMP_BKP10R_Msk

/********************  Bits definition for TAMP_BKP11R register  ***************/
#define TAMP_BKP11R_Pos                     (0U)
#define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP11R                         TAMP_BKP11R_Msk

/********************  Bits definition for TAMP_BKP12R register  ***************/
#define TAMP_BKP12R_Pos                     (0U)
#define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP12R                         TAMP_BKP12R_Msk

/********************  Bits definition for TAMP_BKP13R register  ***************/
#define TAMP_BKP13R_Pos                     (0U)
#define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP13R                         TAMP_BKP13R_Msk

/********************  Bits definition for TAMP_BKP14R register  ***************/
#define TAMP_BKP14R_Pos                     (0U)
#define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP14R                         TAMP_BKP14R_Msk

/********************  Bits definition for TAMP_BKP15R register  ***************/
#define TAMP_BKP15R_Pos                     (0U)
#define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP15R                         TAMP_BKP15R_Msk

/********************  Bits definition for TAMP_BKP16R register  ***************/
#define TAMP_BKP16R_Pos                     (0U)
#define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP16R                         TAMP_BKP16R_Msk

/********************  Bits definition for TAMP_BKP17R register  ***************/
#define TAMP_BKP17R_Pos                     (0U)
#define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP17R                         TAMP_BKP17R_Msk

/********************  Bits definition for TAMP_BKP18R register  ***************/
#define TAMP_BKP18R_Pos                     (0U)
#define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP18R                         TAMP_BKP18R_Msk

/********************  Bits definition for TAMP_BKP19R register  ***************/
#define TAMP_BKP19R_Pos                     (0U)
#define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP19R                         TAMP_BKP19R_Msk

/********************  Bits definition for TAMP_BKP20R register  ***************/
#define TAMP_BKP20R_Pos                     (0U)
#define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP20R                         TAMP_BKP20R_Msk

/********************  Bits definition for TAMP_BKP21R register  ***************/
#define TAMP_BKP21R_Pos                     (0U)
#define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP21R                         TAMP_BKP21R_Msk

/********************  Bits definition for TAMP_BKP22R register  ***************/
#define TAMP_BKP22R_Pos                     (0U)
#define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP22R                         TAMP_BKP22R_Msk

/********************  Bits definition for TAMP_BKP23R register  ***************/
#define TAMP_BKP23R_Pos                     (0U)
#define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP23R                         TAMP_BKP23R_Msk

/********************  Bits definition for TAMP_BKP24R register  ***************/
#define TAMP_BKP24R_Pos                     (0U)
#define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP24R                         TAMP_BKP24R_Msk

/********************  Bits definition for TAMP_BKP25R register  ***************/
#define TAMP_BKP25R_Pos                     (0U)
#define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP25R                         TAMP_BKP25R_Msk

/********************  Bits definition for TAMP_BKP26R register  ***************/
#define TAMP_BKP26R_Pos                     (0U)
#define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP26R                         TAMP_BKP26R_Msk

/********************  Bits definition for TAMP_BKP27R register  ***************/
#define TAMP_BKP27R_Pos                     (0U)
#define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP27R                         TAMP_BKP27R_Msk

/********************  Bits definition for TAMP_BKP28R register  ***************/
#define TAMP_BKP28R_Pos                     (0U)
#define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP28R                         TAMP_BKP28R_Msk

/********************  Bits definition for TAMP_BKP29R register  ***************/
#define TAMP_BKP29R_Pos                     (0U)
#define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP29R                         TAMP_BKP29R_Msk

/********************  Bits definition for TAMP_BKP30R register  ***************/
#define TAMP_BKP30R_Pos                     (0U)
#define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP30R                         TAMP_BKP30R_Msk

/********************  Bits definition for TAMP_BKP31R register  ***************/
#define TAMP_BKP31R_Pos                     (0U)
#define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP31R                         TAMP_BKP31R_Msk


/******************************************************************************/
/*                                                                            */
/*                                    TIM                                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for TIM_CR1 register  ********************/
#define TIM_CR1_CEN_Pos                     (0U)
#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)              /*!< 0x00000001 */
#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                         /*!<Counter enable */
#define TIM_CR1_UDIS_Pos                    (1U)
#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)             /*!< 0x00000002 */
#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                        /*!<Update disable */
#define TIM_CR1_URS_Pos                     (2U)
#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)              /*!< 0x00000004 */
#define TIM_CR1_URS                         TIM_CR1_URS_Msk                         /*!<Update request source */
#define TIM_CR1_OPM_Pos                     (3U)
#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)              /*!< 0x00000008 */
#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                         /*!<One pulse mode */
#define TIM_CR1_DIR_Pos                     (4U)
#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)              /*!< 0x00000010 */
#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                         /*!<Direction */
#define TIM_CR1_CMS_Pos                     (5U)
#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)              /*!< 0x00000060 */
#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                         /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)              /*!< 0x00000020 */
#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)              /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos                    (7U)
#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)             /*!< 0x00000080 */
#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                        /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos                     (8U)
#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)              /*!< 0x00000300 */
#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                         /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)              /*!< 0x00000100 */
#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)              /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos                (11U)
#define TIM_CR1_UIFREMAP_Msk                (0x1UL << TIM_CR1_UIFREMAP_Pos)         /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP                    TIM_CR1_UIFREMAP_Msk                    /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos                  (12U)
#define TIM_CR1_DITHEN_Msk                  (0x1UL << TIM_CR1_DITHEN_Pos)           /*!< 0x00001000 */
#define TIM_CR1_DITHEN                      TIM_CR1_DITHEN_Msk                      /*!<Dithering enable */

/*******************  Bit definition for TIM_CR2 register  ********************/
#define TIM_CR2_CCPC_Pos                    (0U)
#define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)             /*!< 0x00000001 */
#define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                        /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos                    (2U)
#define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)             /*!< 0x00000004 */
#define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                        /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos                    (3U)
#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)             /*!< 0x00000008 */
#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                        /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos                     (4U)
#define TIM_CR2_MMS_Msk                     (0x200007UL << TIM_CR2_MMS_Pos)         /*!< 0x02000070 */
#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                         /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0                       (0x000001UL << TIM_CR2_MMS_Pos)         /*!< 0x00000010 */
#define TIM_CR2_MMS_1                       (0x000002UL << TIM_CR2_MMS_Pos)         /*!< 0x00000020 */
#define TIM_CR2_MMS_2                       (0x000004UL << TIM_CR2_MMS_Pos)         /*!< 0x00000040 */
#define TIM_CR2_MMS_3                       (0x200000UL << TIM_CR2_MMS_Pos)         /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos                    (7U)
#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)             /*!< 0x00000080 */
#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                        /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos                    (8U)
#define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)             /*!< 0x00000100 */
#define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                        /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos                   (9U)
#define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)            /*!< 0x00000200 */
#define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                       /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos                    (10U)
#define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)             /*!< 0x00000400 */
#define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                        /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos                   (11U)
#define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)            /*!< 0x00000800 */
#define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                       /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos                    (12U)
#define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)             /*!< 0x00001000 */
#define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                        /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos                   (13U)
#define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)            /*!< 0x00002000 */
#define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                       /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos                    (14U)
#define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)             /*!< 0x00004000 */
#define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                        /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos                   (15U)
#define TIM_CR2_OIS4N_Msk                   (0x1UL << TIM_CR2_OIS4N_Pos)            /*!< 0x00008000 */
#define TIM_CR2_OIS4N                       TIM_CR2_OIS4N_Msk                       /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos                    (16U)
#define TIM_CR2_OIS5_Msk                    (0x1UL << TIM_CR2_OIS5_Pos)             /*!< 0x00010000 */
#define TIM_CR2_OIS5                        TIM_CR2_OIS5_Msk                        /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos                    (18U)
#define TIM_CR2_OIS6_Msk                    (0x1UL << TIM_CR2_OIS6_Pos)             /*!< 0x00040000 */
#define TIM_CR2_OIS6                        TIM_CR2_OIS6_Msk                        /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos                    (20U)
#define TIM_CR2_MMS2_Msk                    (0xFUL << TIM_CR2_MMS2_Pos)             /*!< 0x00F00000 */
#define TIM_CR2_MMS2                        TIM_CR2_MMS2_Msk                        /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0                      (0x1UL << TIM_CR2_MMS2_Pos)             /*!< 0x00100000 */
#define TIM_CR2_MMS2_1                      (0x2UL << TIM_CR2_MMS2_Pos)             /*!< 0x00200000 */
#define TIM_CR2_MMS2_2                      (0x4UL << TIM_CR2_MMS2_Pos)             /*!< 0x00400000 */
#define TIM_CR2_MMS2_3                      (0x8UL << TIM_CR2_MMS2_Pos)             /*!< 0x00800000 */

/*******************  Bit definition for TIM_SMCR register  *******************/
#define TIM_SMCR_SMS_Pos                    (0U)
#define TIM_SMCR_SMS_Msk                    (0x10007UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010007 */
#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                        /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0                      (0x00001UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
#define TIM_SMCR_SMS_1                      (0x00002UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
#define TIM_SMCR_SMS_2                      (0x00004UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
#define TIM_SMCR_SMS_3                      (0x10000UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010000 */
#define TIM_SMCR_TS_Pos                     (4U)
#define TIM_SMCR_TS_Msk                     (0x30007UL << TIM_SMCR_TS_Pos)          /*!< 0x00300070 */
#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                         /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0                       (0x00001UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
#define TIM_SMCR_TS_1                       (0x00002UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
#define TIM_SMCR_TS_2                       (0x00004UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
#define TIM_SMCR_TS_3                       (0x10000UL << TIM_SMCR_TS_Pos)          /*!< 0x00100000 */
#define TIM_SMCR_TS_4                       (0x20000UL << TIM_SMCR_TS_Pos)          /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos                    (7U)
#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)             /*!< 0x00000080 */
#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                        /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos                    (8U)
#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)             /*!< 0x00000F00 */
#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                        /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000100 */
#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000200 */
#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000400 */
#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos                   (12U)
#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00003000 */
#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                       /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos                    (14U)
#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)             /*!< 0x00004000 */
#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                        /*!<External clock enable */
#define TIM_SMCR_ETP_Pos                    (15U)
#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)             /*!< 0x00008000 */
#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                        /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos                  (24U)
#define TIM_SMCR_SMSPE_Msk                  (0x1UL << TIM_SMCR_SMSPE_Pos)           /*!< 0x02000000 */
#define TIM_SMCR_SMSPE                      TIM_SMCR_SMSPE_Msk                      /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos                  (25U)
#define TIM_SMCR_SMSPS_Msk                  (0x1UL << TIM_SMCR_SMSPS_Pos)           /*!< 0x04000000 */
#define TIM_SMCR_SMSPS                      TIM_SMCR_SMSPS_Msk                      /*!<SMS preload source */

/*******************  Bit definition for TIM_DIER register  *******************/
#define TIM_DIER_UIE_Pos                    (0U)
#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)             /*!< 0x00000001 */
#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                        /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos                  (1U)
#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)           /*!< 0x00000002 */
#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                      /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos                  (2U)
#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)           /*!< 0x00000004 */
#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                      /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos                  (3U)
#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)           /*!< 0x00000008 */
#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                      /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos                  (4U)
#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)           /*!< 0x00000010 */
#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                      /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos                  (5U)
#define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)           /*!< 0x00000020 */
#define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                      /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos                    (6U)
#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)             /*!< 0x00000040 */
#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                        /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos                    (7U)
#define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)             /*!< 0x00000080 */
#define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                        /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos                    (8U)
#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)             /*!< 0x00000100 */
#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                        /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos                  (9U)
#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)           /*!< 0x00000200 */
#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                      /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos                  (10U)
#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)           /*!< 0x00000400 */
#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                      /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos                  (11U)
#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)           /*!< 0x00000800 */
#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                      /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos                  (12U)
#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)           /*!< 0x00001000 */
#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                      /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos                  (13U)
#define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)           /*!< 0x00002000 */
#define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                      /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos                    (14U)
#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)             /*!< 0x00004000 */
#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                        /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos                  (20U)
#define TIM_DIER_IDXIE_Msk                  (0x1UL << TIM_DIER_IDXIE_Pos)           /*!< 0x00100000 */
#define TIM_DIER_IDXIE                      TIM_DIER_IDXIE_Msk                      /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos                  (21U)
#define TIM_DIER_DIRIE_Msk                  (0x1UL << TIM_DIER_DIRIE_Pos)           /*!< 0x00200000 */
#define TIM_DIER_DIRIE                      TIM_DIER_DIRIE_Msk                      /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos                 (22U)
#define TIM_DIER_IERRIE_Msk                 (0x1UL << TIM_DIER_IERRIE_Pos)          /*!< 0x00400000 */
#define TIM_DIER_IERRIE                     TIM_DIER_IERRIE_Msk                     /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos                 (23U)
#define TIM_DIER_TERRIE_Msk                 (0x1UL << TIM_DIER_TERRIE_Pos)          /*!< 0x00800000 */
#define TIM_DIER_TERRIE                     TIM_DIER_TERRIE_Msk                     /*!<Encoder transition error enable */

/********************  Bit definition for TIM_SR register  ********************/
#define TIM_SR_UIF_Pos                      (0U)
#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)               /*!< 0x00000001 */
#define TIM_SR_UIF                          TIM_SR_UIF_Msk                          /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos                    (1U)
#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)             /*!< 0x00000002 */
#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                        /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos                    (2U)
#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)             /*!< 0x00000004 */
#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                        /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos                    (3U)
#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)             /*!< 0x00000008 */
#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                        /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos                    (4U)
#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)             /*!< 0x00000010 */
#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                        /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos                    (5U)
#define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)             /*!< 0x00000020 */
#define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                        /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos                      (6U)
#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)               /*!< 0x00000040 */
#define TIM_SR_TIF                          TIM_SR_TIF_Msk                          /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos                      (7U)
#define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)               /*!< 0x00000080 */
#define TIM_SR_BIF                          TIM_SR_BIF_Msk                          /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos                     (8U)
#define TIM_SR_B2IF_Msk                     (0x1UL << TIM_SR_B2IF_Pos)              /*!< 0x00000100 */
#define TIM_SR_B2IF                         TIM_SR_B2IF_Msk                         /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos                    (9U)
#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)             /*!< 0x00000200 */
#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                        /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos                    (10U)
#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)             /*!< 0x00000400 */
#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                        /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos                    (11U)
#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)             /*!< 0x00000800 */
#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                        /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos                    (12U)
#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)             /*!< 0x00001000 */
#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                        /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos                     (13U)
#define TIM_SR_SBIF_Msk                     (0x1UL << TIM_SR_SBIF_Pos)              /*!< 0x00002000 */
#define TIM_SR_SBIF                         TIM_SR_SBIF_Msk                         /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos                    (16U)
#define TIM_SR_CC5IF_Msk                    (0x1UL << TIM_SR_CC5IF_Pos)             /*!< 0x00010000 */
#define TIM_SR_CC5IF                        TIM_SR_CC5IF_Msk                        /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos                    (17U)
#define TIM_SR_CC6IF_Msk                    (0x1UL << TIM_SR_CC6IF_Pos)             /*!< 0x00020000 */
#define TIM_SR_CC6IF                        TIM_SR_CC6IF_Msk                        /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos                     (20U)
#define TIM_SR_IDXF_Msk                     (0x1UL << TIM_SR_IDXF_Pos)              /*!< 0x00100000 */
#define TIM_SR_IDXF                         TIM_SR_IDXF_Msk                         /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos                     (21U)
#define TIM_SR_DIRF_Msk                     (0x1UL << TIM_SR_DIRF_Pos)              /*!< 0x00200000 */
#define TIM_SR_DIRF                         TIM_SR_DIRF_Msk                         /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos                    (22U)
#define TIM_SR_IERRF_Msk                    (0x1UL << TIM_SR_IERRF_Pos)             /*!< 0x00400000 */
#define TIM_SR_IERRF                        TIM_SR_IERRF_Msk                        /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos                    (23U)
#define TIM_SR_TERRF_Msk                    (0x1UL << TIM_SR_TERRF_Pos)             /*!< 0x00800000 */
#define TIM_SR_TERRF                        TIM_SR_TERRF_Msk                        /*!<Encoder transition error flag */

/*******************  Bit definition for TIM_EGR register  ********************/
#define TIM_EGR_UG_Pos                      (0U)
#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)               /*!< 0x00000001 */
#define TIM_EGR_UG                          TIM_EGR_UG_Msk                          /*!<Update Generation */
#define TIM_EGR_CC1G_Pos                    (1U)
#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)             /*!< 0x00000002 */
#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                        /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos                    (2U)
#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)             /*!< 0x00000004 */
#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                        /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos                    (3U)
#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)             /*!< 0x00000008 */
#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                        /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos                    (4U)
#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)             /*!< 0x00000010 */
#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                        /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos                    (5U)
#define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)             /*!< 0x00000020 */
#define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                        /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos                      (6U)
#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)               /*!< 0x00000040 */
#define TIM_EGR_TG                          TIM_EGR_TG_Msk                          /*!<Trigger Generation */
#define TIM_EGR_BG_Pos                      (7U)
#define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)               /*!< 0x00000080 */
#define TIM_EGR_BG                          TIM_EGR_BG_Msk                          /*!<Break Generation */
#define TIM_EGR_B2G_Pos                     (8U)
#define TIM_EGR_B2G_Msk                     (0x1UL << TIM_EGR_B2G_Pos)              /*!< 0x00000100 */
#define TIM_EGR_B2G                         TIM_EGR_B2G_Msk                         /*!<Break 2 Generation */

/******************  Bit definition for TIM_CCMR1 register  *******************/
#define TIM_CCMR1_CC1S_Pos                  (0U)
#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000003 */
#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                      /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos                 (2U)
#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)          /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                     /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos                 (3U)
#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)          /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                     /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos                  (4U)
#define TIM_CCMR1_OC1M_Msk                  (0x1007UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010070 */
#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                      /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0                    (0x0001UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1                    (0x0002UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2                    (0x0004UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3                    (0x1000UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos                 (7U)
#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)          /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                     /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos                  (8U)
#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000300 */
#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                      /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos                 (10U)
#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)          /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                     /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos                 (11U)
#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)          /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                     /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos                  (12U)
#define TIM_CCMR1_OC2M_Msk                  (0x1007UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01007000 */
#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                      /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0                    (0x0001UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1                    (0x0002UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2                    (0x0004UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3                    (0x1000UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos                 (15U)
#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)          /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                     /*!<Output Compare 2 Clear Enable */

/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos                (2U)
#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk                    /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos                  (4U)
#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)           /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                      /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos                (10U)
#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk                    /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos                  (12U)
#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)           /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                      /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00008000 */

/******************  Bit definition for TIM_CCMR2 register  *******************/
#define TIM_CCMR2_CC3S_Pos                  (0U)
#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000003 */
#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                      /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos                 (2U)
#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)          /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                     /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos                 (3U)
#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)          /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                     /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos                  (4U)
#define TIM_CCMR2_OC3M_Msk                  (0x1007UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010070 */
#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                      /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0                    (0x0001UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1                    (0x0002UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2                    (0x0004UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3                    (0x1000UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos                 (7U)
#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)          /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                     /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos                  (8U)
#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000300 */
#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                      /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos                 (10U)
#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)          /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                     /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos                 (11U)
#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)          /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                     /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos                  (12U)
#define TIM_CCMR2_OC4M_Msk                  (0x1007UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01007000 */
#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                      /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0                    (0x0001UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1                    (0x0002UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2                    (0x0004UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3                    (0x1000UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos                 (15U)
#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)          /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                     /*!<Output Compare 4 Clear Enable */

/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos                (2U)
#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk                    /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos                  (4U)
#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)           /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                      /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos                (10U)
#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk                    /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos                  (12U)
#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)           /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                      /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00008000 */

/******************  Bit definition for TIM_CCMR3 register  *******************/
#define TIM_CCMR3_OC5FE_Pos                 (2U)
#define TIM_CCMR3_OC5FE_Msk                 (0x1UL << TIM_CCMR3_OC5FE_Pos)          /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE                     TIM_CCMR3_OC5FE_Msk                     /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos                 (3U)
#define TIM_CCMR3_OC5PE_Msk                 (0x1UL << TIM_CCMR3_OC5PE_Pos)          /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE                     TIM_CCMR3_OC5PE_Msk                     /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos                  (4U)
#define TIM_CCMR3_OC5M_Msk                  (0x1007UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010070 */
#define TIM_CCMR3_OC5M                      TIM_CCMR3_OC5M_Msk                      /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0                    (0x0001UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1                    (0x0002UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2                    (0x0004UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3                    (0x1000UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos                 (7U)
#define TIM_CCMR3_OC5CE_Msk                 (0x1UL << TIM_CCMR3_OC5CE_Pos)          /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE                     TIM_CCMR3_OC5CE_Msk                     /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos                 (10U)
#define TIM_CCMR3_OC6FE_Msk                 (0x1UL << TIM_CCMR3_OC6FE_Pos)          /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE                     TIM_CCMR3_OC6FE_Msk                     /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos                 (11U)
#define TIM_CCMR3_OC6PE_Msk                 (0x1UL << TIM_CCMR3_OC6PE_Pos)          /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE                     TIM_CCMR3_OC6PE_Msk                     /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos                  (12U)
#define TIM_CCMR3_OC6M_Msk                  (0x1007UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01007000 */
#define TIM_CCMR3_OC6M                      TIM_CCMR3_OC6M_Msk                      /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0                    (0x0001UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1                    (0x0002UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2                    (0x0004UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3                    (0x1000UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos                 (15U)
#define TIM_CCMR3_OC6CE_Msk                 (0x1UL << TIM_CCMR3_OC6CE_Pos)          /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE                     TIM_CCMR3_OC6CE_Msk                     /*!<Output Compare 6 Clear Enable */

/*******************  Bit definition for TIM_CCER register  *******************/
#define TIM_CCER_CC1E_Pos                   (0U)
#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)            /*!< 0x00000001 */
#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                       /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos                   (1U)
#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)            /*!< 0x00000002 */
#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                       /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos                  (2U)
#define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)           /*!< 0x00000004 */
#define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                      /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos                  (3U)
#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)           /*!< 0x00000008 */
#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                      /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos                   (4U)
#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)            /*!< 0x00000010 */
#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                       /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos                   (5U)
#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)            /*!< 0x00000020 */
#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                       /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos                  (6U)
#define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)           /*!< 0x00000040 */
#define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                      /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos                  (7U)
#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)           /*!< 0x00000080 */
#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                      /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos                   (8U)
#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)            /*!< 0x00000100 */
#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                       /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos                   (9U)
#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)            /*!< 0x00000200 */
#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                       /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos                  (10U)
#define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)           /*!< 0x00000400 */
#define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                      /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos                  (11U)
#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)           /*!< 0x00000800 */
#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                      /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos                   (12U)
#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)            /*!< 0x00001000 */
#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                       /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos                   (13U)
#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)            /*!< 0x00002000 */
#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                       /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos                  (14U)
#define TIM_CCER_CC4NE_Msk                  (0x1UL << TIM_CCER_CC4NE_Pos)           /*!< 0x00004000 */
#define TIM_CCER_CC4NE                      TIM_CCER_CC4NE_Msk                      /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos                  (15U)
#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)           /*!< 0x00008000 */
#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                      /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos                   (16U)
#define TIM_CCER_CC5E_Msk                   (0x1UL << TIM_CCER_CC5E_Pos)            /*!< 0x00010000 */
#define TIM_CCER_CC5E                       TIM_CCER_CC5E_Msk                       /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos                   (17U)
#define TIM_CCER_CC5P_Msk                   (0x1UL << TIM_CCER_CC5P_Pos)            /*!< 0x00020000 */
#define TIM_CCER_CC5P                       TIM_CCER_CC5P_Msk                       /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos                   (20U)
#define TIM_CCER_CC6E_Msk                   (0x1UL << TIM_CCER_CC6E_Pos)            /*!< 0x00100000 */
#define TIM_CCER_CC6E                       TIM_CCER_CC6E_Msk                       /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos                   (21U)
#define TIM_CCER_CC6P_Msk                   (0x1UL << TIM_CCER_CC6P_Pos)            /*!< 0x00200000 */
#define TIM_CCER_CC6P                       TIM_CCER_CC6P_Msk                       /*!<Capture/Compare 6 output Polarity */

/*******************  Bit definition for TIM_CNT register  ********************/
#define TIM_CNT_CNT_Pos                     (0U)
#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)       /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                         /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos                  (31U)
#define TIM_CNT_UIFCPY_Msk                  (0x1UL << TIM_CNT_UIFCPY_Pos)           /*!< 0x80000000 */
#define TIM_CNT_UIFCPY                      TIM_CNT_UIFCPY_Msk                      /*!<Update interrupt flag copy (if UIFREMAP=1) */

/*******************  Bit definition for TIM_PSC register  ********************/
#define TIM_PSC_PSC_Pos                     (0U)
#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)           /*!< 0x0000FFFF */
#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                         /*!<Prescaler Value */

/*******************  Bit definition for TIM_ARR register  ********************/
#define TIM_ARR_ARR_Pos                     (0U)
#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)       /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                         /*!<Actual auto-reload Value */

/*******************  Bit definition for TIM_RCR register  ********************/
#define TIM_RCR_REP_Pos                     (0U)
#define TIM_RCR_REP_Msk                     (0xFFFFUL << TIM_RCR_REP_Pos)           /*!< 0x0000FFFF */
#define TIM_RCR_REP                         TIM_RCR_REP_Msk                         /*!<Repetition Counter Value */

/*******************  Bit definition for TIM_CCR1 register  *******************/
#define TIM_CCR1_CCR1_Pos                   (0U)
#define TIM_CCR1_CCR1_Msk                   (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0xFFFFFFFFUL */
#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                       /*!<Capture/Compare 1 Value */

/*******************  Bit definition for TIM_CCR2 register  *******************/
#define TIM_CCR2_CCR2_Pos                   (0U)
#define TIM_CCR2_CCR2_Msk                   (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0xFFFFFFFFUL */
#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                       /*!<Capture/Compare 2 Value */

/*******************  Bit definition for TIM_CCR3 register  *******************/
#define TIM_CCR3_CCR3_Pos                   (0U)
#define TIM_CCR3_CCR3_Msk                   (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0xFFFFFFFFUL */
#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                       /*!<Capture/Compare 3 Value */

/*******************  Bit definition for TIM_CCR4 register  *******************/
#define TIM_CCR4_CCR4_Pos                   (0U)
#define TIM_CCR4_CCR4_Msk                   (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0xFFFFFFFFUL */
#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                       /*!<Capture/Compare 4 Value */

/*******************  Bit definition for TIM_CCR5 register  *******************/
#define TIM_CCR5_CCR5_Pos                   (0U)
#define TIM_CCR5_CCR5_Msk                   (0xFFFFFUL << TIM_CCR5_CCR5_Pos)        /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5                       TIM_CCR5_CCR5_Msk                       /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos                  (29U)
#define TIM_CCR5_GC5C1_Msk                  (0x1UL << TIM_CCR5_GC5C1_Pos)           /*!< 0x20000000 */
#define TIM_CCR5_GC5C1                      TIM_CCR5_GC5C1_Msk                      /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos                  (30U)
#define TIM_CCR5_GC5C2_Msk                  (0x1UL << TIM_CCR5_GC5C2_Pos)           /*!< 0x40000000 */
#define TIM_CCR5_GC5C2                      TIM_CCR5_GC5C2_Msk                      /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos                  (31U)
#define TIM_CCR5_GC5C3_Msk                  (0x1UL << TIM_CCR5_GC5C3_Pos)           /*!< 0x80000000 */
#define TIM_CCR5_GC5C3                      TIM_CCR5_GC5C3_Msk                      /*!<Group Channel 5 and Channel 3 */

/*******************  Bit definition for TIM_CCR6 register  *******************/
#define TIM_CCR6_CCR6_Pos                   (0U)
#define TIM_CCR6_CCR6_Msk                   (0xFFFFFUL << TIM_CCR6_CCR6_Pos)        /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6                       TIM_CCR6_CCR6_Msk                       /*!<Capture/Compare 6 Value */

/*******************  Bit definition for TIM_BDTR register  *******************/
#define TIM_BDTR_DTG_Pos                    (0U)
#define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)            /*!< 0x000000FF */
#define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                        /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000001 */
#define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000002 */
#define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000004 */
#define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000008 */
#define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000010 */
#define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000020 */
#define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000040 */
#define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos                   (8U)
#define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000300 */
#define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                       /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos                   (10U)
#define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)            /*!< 0x00000400 */
#define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                       /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos                   (11U)
#define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)            /*!< 0x00000800 */
#define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                       /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos                    (12U)
#define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)             /*!< 0x00001000 */
#define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                        /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos                    (13U)
#define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)             /*!< 0x00002000 */
#define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                        /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos                    (14U)
#define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)             /*!< 0x00004000 */
#define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                        /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos                    (15U)
#define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)             /*!< 0x00008000 */
#define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                        /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos                    (16U)
#define TIM_BDTR_BKF_Msk                    (0xFUL << TIM_BDTR_BKF_Pos)             /*!< 0x000F0000 */
#define TIM_BDTR_BKF                        TIM_BDTR_BKF_Msk                        /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos                   (20U)
#define TIM_BDTR_BK2F_Msk                   (0xFUL << TIM_BDTR_BK2F_Pos)            /*!< 0x00F00000 */
#define TIM_BDTR_BK2F                       TIM_BDTR_BK2F_Msk                       /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos                   (24U)
#define TIM_BDTR_BK2E_Msk                   (0x1UL << TIM_BDTR_BK2E_Pos)            /*!< 0x01000000 */
#define TIM_BDTR_BK2E                       TIM_BDTR_BK2E_Msk                       /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos                   (25U)
#define TIM_BDTR_BK2P_Msk                   (0x1UL << TIM_BDTR_BK2P_Pos)            /*!< 0x02000000 */
#define TIM_BDTR_BK2P                       TIM_BDTR_BK2P_Msk                       /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos                 (26U)
#define TIM_BDTR_BKDSRM_Msk                 (0x1UL << TIM_BDTR_BKDSRM_Pos)          /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM                     TIM_BDTR_BKDSRM_Msk                     /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos                (27U)
#define TIM_BDTR_BK2DSRM_Msk                (0x1UL << TIM_BDTR_BK2DSRM_Pos)         /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM                    TIM_BDTR_BK2DSRM_Msk                    /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos                  (28U)
#define TIM_BDTR_BKBID_Msk                  (0x1UL << TIM_BDTR_BKBID_Pos)           /*!< 0x10000000 */
#define TIM_BDTR_BKBID                      TIM_BDTR_BKBID_Msk                      /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos                 (29U)
#define TIM_BDTR_BK2BID_Msk                 (0x1UL << TIM_BDTR_BK2BID_Pos)          /*!< 0x20000000 */
#define TIM_BDTR_BK2BID                     TIM_BDTR_BK2BID_Msk                     /*!<Break2 BIDirectional */

/*******************  Bit definition for TIM_DCR register  ********************/
#define TIM_DCR_DBA_Pos                     (0U)
#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)             /*!< 0x0000001F */
#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                         /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)             /*!< 0x00000001 */
#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)             /*!< 0x00000002 */
#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)             /*!< 0x00000004 */
#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)             /*!< 0x00000008 */
#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)             /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos                     (8U)
#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)             /*!< 0x00001F00 */
#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                         /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)             /*!< 0x00000100 */
#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)             /*!< 0x00000200 */
#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)             /*!< 0x00000400 */
#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)             /*!< 0x00000800 */
#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)             /*!< 0x00001000 */
#define TIM_DCR_DBSS_Pos                    (16U)
#define TIM_DCR_DBSS_Msk                    (0xFUL << TIM_DCR_DBSS_Pos)             /*!< 0x000F0000 */
#define TIM_DCR_DBSS                        TIM_DCR_DBSS_Msk                        /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
#define TIM_DCR_DBSS_0                      (0x01UL << TIM_DCR_DBSS_Pos)            /*!< 0x00010000 */
#define TIM_DCR_DBSS_1                      (0x02UL << TIM_DCR_DBSS_Pos)            /*!< 0x00020000 */
#define TIM_DCR_DBSS_2                      (0x04UL << TIM_DCR_DBSS_Pos)            /*!< 0x00040000 */
#define TIM_DCR_DBSS_3                      (0x08UL << TIM_DCR_DBSS_Pos)            /*!< 0x00080000 */

/*******************  Bit definition for TIM_AF1 register  *******************/
#define TIM_AF1_BKINE_Pos                  (0U)
#define TIM_AF1_BKINE_Msk                  (0x1UL << TIM_AF1_BKINE_Pos)           /*!< 0x00000001 */
#define TIM_AF1_BKINE                      TIM_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
#define TIM_AF1_BKINP_Pos                  (9U)
#define TIM_AF1_BKINP_Msk                  (0x1UL << TIM_AF1_BKINP_Pos)           /*!< 0x00000200 */
#define TIM_AF1_BKINP                      TIM_AF1_BKINP_Msk                      /*!<BRK BKIN input polarity */
#define TIM_AF1_ETRSEL_Pos                 (14U)
#define TIM_AF1_ETRSEL_Msk                 (0xFUL << TIM_AF1_ETRSEL_Pos)          /*!< 0x0003C000 */
#define TIM_AF1_ETRSEL                     TIM_AF1_ETRSEL_Msk                     /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM_AF1_ETRSEL_0                   (0x1UL << TIM_AF1_ETRSEL_Pos)          /*!< 0x00004000 */
#define TIM_AF1_ETRSEL_1                   (0x2UL << TIM_AF1_ETRSEL_Pos)          /*!< 0x00008000 */
#define TIM_AF1_ETRSEL_2                   (0x4UL << TIM_AF1_ETRSEL_Pos)          /*!< 0x00010000 */
#define TIM_AF1_ETRSEL_3                   (0x8UL << TIM_AF1_ETRSEL_Pos)          /*!< 0x00020000 */

/*******************  Bit definition for TIM1_AF2 register  *********************/
#define TIM_AF2_BK2INE_Pos                 (0U)
#define TIM_AF2_BK2INE_Msk                 (0x1UL << TIM_AF2_BK2INE_Pos)          /*!< 0x00000001 */
#define TIM_AF2_BK2INE                     TIM_AF2_BK2INE_Msk                     /*!<BRK2 BKIN input enable */
#define TIM_AF2_BK2INP_Pos                 (9U)
#define TIM_AF2_BK2INP_Msk                 (0x1UL << TIM_AF2_BK2INP_Pos)          /*!< 0x00000200 */
#define TIM_AF2_BK2INP                     TIM_AF2_BK2INP_Msk                     /*!<BRK2 BKIN input polarity */

/*******************  Bit definition for TIM_TISEL register  *********************/
#define TIM_TISEL_TI1SEL_Pos                (0U)
#define TIM_TISEL_TI1SEL_Msk                (0xFUL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL                    TIM_TISEL_TI1SEL_Msk                    /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0                  (0x1UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1                  (0x2UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2                  (0x4UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3                  (0x8UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos                (8U)
#define TIM_TISEL_TI2SEL_Msk                (0xFUL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL                    TIM_TISEL_TI2SEL_Msk                    /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0                  (0x1UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1                  (0x2UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2                  (0x4UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3                  (0x8UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos                (16U)
#define TIM_TISEL_TI3SEL_Msk                (0xFUL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL                    TIM_TISEL_TI3SEL_Msk                    /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0                  (0x1UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1                  (0x2UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2                  (0x4UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3                  (0x8UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos                (24U)
#define TIM_TISEL_TI4SEL_Msk                (0xFUL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL                    TIM_TISEL_TI4SEL_Msk                    /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0                  (0x1UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1                  (0x2UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2                  (0x4UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3                  (0x8UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x08000000 */

/*******************  Bit definition for TIM_DTR2 register  *********************/
#define TIM_DTR2_DTGF_Pos                   (0U)
#define TIM_DTR2_DTGF_Msk                   (0xFFUL << TIM_DTR2_DTGF_Pos)           /*!< 0x0000000F */
#define TIM_DTR2_DTGF                       TIM_DTR2_DTGF_Msk                       /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0                     (0x01UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1                     (0x02UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2                     (0x04UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3                     (0x08UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4                     (0x10UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5                     (0x20UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6                     (0x40UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7                     (0x80UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos                   (16U)
#define TIM_DTR2_DTAE_Msk                   (0x1UL << TIM_DTR2_DTAE_Pos)            /*!< 0x00004000 */
#define TIM_DTR2_DTAE                       TIM_DTR2_DTAE_Msk                       /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos                   (17U)
#define TIM_DTR2_DTPE_Msk                   (0x1UL << TIM_DTR2_DTPE_Pos)            /*!< 0x00008000 */
#define TIM_DTR2_DTPE                       TIM_DTR2_DTPE_Msk                       /*!<Deadtime prelaod enable */

/*******************  Bit definition for TIM_ECR register  *********************/
#define TIM_ECR_IE_Pos                      (0U)
#define TIM_ECR_IE_Msk                      (0x1UL << TIM_ECR_IE_Pos)               /*!< 0x00000001 */
#define TIM_ECR_IE                          TIM_ECR_IE_Msk                          /*!<Index enable */
#define TIM_ECR_IDIR_Pos                    (1U)
#define TIM_ECR_IDIR_Msk                    (0x3UL << TIM_ECR_IDIR_Pos)             /*!< 0x00000006 */
#define TIM_ECR_IDIR                        TIM_ECR_IDIR_Msk                        /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0                      (0x01UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000001 */
#define TIM_ECR_IDIR_1                      (0x02UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000002 */
#define TIM_ECR_IBLK_Pos                    (3U)
#define TIM_ECR_IBLK_Msk                    (0x3UL << TIM_ECR_IBLK_Pos)             /*!< 0x00000018 */
#define TIM_ECR_IBLK                        TIM_ECR_IBLK_Msk                        /*!<IBLK[1:0] bits (Index blanking)*/
#define TIM_ECR_IBLK_0                      (0x01UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000008 */
#define TIM_ECR_IBLK_1                      (0x02UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000010 */
#define TIM_ECR_FIDX_Pos                    (5U)
#define TIM_ECR_FIDX_Msk                    (0x1UL << TIM_ECR_FIDX_Pos)             /*!< 0x00000020 */
#define TIM_ECR_FIDX                        TIM_ECR_FIDX_Msk                        /*!<First index enable */
#define TIM_ECR_IPOS_Pos                    (6U)
#define TIM_ECR_IPOS_Msk                    (0x3UL << TIM_ECR_IPOS_Pos)             /*!< 0x000000C0 */
#define TIM_ECR_IPOS                        TIM_ECR_IPOS_Msk                        /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0                      (0x01UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000040 */
#define TIM_ECR_IPOS_1                      (0x02UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000080 */
#define TIM_ECR_PW_Pos                      (16U)
#define TIM_ECR_PW_Msk                      (0xFFUL << TIM_ECR_PW_Pos)              /*!< 0x00FF0000 */
#define TIM_ECR_PW                          TIM_ECR_PW_Msk                          /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0                        (0x01UL << TIM_ECR_PW_Pos)              /*!< 0x00010000 */
#define TIM_ECR_PW_1                        (0x02UL << TIM_ECR_PW_Pos)              /*!< 0x00020000 */
#define TIM_ECR_PW_2                        (0x04UL << TIM_ECR_PW_Pos)              /*!< 0x00040000 */
#define TIM_ECR_PW_3                        (0x08UL << TIM_ECR_PW_Pos)              /*!< 0x00080000 */
#define TIM_ECR_PW_4                        (0x10UL << TIM_ECR_PW_Pos)              /*!< 0x00100000 */
#define TIM_ECR_PW_5                        (0x20UL << TIM_ECR_PW_Pos)              /*!< 0x00200000 */
#define TIM_ECR_PW_6                        (0x40UL << TIM_ECR_PW_Pos)              /*!< 0x00400000 */
#define TIM_ECR_PW_7                        (0x80UL << TIM_ECR_PW_Pos)              /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos                  (24U)
#define TIM_ECR_PWPRSC_Msk                  (0x7UL << TIM_ECR_PWPRSC_Pos)           /*!< 0x07000000 */
#define TIM_ECR_PWPRSC                      TIM_ECR_PWPRSC_Msk                      /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0                    (0x01UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1                    (0x02UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2                    (0x04UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x04000000 */

/*******************  Bit definition for TIM_DMAR register  *******************/
#define TIM_DMAR_DMAB_Pos                   (0U)
#define TIM_DMAR_DMAB_Msk                   (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */


/*********************************************************************************/
/*                                                                               */
/*                                    UCPD                                       */
/*                                                                               */
/*********************************************************************************/
/********************  Bits definition for UCPD_CFG1 register  *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos                (6U)
#define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos              (11U)
#define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos            (20U)
#define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos               (29U)
#define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
#define UCPD_CFG1_RXDMAEN_Pos               (30U)
#define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
#define UCPD_CFG1_UCPDEN_Pos                (31U)
#define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */

/********************  Bits definition for UCPD_CFG2 register  *******************/
#define UCPD_CFG2_RXFILTDIS_Pos             (0U)
#define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos             (1U)
#define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos              (2U)
#define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos                 (3U)
#define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
#define UCPD_CFG2_RXAFILTEN_Pos             (8U)
#define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)   /*!< 0x00000100 */
#define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk              /*!< Rx analog filter enable */

/********************  Bits definition for UCPD_CFG3 register  *******************/
#define UCPD_CFG3_TRIM_CC1_RD_Pos           (0U)
#define UCPD_CFG3_TRIM_CC1_RD_Msk           (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos)   /*!< 0x0000000F */
#define UCPD_CFG3_TRIM_CC1_RD               UCPD_CFG3_TRIM_CC1_RD_Msk              /*!< SW trim value for RD resistor (CC1) */
#define UCPD_CFG3_TRIM_CC1_RP_Pos           (9U)
#define UCPD_CFG3_TRIM_CC1_RP_Msk           (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos)   /*!< 0x00001E00 */
#define UCPD_CFG3_TRIM_CC1_RP               UCPD_CFG3_TRIM_CC1_RP_Msk              /*!< SW trim value for RP current sources (CC1) */
#define UCPD_CFG3_TRIM_CC2_RD_Pos           (16U)
#define UCPD_CFG3_TRIM_CC2_RD_Msk           (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos)   /*!< 0x000F0000 */
#define UCPD_CFG3_TRIM_CC2_RD               UCPD_CFG3_TRIM_CC2_RD_Msk              /*!< SW trim value for RD resistor (CC2) */
#define UCPD_CFG3_TRIM_CC2_RP_Pos           (25U)
#define UCPD_CFG3_TRIM_CC2_RP_Msk           (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos)   /*!< 0x1E000000 */
#define UCPD_CFG3_TRIM_CC2_RP               UCPD_CFG3_TRIM_CC2_RP_Msk              /*!< SW trim value for RP current sources (CC2) */

/********************  Bits definition for UCPD_CR register  *********************/
#define UCPD_CR_TXMODE_Pos                  (0U)
#define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
#define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
#define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos                  (2U)
#define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
#define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
#define UCPD_CR_TXHRST_Pos                  (3U)
#define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
#define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
#define UCPD_CR_RXMODE_Pos                  (4U)
#define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
#define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
#define UCPD_CR_PHYRXEN_Pos                 (5U)
#define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
#define UCPD_CR_PHYCCSEL_Pos                (6U)
#define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
#define UCPD_CR_ANASUBMODE_Pos              (7U)
#define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
#define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos                 (9U)
#define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
#define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
#define UCPD_CR_CCENABLE_Pos                (10U)
#define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
#define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
#define UCPD_CR_USEEXTPHY_Pos               (12U)
#define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)     /*!< 0x00001000 */
#define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                /*!< Controls enable of USB Power Delivery transmitter */
#define UCPD_CR_CC2VCONNEN_Pos              (13U)
#define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)    /*!< 0x00002000 */
#define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk               /*!< VCONN enable for CC2 */
#define UCPD_CR_CC1VCONNEN_Pos              (14U)
#define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)    /*!< 0x00004000 */
#define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk               /*!< VCONN enable for CC1 */
#define UCPD_CR_DBATEN_Pos                  (15U)
#define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)        /*!< 0x00008000 */
#define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                   /*!< Enable dead battery behavior (Active High) */
#define UCPD_CR_FRSRXEN_Pos                 (16U)
#define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)       /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                  /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos                   (17U)
#define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
#define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos                    (18U)
#define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
#define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
#define UCPD_CR_RPUSBABSENT_Pos             (19U)
#define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)   /*!< 0x00080000 */
#define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk              /*!<  */
#define UCPD_CR_CC1TCDIS_Pos                (20U)
#define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos                (21U)
#define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */

/********************  Bits definition for UCPD_IMR register  ********************/
#define UCPD_IMR_TXISIE_Pos                 (0U)
#define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
#define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
#define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
#define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
#define UCPD_IMR_TXMSGABTIE_Pos             (3U)
#define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
#define UCPD_IMR_HRSTDISCIE_Pos             (4U)
#define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
#define UCPD_IMR_HRSTSENTIE_Pos             (5U)
#define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
#define UCPD_IMR_TXUNDIE_Pos                (6U)
#define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
#define UCPD_IMR_RXNEIE_Pos                 (8U)
#define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
#define UCPD_IMR_RXORDDETIE_Pos             (9U)
#define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
#define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
#define UCPD_IMR_RXOVRIE_Pos                (11U)
#define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
#define UCPD_IMR_RXMSGENDIE_Pos             (12U)
#define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
#define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
#define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
#define UCPD_IMR_FRSEVTIE_Pos               (20U)
#define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)     /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                /*!< Fast Role Swap interrupt  */

/********************  Bits definition for UCPD_SR register  *********************/
#define UCPD_SR_TXIS_Pos                    (0U)
#define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
#define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
#define UCPD_SR_TXMSGDISC_Pos               (1U)
#define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
#define UCPD_SR_TXMSGSENT_Pos               (2U)
#define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
#define UCPD_SR_TXMSGABT_Pos                (3U)
#define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
#define UCPD_SR_HRSTDISC_Pos                (4U)
#define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
#define UCPD_SR_HRSTSENT_Pos                (5U)
#define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
#define UCPD_SR_TXUND_Pos                   (6U)
#define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
#define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
#define UCPD_SR_RXNE_Pos                    (8U)
#define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
#define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
#define UCPD_SR_RXORDDET_Pos                (9U)
#define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
#define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
#define UCPD_SR_RXHRSTDET_Pos               (10U)
#define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
#define UCPD_SR_RXOVR_Pos                   (11U)
#define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
#define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
#define UCPD_SR_RXMSGEND_Pos                (12U)
#define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
#define UCPD_SR_RXERR_Pos                   (13U)
#define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
#define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos               (14U)
#define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
#define UCPD_SR_TYPECEVT2_Pos               (15U)
#define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
#define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
#define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos                  (20U)
#define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)        /*!< 0x00100000 */
#define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                   /*!< Fast Role Swap detection event  */

/********************  Bits definition for UCPD_ICR register  ********************/
#define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
#define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
#define UCPD_ICR_TXMSGABTCF_Pos             (3U)
#define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
#define UCPD_ICR_HRSTDISCCF_Pos             (4U)
#define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
#define UCPD_ICR_HRSTSENTCF_Pos             (5U)
#define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
#define UCPD_ICR_TXUNDCF_Pos                (6U)
#define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
#define UCPD_ICR_RXORDDETCF_Pos             (9U)
#define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
#define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
#define UCPD_ICR_RXOVRCF_Pos                (11U)
#define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
#define UCPD_ICR_RXMSGENDCF_Pos             (12U)
#define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
#define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
#define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
#define UCPD_ICR_FRSEVTCF_Pos               (20U)
#define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)     /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                /*!< Fast Role Swap event flag clear  */

/********************  Bits definition for UCPD_TXORDSET register  ***************/
#define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */

/********************  Bits definition for UCPD_TXPAYSZ register  ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */

/********************  Bits definition for UCPD_TXDR register  *******************/
#define UCPD_TXDR_TXDATA_Pos                (0U)
#define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                 /*!< Tx Data Register */

/********************  Bits definition for UCPD_RXORDSET register  ***************/
#define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
#define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */

/********************  Bits definition for UCPD_RXPAYSZ register  ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */

/********************  Bits definition for UCPD_RXDR register  *******************/
#define UCPD_RXDR_RXDATA_Pos                (0U)
#define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */

/********************  Bits definition for UCPD_RXORDEXT1 register  **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */

/********************  Bits definition for UCPD_RXORDEXT2 register  **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */

/******************************************************************************/
/*                                                                            */
/*                                       USB_OTG                              */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos)      /*!< 0x00000001 */
#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk                /*!< Session request success */
#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos)         /*!< 0x00000002 */
#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk                   /*!< Session request */
#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos)    /*!< 0x00000004 */
#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk              /*!< VBUS valid override enable */
#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos)   /*!< 0x00000008 */
#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk             /*!< VBUS valid override value */
#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos)     /*!< 0x00000010 */
#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk               /*!< A-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos)    /*!< 0x00000020 */
#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk              /*!< A-peripheral session valid override value */
#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos)     /*!< 0x00000040 */
#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk               /*!< B-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos)    /*!< 0x00000080 */
#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk              /*!< B-peripheral session valid override value  */
#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos)     /*!< 0x00080000 */
#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk               /*!<  B-session valid*/

/********************  Bit definition for USB_OTG_HCFG register  ********************/
#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos)        /*!< 0x00000003 */
#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk                  /*!< FS/LS PHY clock select */
#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos)        /*!< 0x00000001 */
#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos)        /*!< 0x00000002 */
#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos)          /*!< 0x00000004 */
#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk                    /*!< FS- and LS-only support */

/********************  Bit definition for USB_OTG_DCFG register  ********************/
#define USB_OTG_DCFG_DSPD_Pos                    (0U)
#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos)           /*!< 0x00000003 */
#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk                     /*!< Device speed */
#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos)           /*!< 0x00000001 */
#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos)           /*!< 0x00000002 */
#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos)       /*!< 0x00000004 */
#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk                 /*!< Nonzero-length status OUT handshake */
#define USB_OTG_DCFG_DAD_Pos                     (4U)
#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos)           /*!< 0x000007F0 */
#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk                      /*!< Device address */
#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000010 */
#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000020 */
#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000040 */
#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000080 */
#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000100 */
#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000200 */
#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000400 */
#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos)          /*!< 0x00001800 */
#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk                    /*!< Periodic (micro)frame interval */
#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos)          /*!< 0x00000800 */
#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos)          /*!< 0x00001000 */
#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos)      /*!< 0x03000000 */
#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk                /*!< Periodic scheduling interval */
#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos)      /*!< 0x01000000 */
#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos)      /*!< 0x02000000 */

/********************  Bit definition for USB_OTG_PCGCR register  ********************/
#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos)       /*!< 0x00000001 */
#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk                 /*!< Stop PHY clock */
#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos)      /*!< 0x00000002 */
#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk                /*!< Gate HCLK */
#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos)       /*!< 0x00000010 */
#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk                 /*!< PHY suspended */

/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos)       /*!< 0x00000004 */
#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk                 /*!< Session end detected */
#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos)     /*!< 0x00000100 */
#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk               /*!< Session request success status change */
#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos)     /*!< 0x00000200 */
#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk               /*!< Host negotiation success status change */
#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos)      /*!< 0x00020000 */
#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk                /*!< Host negotiation detected */
#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos)     /*!< 0x00040000 */
#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk               /*!< A-device timeout change */
#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos)      /*!< 0x00080000 */
#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk                /*!< Debounce done */

/********************  Bit definition for USB_OTG_DCTL register  ********************/
#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos)         /*!< 0x00000001 */
#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk                   /*!< Remote wakeup signaling */
#define USB_OTG_DCTL_SDIS_Pos                    (1U)
#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos)           /*!< 0x00000002 */
#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk                     /*!< Soft disconnect */
#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos)         /*!< 0x00000004 */
#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk                   /*!< Global IN NAK status */
#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos)         /*!< 0x00000008 */
#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk                   /*!< Global OUT NAK status */
#define USB_OTG_DCTL_TCTL_Pos                    (4U)
#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000070 */
#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk                     /*!< Test control */
#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000010 */
#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000020 */
#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000040 */
#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos)         /*!< 0x00000080 */
#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk                   /*!< Set global IN NAK */
#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos)         /*!< 0x00000100 */
#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk                   /*!< Clear global IN NAK */
#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos)         /*!< 0x00000200 */
#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk                   /*!< Set global OUT NAK */
#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos)         /*!< 0x00000400 */
#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk                   /*!< Clear global OUT NAK */
#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos)       /*!< 0x00000800 */
#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk                 /*!< Power-on programming done */

/********************  Bit definition for USB_OTG_HFIR register  ********************/
#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos)       /*!< 0x0000FFFF */
#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk                    /*!< Frame interval */

/********************  Bit definition for USB_OTG_HFNUM register  ********************/
#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos)      /*!< 0x0000FFFF */
#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk                   /*!< Frame number */
#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos)      /*!< 0xFFFF0000 */
#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk                   /*!< Frame time remaining */

/********************  Bit definition for USB_OTG_DSTS register  ********************/
#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos)        /*!< 0x00000001 */
#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk                  /*!< Suspend status */

#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos)        /*!< 0x00000006 */
#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk                  /*!< Enumerated speed */
#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos)        /*!< 0x00000002 */
#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos)        /*!< 0x00000004 */
#define USB_OTG_DSTS_EERR_Pos                    (3U)
#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos)           /*!< 0x00000008 */
#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk                     /*!< Erratic error */
#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos)       /*!< 0x003FFF00 */
#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk                    /*!< Frame number of the received SOF */

/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos)        /*!< 0x00000001 */
#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk                  /*!< Global interrupt mask */
#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk               /*!< Burst length/type */
#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000002 */
#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000004 */
#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000008 */
#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000010 */
#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos)       /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk                 /*!< DMA enable */
#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos)     /*!< 0x00000080 */
#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk               /*!< TxFIFO empty level */
#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos)    /*!< 0x00000100 */
#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk              /*!< Periodic TxFIFO empty level */

/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000007 */
#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk                 /*!< FS timeout calibration */
#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos)      /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk                /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos)      /*!< 0x00000100 */
#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk                /*!< SRP-capable */
#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos)      /*!< 0x00000200 */
#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk                /*!< HNP-capable */
#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00003C00 */
#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk                  /*!< USB turnaround time */
#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00000400 */
#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00000800 */
#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00001000 */
#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00002000 */
#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos)     /*!< 0x00008000 */
#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk               /*!< PHY Low-power clock select */
#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos)    /*!< 0x00020000 */
#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk              /*!< ULPI FS/LS select */
#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos)      /*!< 0x00040000 */
#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk                /*!< ULPI Auto-resume */
#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos)     /*!< 0x00080000 */
#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk               /*!< ULPI Clock SuspendM */
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)  /*!< 0x00100000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk            /*!< ULPI External VBUS Drive */
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)  /*!< 0x00200000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk            /*!< ULPI external VBUS indicator */
#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos)       /*!< 0x00400000 */
#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk                 /*!< TermSel DLine pulsing selection */
#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos)        /*!< 0x00800000 */
#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk                  /*!< Indicator complement */
#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos)        /*!< 0x01000000 */
#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk                  /*!< Indicator pass through */
#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos)     /*!< 0x02000000 */
#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk               /*!< ULPI interface protect disable */
#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos)       /*!< 0x20000000 */
#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk                 /*!< Forced host mode */
#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos)       /*!< 0x40000000 */
#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk                 /*!< Forced peripheral mode */
#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos)      /*!< 0x80000000 */
#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk                /*!< Corrupt Tx packet */

/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos)       /*!< 0x00000001 */
#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk                 /*!< Core soft reset */
#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos)       /*!< 0x00000002 */
#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk                 /*!< HCLK soft reset */
#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos)       /*!< 0x00000004 */
#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk                 /*!< Host frame counter reset */
#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos)     /*!< 0x00000010 */
#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk               /*!< RxFIFO flush */
#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos)     /*!< 0x00000020 */
#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk               /*!< TxFIFO flush */
#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x000007C0 */
#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk                /*!< TxFIFO number */
#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000040 */
#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000080 */
#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000100 */
#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000200 */
#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000400 */
#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos)      /*!< 0x40000000 */
#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk                /*!< DMA request signal */
#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos)      /*!< 0x80000000 */
#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk                /*!< AHB master idle */

/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos)       /*!< 0x00000001 */
#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk                 /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos)        /*!< 0x00000002 */
#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk                  /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos)         /*!< 0x00000008 */
#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk                   /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)   /*!< 0x00000010 */
#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk             /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos)     /*!< 0x00000020 */
#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk               /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos)     /*!< 0x00000040 */
#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk               /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos)      /*!< 0x00000100 */
#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk                /*!< FIFO underrun mask */
#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos)         /*!< 0x00000200 */
#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk                   /*!< BNA interrupt mask */

/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk              /*!< Periodic transmit data FIFO space available */
#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00FF0000 */
#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk               /*!< Periodic transmit request queue space available */
#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00010000 */
#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00020000 */
#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00040000 */
#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00080000 */
#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00100000 */
#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00200000 */
#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00400000 */
#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00800000 */

#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0xFF000000 */
#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk               /*!< Top of the periodic transmit request queue */
#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x01000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x02000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x04000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x08000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x10000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x20000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x40000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x80000000 */

/********************  Bit definition for USB_OTG_HAINT register  ********************/
#define USB_OTG_HAINT_HAINT_Pos                  (0U)
#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos)      /*!< 0x0000FFFF */
#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk                   /*!< Channel interrupts */

/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos)       /*!< 0x00000001 */
#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk                 /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos)        /*!< 0x00000002 */
#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk                  /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos)       /*!< 0x00000008 */
#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk                 /*!< SETUP phase done mask */
#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos)      /*!< 0x00000010 */
#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk                /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos)     /*!< 0x00000040 */
#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk               /*!< Back-to-back SETUP packets received mask */
#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos)        /*!< 0x00000100 */
#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk                  /*!< OUT packet error mask */
#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos)        /*!< 0x00000200 */
#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk                  /*!< BNA interrupt mask */

/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos)              /*!< 0x00000001 */
#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk                        /*!< Current mode of operation */
#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos)              /*!< 0x00000002 */
#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk                        /*!< Mode mismatch interrupt */
#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos)            /*!< 0x00000004 */
#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk                      /*!< OTG interrupt */
#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos)               /*!< 0x00000008 */
#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk                         /*!< Start of frame */
#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos)            /*!< 0x00000010 */
#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk                      /*!< RxFIFO nonempty */
#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos)            /*!< 0x00000020 */
#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk                      /*!< Nonperiodic TxFIFO empty */
#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos)          /*!< 0x00000040 */
#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk                    /*!< Global IN nonperiodic NAK effective */
#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)        /*!< 0x00000080 */
#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk                  /*!< Global OUT NAK effective */
#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos)             /*!< 0x00000400 */
#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk                       /*!< Early suspend */
#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos)           /*!< 0x00000800 */
#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk                     /*!< USB suspend */
#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos)            /*!< 0x00001000 */
#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk                      /*!< USB reset */
#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos)           /*!< 0x00002000 */
#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk                     /*!< Enumeration done */
#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos)           /*!< 0x00004000 */
#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk                     /*!< Isochronous OUT packet dropped interrupt */
#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos)              /*!< 0x00008000 */
#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk                        /*!< End of periodic frame interrupt */
#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos)            /*!< 0x00040000 */
#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk                      /*!< IN endpoint interrupt */
#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos)            /*!< 0x00080000 */
#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk                      /*!< OUT endpoint interrupt */
#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos)          /*!< 0x00100000 */
#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk                    /*!< Incomplete isochronous IN transfer */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk           /*!< Incomplete periodic transfer */
#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos)         /*!< 0x00400000 */
#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk                   /*!< Data fetch suspended */
#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos)           /*!< 0x01000000 */
#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk                     /*!< Host port interrupt */
#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos)             /*!< 0x02000000 */
#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk                       /*!< Host channels interrupt */
#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos)             /*!< 0x04000000 */
#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk                       /*!< Periodic TxFIFO empty */
#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos)            /*!< 0x08000000 */
#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk                      /*!< LPM interrupt */
#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos)           /*!< 0x10000000 */
#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk                     /*!< Connector ID status change */
#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos)           /*!< 0x20000000 */
#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk                     /*!< Disconnect detected interrupt */
#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos)            /*!< 0x40000000 */
#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk                      /*!< Session request/new session detected interrupt */
#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos)            /*!< 0x80000000 */
#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk                      /*!< Resume/remote wakeup detected interrupt */

/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos)           /*!< 0x00000002 */
#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk                     /*!< Mode mismatch interrupt mask */
#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos)          /*!< 0x00000004 */
#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk                    /*!< OTG interrupt mask */
#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos)            /*!< 0x00000008 */
#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk                      /*!< Start of frame mask */
#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos)         /*!< 0x00000010 */
#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk                   /*!< Receive FIFO nonempty mask */
#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos)         /*!< 0x00000020 */
#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk                   /*!< Nonperiodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos)       /*!< 0x00000040 */
#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk                 /*!< Global nonperiodic IN NAK effective mask */
#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos)       /*!< 0x00000080 */
#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk                 /*!< Global OUT NAK effective mask */
#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos)          /*!< 0x00000400 */
#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk                    /*!< Early suspend mask */
#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos)        /*!< 0x00000800 */
#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk                  /*!< USB suspend mask */
#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos)          /*!< 0x00001000 */
#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk                    /*!< USB reset mask */
#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos)        /*!< 0x00002000 */
#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk                  /*!< Enumeration done mask */
#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos)        /*!< 0x00004000 */
#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk                  /*!< Isochronous OUT packet dropped interrupt mask */
#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos)           /*!< 0x00008000 */
#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk                     /*!< End of periodic frame interrupt mask */
#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos)          /*!< 0x00020000 */
#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk                    /*!< Endpoint mismatch interrupt mask */
#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos)          /*!< 0x00040000 */
#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk                    /*!< IN endpoints interrupt mask */
#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos)          /*!< 0x00080000 */
#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk                    /*!< OUT endpoints interrupt mask */
#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos)       /*!< 0x00100000 */
#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk                 /*!< Incomplete isochronous IN transfer mask */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk           /*!< Incomplete periodic transfer mask */
#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos)          /*!< 0x00400000 */
#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk                    /*!< Data fetch suspended mask */
#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos)           /*!< 0x01000000 */
#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk                     /*!< Host port interrupt mask */
#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos)            /*!< 0x02000000 */
#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk                      /*!< Host channels interrupt mask */
#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos)          /*!< 0x04000000 */
#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk                    /*!< Periodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos)         /*!< 0x08000000 */
#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk                   /*!< LPM interrupt Mask */
#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos)        /*!< 0x10000000 */
#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk                  /*!< Connector ID status change mask */
#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos)         /*!< 0x20000000 */
#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk                   /*!< Disconnect detected interrupt mask */
#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos)           /*!< 0x40000000 */
#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk                     /*!< Session request/new session detected interrupt mask */
#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos)            /*!< 0x80000000 */
#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk                      /*!< Resume/remote wakeup detected interrupt mask */

/********************  Bit definition for USB_OTG_DAINT register  ********************/
#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos)         /*!< 0x0000FFFF */
#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk                      /*!< IN endpoint interrupt bits */
#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos)         /*!< 0xFFFF0000 */
#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk                      /*!< OUT endpoint interrupt bits */

/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos)      /*!< 0x0000FFFF */
#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk                   /*!< Channel interrupt mask */

/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos)           /*!< 0x0000000F */
#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk                     /*!< IN EP interrupt mask bits */
#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos)          /*!< 0x00007FF0 */
#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk                      /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos)            /*!< 0x00018000 */
#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk                      /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos)          /*!< 0x001E0000 */
#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk                    /*!< OUT EP interrupt mask bits */

/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos)        /*!< 0x0000FFFF */
#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk                     /*!< IN EP interrupt mask bits */
#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos)        /*!< 0xFFFF0000 */
#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk                     /*!< OUT EP interrupt mask bits */

/********************  Bit definition for OTG register  ********************/
#define USB_OTG_CHNUM_Pos                        (0U)
#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)                  /*!< 0x0000000F */
#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk                            /*!< Channel number */
#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000001 */
#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000002 */
#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000004 */
#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos                         (4U)
#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)                 /*!< 0x00007FF0 */
#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk                             /*!< Byte count */
#define USB_OTG_DPID_Pos                         (15U)
#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)                   /*!< 0x00018000 */
#define USB_OTG_DPID                             USB_OTG_DPID_Msk                             /*!< Data PID */
#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)                   /*!< 0x00008000 */
#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)                   /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos                       (17U)
#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)                 /*!< 0x001E0000 */
#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk                           /*!< Packet status */
#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos                        (0U)
#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)                  /*!< 0x0000000F */
#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk                            /*!< Endpoint number */
#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000001 */
#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000002 */
#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000004 */
#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos                       (21U)
#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)                 /*!< 0x01E00000 */
#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk                           /*!< Frame number */
#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)                 /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)                 /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)                 /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)                 /*!< 0x01000000 */

/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos)        /*!< 0x0000FFFF */
#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk                     /*!< RxFIFO depth */

/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos)     /*!< 0x0000FFFF */
#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk                  /*!< Device VBUS discharge time */

/********************  Bit definition for OTG register  ********************/
#define USB_OTG_NPTXFSA_Pos                      (0U)
#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos)             /*!< 0x0000FFFF */
#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk                          /*!< Nonperiodic transmit RAM start address */
#define USB_OTG_NPTXFD_Pos                       (16U)
#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos)              /*!< 0xFFFF0000 */
#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk                           /*!< Nonperiodic TxFIFO depth */
#define USB_OTG_TX0FSA_Pos                       (0U)
#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos)              /*!< 0x0000FFFF */
#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk                           /*!< Endpoint 0 transmit RAM start address */
#define USB_OTG_TX0FD_Pos                        (16U)
#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos)               /*!< 0xFFFF0000 */
#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk                            /*!< Endpoint 0 TxFIFO depth */

/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos)    /*!< 0x00000FFF */
#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk                /*!< Device VBUS pulsing time */

/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)   /*!< 0x0000FFFF */
#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk                /*!< Nonperiodic TxFIFO space available */

#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00FF0000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk                /*!< Nonperiodic transmit request queue space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00010000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00020000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00040000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00080000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00100000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00200000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00400000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00800000 */

#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x7F000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk                /*!< Top of the nonperiodic transmit request queue */
#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x01000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x02000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x04000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x08000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x10000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x20000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x40000000 */

/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos)    /*!< 0x00000001 */
#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk              /*!< Nonisochronous IN endpoints threshold enable */
#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos)       /*!< 0x00000002 */
#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk                 /*!< ISO IN endpoint threshold enable */
#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x000007FC */
#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk                 /*!< Transmit threshold length */
#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000004 */
#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000008 */
#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000010 */
#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000020 */
#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000040 */
#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000080 */
#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000100 */
#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000200 */
#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000400 */

#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos)        /*!< 0x00010000 */
#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk                  /*!< Receive threshold enable */
#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x03FE0000 */
#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk                 /*!< Receive threshold length */
#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00020000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00040000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00080000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00100000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00200000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00400000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00800000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x01000000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x02000000 */
#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos)          /*!< 0x08000000 */
#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk                    /*!< Arbiter parking enable */

/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk              /*!< IN EP Tx FIFO empty interrupt mask bits */

/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos)       /*!< 0x00000002 */
#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk                 /*!< IN endpoint 1interrupt bit */
#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos)       /*!< 0x00020000 */
#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk                 /*!< OUT endpoint 1 interrupt bit */

/********************  Bit definition for USB_OTG_FS_GCCFG register  ********************/
#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos)            /*!< 0x00000001 */
#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk                      /*!< Data contact detection (DCD) status */
#define USB_OTG_GCCFG_PDET_Pos                   (1U)
#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos)             /*!< 0x00000002 */
#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk                       /*!< Primary detection (PD) status */
#define USB_OTG_GCCFG_SDET_Pos                   (2U)
#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos)             /*!< 0x00000004 */
#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk                       /*!< Secondary detection (SD) status */
#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos)           /*!< 0x00000008 */
#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk                     /*!< DM pull-up detection status */
#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos)           /*!< 0x00010000 */
#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk                     /*!< Power down */
#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos)            /*!< 0x00020000 */
#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk                      /*!< Battery charging detector (BCD) enable */
#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos)            /*!< 0x00040000 */
#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk                      /*!< Data contact detection (DCD) mode enable */
#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos)             /*!< 0x00080000 */
#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk                       /*!< Primary detection (PD) mode enable */
#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos)             /*!< 0x00100000 */
#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk                       /*!< Secondary detection (SD) mode enable */

/********************  Bit definition for USB_OTG_HS_GCCFG register  ********************/
#define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
#define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
#define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
#define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
#define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
#define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk               (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)         /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                   /*!< Single-Ended DM2 indicator DM voltage level  */
#define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
#define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
#define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
#define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
#define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
#define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
#define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
#define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
#define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
#define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
#define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
#define USB_OTG_GCCFG_DCDETEN_Pos                (19U)
#define USB_OTG_GCCFG_DCDETEN_Msk                (0x1U << USB_OTG_GCCFG_DCDETEN_Pos)          /*!< 0x00080000 */
#define USB_OTG_GCCFG_DCDETEN                    USB_OTG_GCCFG_DCDETEN_Msk                    /*!< Data contact detection (DCD) mode enable */
#define USB_OTG_GCCFG_PDETEN_Pos                 (20U)
#define USB_OTG_GCCFG_PDETEN_Msk                 (0x1U << USB_OTG_GCCFG_PDETEN_Pos)           /*!< 0x00080000 */
#define USB_OTG_GCCFG_PDETEN                     USB_OTG_GCCFG_PDETEN_Msk                     /*!< Primary detection (PD) mode enable */
#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos)            /*!< 0x00200000 */
#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk                      /*!< Vbus detection enable */
#define USB_OTG_GCCFG_SDETEN_Pos                 (22U)
#define USB_OTG_GCCFG_SDETEN_Msk                 (0x1U << USB_OTG_GCCFG_SDETEN_Pos)           /*!< 0x00400000 */
#define USB_OTG_GCCFG_SDETEN                     USB_OTG_GCCFG_SDETEN_Msk                     /*!< Secondary detection (PD) mode enable */
#define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
#define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
#define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 femtoPHY input */
#define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
#define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
#define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 femtoPHY input override */
#define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
#define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
#define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */

/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)
#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos)     /*!< 0x00000040 */
#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk               /*!< Power down */

/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)   /*!< 0x00000002 */
#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk             /*!< IN Endpoint 1 interrupt mask bit */
#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)   /*!< 0x00020000 */
#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk             /*!< OUT Endpoint 1 interrupt mask bit */

/********************  Bit definition for USB_OTG_CID register  ********************/
#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos)  /*!< 0xFFFFFFFF */
#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk                   /*!< Product ID field */

/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)
#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos)        /*!< 0x00004000 */
#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk                  /* LPM mode specified for Mode of Operation */

/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos)         /*!< 0x10000000 */
#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk                   /* Enable best effort service latency */
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)     /*!< 0x0E000000 */
#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk               /* LPM retry count status */
#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos)         /*!< 0x01000000 */
#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk                   /* Send LPM transaction */
#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos)        /*!< 0x00E00000 */
#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk                  /* LPM retry count */
#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos)       /*!< 0x001E0000 */
#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk                 /* LPMCHIDX: */
#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)
#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos)     /*!< 0x00010000 */
#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk               /* Sleep State Resume OK */
#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos)         /*!< 0x00008000 */
#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk                   /* Port sleep status */
#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos)         /*!< 0x00006000 */
#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk                   /* LPM response */
#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos)         /*!< 0x00001000 */
#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk                   /* L1 deep sleep enable */
#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos)       /*!< 0x00000F00 */
#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk                 /* BESL threshold */
#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos)         /*!< 0x00000080 */
#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk                   /* L1 shallow sleep enable */
#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos)        /*!< 0x00000040 */
#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk                  /* bRemoteWake value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos)           /*!< 0x0000003C */
#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk                     /* BESL value received with last ACKed LPM Token  */
#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos)         /*!< 0x00000002 */
#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk                   /* LPM Token acknowledge enable*/
#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos)          /*!< 0x00000001 */
#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk                    /* LPM support enable  */

/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)     /*!< 0x00000001 */
#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk               /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos)      /*!< 0x00000002 */
#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk                /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos)       /*!< 0x00000008 */
#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk                 /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk           /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)   /*!< 0x00000020 */
#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk             /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)   /*!< 0x00000040 */
#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk             /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)    /*!< 0x00000100 */
#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk              /*!< FIFO underrun mask */
#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos)       /*!< 0x00000200 */
#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk                 /*!< BNA interrupt mask */
#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos)      /*!< 0x00002000 */
#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk                /*!< NAK interrupt mask */

/********************  Bit definition for USB_OTG_HPRT register  ********************/
#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos)             /*!< 0x00000001 */
#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk                       /*!< Port connect status */
#define USB_OTG_HPRT_PCDET_Pos                   (1U)
#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos)             /*!< 0x00000002 */
#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk                       /*!< Port connect detected */
#define USB_OTG_HPRT_PENA_Pos                    (2U)
#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos)              /*!< 0x00000004 */
#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk                        /*!< Port enable */
#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos)           /*!< 0x00000008 */
#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk                     /*!< Port enable/disable change */
#define USB_OTG_HPRT_POCA_Pos                    (4U)
#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos)              /*!< 0x00000010 */
#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk                        /*!< Port overcurrent active */
#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos)           /*!< 0x00000020 */
#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk                     /*!< Port overcurrent change */
#define USB_OTG_HPRT_PRES_Pos                    (6U)
#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos)              /*!< 0x00000040 */
#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk                        /*!< Port resume */
#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos)             /*!< 0x00000080 */
#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk                       /*!< Port suspend */
#define USB_OTG_HPRT_PRST_Pos                    (8U)
#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos)              /*!< 0x00000100 */
#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk                        /*!< Port reset */

#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos)             /*!< 0x00000C00 */
#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk                       /*!< Port line status */
#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos)             /*!< 0x00000400 */
#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos)             /*!< 0x00000800 */
#define USB_OTG_HPRT_PPWR_Pos                    (12U)
#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos)              /*!< 0x00001000 */
#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk                        /*!< Port power */

#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x0001E000 */
#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk                       /*!< Port test control */
#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00002000 */
#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00004000 */
#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00008000 */
#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00010000 */

#define USB_OTG_HPRT_PSPD_Pos                    (17U)
#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos)              /*!< 0x00060000 */
#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk                        /*!< Port speed */
#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos)              /*!< 0x00020000 */
#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos)              /*!< 0x00040000 */

/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)     /*!< 0x00000001 */
#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk               /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos)      /*!< 0x00000002 */
#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk                /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos)       /*!< 0x00000008 */
#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk                 /*!< Timeout condition mask */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk           /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)   /*!< 0x00000020 */
#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk             /*!< IN token received with EP mismatch mask */
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)   /*!< 0x00000040 */
#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk             /*!< IN endpoint NAK effective mask */
#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)    /*!< 0x00000100 */
#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk              /*!< OUT packet error mask */
#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos)       /*!< 0x00000200 */
#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk                 /*!< BNA interrupt mask */
#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos)     /*!< 0x00001000 */
#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk               /*!< Bubble error interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos)      /*!< 0x00002000 */
#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk                /*!< NAK interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos)     /*!< 0x00004000 */
#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk               /*!< NYET interrupt mask */

/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos)      /*!< 0x0000FFFF */
#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk                   /*!< Host periodic TxFIFO start address */
#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos)      /*!< 0xFFFF0000 */
#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk                   /*!< Host periodic TxFIFO depth */

/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos)        /*!< 0x000007FF */
#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk                    /*!< Maximum packet size */
#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos)         /*!< 0x00008000 */
#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk                   /*!< USB active endpoint */
#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos)     /*!< 0x00010000 */
#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk               /*!< Even/odd frame */
#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos)         /*!< 0x00020000 */
#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk                   /*!< NAK status */

#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos)          /*!< 0x000C0000 */
#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk                    /*!< Endpoint type */
#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos)          /*!< 0x00040000 */
#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos)          /*!< 0x00080000 */
#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos)          /*!< 0x00200000 */
#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk                    /*!< STALL handshake */

#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x03C00000 */
#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk                   /*!< TxFIFO number */
#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x00400000 */
#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x00800000 */
#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x01000000 */
#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x02000000 */
#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos)           /*!< 0x04000000 */
#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk                     /*!< Clear NAK */
#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos)           /*!< 0x08000000 */
#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk                     /*!< Set NAK */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk           /*!< Set DATA0 PID */
#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos)        /*!< 0x20000000 */
#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk                  /*!< Set odd frame */
#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos)          /*!< 0x40000000 */
#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk                    /*!< Endpoint disable */
#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos)          /*!< 0x80000000 */
#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk                    /*!< Endpoint enable */

/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos)         /*!< 0x000007FF */
#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk                     /*!< Maximum packet size */

#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00007800 */
#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk                     /*!< Endpoint number */
#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00000800 */
#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00001000 */
#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00002000 */
#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00004000 */
#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos)           /*!< 0x00008000 */
#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk                     /*!< Endpoint direction */
#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos)           /*!< 0x00020000 */
#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk                     /*!< Low-speed device */

#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos)           /*!< 0x000C0000 */
#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk                     /*!< Endpoint type */
#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos)           /*!< 0x00040000 */
#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos)           /*!< 0x00080000 */

#define USB_OTG_HCCHAR_MC_Pos                    (20U)
#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos)              /*!< 0x00300000 */
#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk                        /*!< Multi Count (MC) / Error Count (EC) */
#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos)              /*!< 0x00100000 */
#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos)              /*!< 0x00200000 */

#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x1FC00000 */
#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk                       /*!< Device address */
#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x00400000 */
#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x00800000 */
#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x01000000 */
#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x02000000 */
#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x04000000 */
#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x08000000 */
#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x10000000 */
#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos)          /*!< 0x20000000 */
#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk                    /*!< Odd frame */
#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos)           /*!< 0x40000000 */
#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk                     /*!< Channel disable */
#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos)           /*!< 0x80000000 */
#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk                     /*!< Channel enable */

/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x0000007F */
#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk                   /*!< Port address */
#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000001 */
#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000002 */
#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000004 */
#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000008 */
#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000010 */
#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000020 */
#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000040 */

#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00003F80 */
#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk                   /*!< Hub address */
#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000080 */
#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000100 */
#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000200 */
#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000400 */
#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000800 */
#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00001000 */
#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00002000 */

#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos)         /*!< 0x0000C000 */
#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk                   /*!< XACTPOS */
#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos)         /*!< 0x00004000 */
#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos)         /*!< 0x00008000 */
#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos)       /*!< 0x00010000 */
#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk                 /*!< Do complete split */
#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos)         /*!< 0x80000000 */
#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk                   /*!< Split enable */

/********************  Bit definition for USB_OTG_HCINT register  ********************/
#define USB_OTG_HCINT_XFRC_Pos                   (0U)
#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos)             /*!< 0x00000001 */
#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk                       /*!< Transfer completed */
#define USB_OTG_HCINT_CHH_Pos                    (1U)
#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos)              /*!< 0x00000002 */
#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk                        /*!< Channel halted */
#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos)           /*!< 0x00000004 */
#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk                     /*!< AHB error */
#define USB_OTG_HCINT_STALL_Pos                  (3U)
#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos)            /*!< 0x00000008 */
#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk                      /*!< STALL response received interrupt */
#define USB_OTG_HCINT_NAK_Pos                    (4U)
#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos)              /*!< 0x00000010 */
#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk                        /*!< NAK response received interrupt */
#define USB_OTG_HCINT_ACK_Pos                    (5U)
#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos)              /*!< 0x00000020 */
#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk                        /*!< ACK response received/transmitted interrupt */
#define USB_OTG_HCINT_NYET_Pos                   (6U)
#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos)             /*!< 0x00000040 */
#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk                       /*!< Response received interrupt */
#define USB_OTG_HCINT_TXERR_Pos                  (7U)
#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos)            /*!< 0x00000080 */
#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk                      /*!< Transaction error */
#define USB_OTG_HCINT_BBERR_Pos                  (8U)
#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos)            /*!< 0x00000100 */
#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk                      /*!< Babble error */
#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos)            /*!< 0x00000200 */
#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk                      /*!< Frame overrun */
#define USB_OTG_HCINT_DTERR_Pos                  (10U)
#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos)            /*!< 0x00000400 */
#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk                      /*!< Data toggle error */

/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos)           /*!< 0x00000001 */
#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk                     /*!< Transfer completed interrupt */
#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos)         /*!< 0x00000002 */
#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk                   /*!< Endpoint disabled interrupt */
#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos)            /*!< 0x00000008 */
#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk                      /*!< Timeout condition */
#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos)         /*!< 0x00000010 */
#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk                   /*!< IN token received when TxFIFO is empty */
#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos)         /*!< 0x00000040 */
#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk                   /*!< IN endpoint NAK effective */
#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos)           /*!< 0x00000080 */
#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk                     /*!< Transmit FIFO empty */
#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)     /*!< 0x00000100 */
#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk               /*!< Transmit Fifo Underrun */
#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos)            /*!< 0x00000200 */
#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk                      /*!< Buffer not available interrupt */
#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos)      /*!< 0x00000800 */
#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk                /*!< Packet dropped status */
#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos)           /*!< 0x00001000 */
#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk                     /*!< Babble error interrupt */
#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos)            /*!< 0x00002000 */
#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk                      /*!< NAK interrupt */

/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos)         /*!< 0x00000001 */
#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk                   /*!< Transfer completed mask */
#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos)          /*!< 0x00000002 */
#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk                    /*!< Channel halted mask */
#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos)        /*!< 0x00000004 */
#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk                  /*!< AHB error */
#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos)        /*!< 0x00000008 */
#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk                  /*!< STALL response received interrupt mask */
#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos)          /*!< 0x00000010 */
#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk                    /*!< NAK response received interrupt mask */
#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos)          /*!< 0x00000020 */
#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk                    /*!< ACK response received/transmitted interrupt mask */
#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos)          /*!< 0x00000040 */
#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk                    /*!< response received interrupt mask */
#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos)        /*!< 0x00000080 */
#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk                  /*!< Transaction error mask */
#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos)        /*!< 0x00000100 */
#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk                  /*!< Babble error mask */
#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos)        /*!< 0x00000200 */
#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk                  /*!< Frame overrun mask */
#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos)        /*!< 0x00000400 */
#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk                  /*!< Data toggle error mask */

/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)    /*!< 0x0007FFFF */
#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk                  /*!< Transfer size */
#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos)      /*!< 0x1FF80000 */
#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk                  /*!< Packet count */
#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos)        /*!< 0x60000000 */
#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk                  /*!< Packet count */

/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos)      /*!< 0x0007FFFF */
#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk                    /*!< Transfer size */
#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos)        /*!< 0x1FF80000 */
#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk                    /*!< Packet count */
#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos)          /*!< 0x80000000 */
#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk                    /*!< Do PING */
#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos)            /*!< 0x60000000 */
#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk                      /*!< Data PID */
#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos)            /*!< 0x20000000 */
#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos)            /*!< 0x40000000 */

/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk                  /*!< DMA address */

/********************  Bit definition for USB_OTG_HCDMA register  ********************/
#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos)   /*!< 0xFFFFFFFF */
#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk                    /*!< DMA address */

/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos)   /*!< 0x0000FFFF */
#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk                /*!< IN endpoint TxFIFO space avail */

/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos)    /*!< 0x0000FFFF */
#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk                 /*!< IN endpoint FIFOx transmit RAM start address */
#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos)    /*!< 0xFFFF0000 */
#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk                 /*!< IN endpoint TxFIFO depth */

/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos)        /*!< 0x000007FF */
#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk                    /*!< Maximum packet size */
#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos)         /*!< 0x00008000 */
#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk                   /*!< USB active endpoint */
#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos)         /*!< 0x00020000 */
#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk                   /*!< NAK status */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk           /*!< Set DATA0 PID */
#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos)        /*!< 0x20000000 */
#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk                  /*!< Set odd frame */
#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos)          /*!< 0x000C0000 */
#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk                    /*!< Endpoint type */
#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos)          /*!< 0x00040000 */
#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos)          /*!< 0x00080000 */
#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos)           /*!< 0x00100000 */
#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk                     /*!< Snoop mode */
#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos)          /*!< 0x00200000 */
#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk                    /*!< STALL handshake */
#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos)           /*!< 0x04000000 */
#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk                     /*!< Clear NAK */
#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos)           /*!< 0x08000000 */
#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk                     /*!< Set NAK */
#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos)          /*!< 0x40000000 */
#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk                    /*!< Endpoint disable */
#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos)          /*!< 0x80000000 */
#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk                    /*!< Endpoint enable */

/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos)           /*!< 0x00000001 */
#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk                     /*!< Transfer completed interrupt */
#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos)         /*!< 0x00000002 */
#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk                   /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos)           /*!< 0x00000008 */
#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk                     /*!< SETUP phase done */
#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos)        /*!< 0x00000010 */
#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk                  /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos)        /*!< 0x00000040 */
#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk                  /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos)           /*!< 0x00004000 */
#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk                     /*!< NYET interrupt */

/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)    /*!< 0x0007FFFF */
#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk                  /*!< Transfer size */
#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos)      /*!< 0x1FF80000 */
#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk                  /*!< Packet count */

#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos)       /*!< 0x60000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk                 /*!< SETUP packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos)       /*!< 0x20000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos)       /*!< 0x40000000 */

/********************  Bit definition for PCGCCTL register  ********************/
#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos)        /*!< 0x00000001 */
#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk                  /*!< SETUP packet count */
#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos)        /*!< 0x00000002 */
#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk                  /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos)        /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk                  /*!<Bit 1 */


/******************************************************************************/
/*                                                                            */
/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for USART_CR1 register  *******************/
#define USART_CR1_UE_Pos                (0U)
#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
#define USART_CR1_UE                    USART_CR1_UE_Msk                        /*!< USART Enable */
#define USART_CR1_UESM_Pos              (1U)
#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
#define USART_CR1_UESM                  USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos                (2U)
#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
#define USART_CR1_RE                    USART_CR1_RE_Msk                        /*!< Receiver Enable */
#define USART_CR1_TE_Pos                (3U)
#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
#define USART_CR1_TE                    USART_CR1_TE_Msk                        /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos            (4U)
#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos            (5U)
#define USART_CR1_RXNEIE_Msk            (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
#define USART_CR1_RXNEIE                USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos    USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk    USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos              (6U)
#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos             (7U)
#define USART_CR1_TXEIE_Msk             (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
#define USART_CR1_TXEIE                 USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos              (8U)
#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos                (9U)
#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
#define USART_CR1_PS                    USART_CR1_PS_Msk                        /*!< Parity Selection */
#define USART_CR1_PCE_Pos               (10U)
#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
#define USART_CR1_PCE                   USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos              (11U)
#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos                 (12U)
#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
#define USART_CR1_M0_Pos                (12U)
#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
#define USART_CR1_M0                    USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos               (13U)
#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
#define USART_CR1_MME                   USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos              (14U)
#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos             (15U)
#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos              (16U)
#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos              (21U)
#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos             (26U)
#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
#define USART_CR1_EOBIE_Pos             (27U)
#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
#define USART_CR1_M1_Pos                (28U)
#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
#define USART_CR1_M1                    USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos            (29U)
#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos            (30U)
#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
#define USART_CR1_RXFFIE_Pos            (31U)
#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */

/******************  Bit definition for USART_CR2 register  *******************/
#define USART_CR2_SLVEN_Pos             (0U)
#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos           (3U)
#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos             (4U)
#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos              (5U)
#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos             (6U)
#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos              (8U)
#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos              (9U)
#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                      /*!< Clock Phase */
#define USART_CR2_CPOL_Pos              (10U)
#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos             (11U)
#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
#define USART_CR2_STOP_Pos              (12U)
#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
#define USART_CR2_STOP                  USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos             (14U)
#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos              (15U)
#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos             (16U)
#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos             (17U)
#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos           (18U)
#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos          (19U)
#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos             (20U)
#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos           (21U)
#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos             (23U)
#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos               (24U)
#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
#define USART_CR2_ADD                   USART_CR2_ADD_Msk                       /*!< Address of the USART node */

/******************  Bit definition for USART_CR3 register  *******************/
#define USART_CR3_EIE_Pos               (0U)
#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
#define USART_CR3_EIE                   USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos              (1U)
#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
#define USART_CR3_IREN                  USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos              (2U)
#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos             (3U)
#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos              (4U)
#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
#define USART_CR3_NACK                  USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos              (5U)
#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos              (6U)
#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos              (7U)
#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos              (8U)
#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                      /*!< RTS Enable */
#define USART_CR3_CTSE_Pos              (9U)
#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk
#define USART_CR3_CTSIE_Pos             (10U)
#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos            (11U)
#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos            (12U)
#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos              (13U)
#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos               (14U)
#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
#define USART_CR3_DEM                   USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos               (15U)
#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
#define USART_CR3_DEP                   USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos           (17U)
#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
#define USART_CR3_WUS_Pos               (20U)
#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
#define USART_CR3_WUS                   USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos             (22U)
#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos            (23U)
#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
#define USART_CR3_TCBGTIE_Pos           (24U)
#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos           (25U)
#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos            (28U)
#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
#define USART_CR3_TXFTCFG_Pos           (29U)
#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

/******************  Bit definition for USART_BRR register  *******************/
#define USART_BRR_LPUART                ((uint32_t)0x000FFFFF)                  /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR                   ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */

/******************  Bit definition for USART_GTPR register  ******************/
#define USART_GTPR_PSC_Pos              (0U)
#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos               (8U)
#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
#define USART_GTPR_GT                   USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */

/*******************  Bit definition for USART_RTOR register  *****************/
#define USART_RTOR_RTO_Pos              (0U)
#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
#define USART_RTOR_BLEN_Pos             (24U)
#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                     /*!< Block Length */

/*******************  Bit definition for USART_RQR register  ******************/
#define USART_RQR_ABRRQ_Pos             (0U)
#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos             (1U)
#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos              (2U)
#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos             (3U)
#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos             (4U)
#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */

/*******************  Bit definition for USART_ISR register  ******************/
#define USART_ISR_PE_Pos                (0U)
#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
#define USART_ISR_PE                    USART_ISR_PE_Msk                        /*!< Parity Error */
#define USART_ISR_FE_Pos                (1U)
#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
#define USART_ISR_FE                    USART_ISR_FE_Msk                        /*!< Framing Error */
#define USART_ISR_NE_Pos                (2U)
#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
#define USART_ISR_NE                    USART_ISR_NE_Msk                        /*!< START bit Noise Error detection Flag */
#define USART_ISR_ORE_Pos               (3U)
#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
#define USART_ISR_ORE                   USART_ISR_ORE_Msk                       /*!< OverRun Error */
#define USART_ISR_IDLE_Pos              (4U)
#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos              (5U)
#define USART_ISR_RXNE_Msk              (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
#define USART_ISR_RXNE                  USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos        USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk        USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos                (6U)
#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
#define USART_ISR_TC                    USART_ISR_TC_Msk                        /*!< Transmission Complete */
#define USART_ISR_TXE_Pos               (7U)
#define USART_ISR_TXE_Msk               (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
#define USART_ISR_TXE                   USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos         USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk         USART_ISR_TXE_Msk                       /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos              (8U)
#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos             (9U)
#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
#define USART_ISR_CTS_Pos               (10U)
#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
#define USART_ISR_CTS                   USART_ISR_CTS_Msk                       /*!< CTS Flag */
#define USART_ISR_RTOF_Pos              (11U)
#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
#define USART_ISR_EOBF_Pos              (12U)
#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos               (13U)
#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
#define USART_ISR_UDR                   USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
#define USART_ISR_ABRE_Pos              (14U)
#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos              (15U)
#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos              (16U)
#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                      /*!< Busy Flag */
#define USART_ISR_CMF_Pos               (17U)
#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
#define USART_ISR_CMF                   USART_ISR_CMF_Msk                       /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos              (18U)
#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
#define USART_ISR_RWU_Pos               (19U)
#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
#define USART_ISR_RWU                   USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos               (20U)
#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
#define USART_ISR_WUF                   USART_ISR_WUF_Msk                       /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos             (21U)
#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos             (22U)
#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
#define USART_ISR_REACK                 USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos              (23U)
#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
#define USART_ISR_RXFF_Pos              (24U)
#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
#define USART_ISR_TCBGT_Pos             (25U)
#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos              (26U)
#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
#define USART_ISR_TXFT_Pos              (27U)
#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */

/*******************  Bit definition for USART_ICR register  ******************/
#define USART_ICR_PECF_Pos              (0U)
#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
#define USART_ICR_PECF                  USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos              (1U)
#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
#define USART_ICR_FECF                  USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos              (2U)
#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
#define USART_ICR_NECF                  USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
#define USART_ICR_ORECF_Pos             (3U)
#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos            (4U)
#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos            (5U)
#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
#define USART_ICR_TCCF_Pos              (6U)
#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos           (7U)
#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos             (8U)
#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos             (9U)
#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos             (11U)
#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos             (12U)
#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos             (13U)
#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos              (17U)
#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos              (20U)
#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */

/*******************  Bit definition for USART_RDR register  ******************/
#define USART_RDR_RDR_Pos               (0U)
#define USART_RDR_RDR_Msk               (0x01FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
#define USART_RDR_RDR                   USART_RDR_RDR_Msk                       /*!< RDR[8:0] bits (Receive Data value) */

/*******************  Bit definition for USART_TDR register  ******************/
#define USART_TDR_TDR_Pos               (0U)
#define USART_TDR_TDR_Msk               (0x01FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
#define USART_TDR_TDR                   USART_TDR_TDR_Msk                       /*!< TDR[8:0] bits (Transmit Data value) */

/*******************  Bit definition for USART_PRESC register  ******************/
#define USART_PRESC_PRESCALER_Pos       (0U)
#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */


/******************************************************************************/
/*                                                                            */
/*                            Window WATCHDOG                                 */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for WWDG_CR register  ********************/
#define WWDG_CR_T_Pos                  (0U)
#define WWDG_CR_T_Msk                  (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
#define WWDG_CR_T                      WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0                    (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
#define WWDG_CR_T_1                    (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
#define WWDG_CR_T_2                    (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
#define WWDG_CR_T_3                    (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
#define WWDG_CR_T_4                    (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
#define WWDG_CR_T_5                    (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
#define WWDG_CR_T_6                    (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos               (7U)
#define WWDG_CR_WDGA_Msk               (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
#define WWDG_CR_WDGA                   WWDG_CR_WDGA_Msk                        /*!<Activation bit */

/*******************  Bit definition for WWDG_CFR register  *******************/
#define WWDG_CFR_W_Pos                 (0U)
#define WWDG_CFR_W_Msk                 (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
#define WWDG_CFR_W                     WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0                   (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
#define WWDG_CFR_W_1                   (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
#define WWDG_CFR_W_2                   (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
#define WWDG_CFR_W_3                   (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
#define WWDG_CFR_W_4                   (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
#define WWDG_CFR_W_5                   (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
#define WWDG_CFR_W_6                   (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos             (11U)
#define WWDG_CFR_WDGTB_Msk             (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
#define WWDG_CFR_WDGTB                 WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0               (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1               (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2               (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos               (9U)
#define WWDG_CFR_EWI_Msk               (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
#define WWDG_CFR_EWI                   WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */

/*******************  Bit definition for WWDG_SR register  ********************/
#define WWDG_SR_EWIF_Pos               (0U)
#define WWDG_SR_EWIF_Msk               (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
#define WWDG_SR_EWIF                   WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */

/** @} */ /* End of group STM32H7RSxx_Peripheral_Registers_Bits_Definition */

/** @} */ /* End of group STM32H7RSxx_Peripheral_Exported_constants */

/** @addtogroup STM32H7RSxx_Peripheral_Exported_macros
  * @{
  */

/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
                                       ((INSTANCE) == ADC2))

#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

/******************************* AXIM ASIB Instances ***************************/
#define IS_AXIM_ASIB_ALL_INSTANCE(INSTANCE)      (((INSTANCE) == AXIM_ASIB_1)  || \
                                                  ((INSTANCE) == AXIM_ASIB_2)  || \
                                                  ((INSTANCE) == AXIM_ASIB_3)  || \
                                                  ((INSTANCE) == AXIM_ASIB_4)  || \
                                                  ((INSTANCE) == AXIM_ASIB_5)  || \
                                                  ((INSTANCE) == AXIM_ASIB_6)  || \
                                                  ((INSTANCE) == AXIM_ASIB_7)  || \
                                                  ((INSTANCE) == AXIM_ASIB_8)  || \
                                                  ((INSTANCE) == AXIM_ASIB_9)  || \
                                                  ((INSTANCE) == AXIM_ASIB_10) || \
                                                  ((INSTANCE) == AXIM_ASIB_11))

/******************************* AXIM AMIB Instances ***************************/
#define IS_AXIM_AMIB_ALL_INSTANCE(INSTANCE)      (((INSTANCE) == AXIM_AMIB_1)  || \
                                                  ((INSTANCE) == AXIM_AMIB_2)  || \
                                                  ((INSTANCE) == AXIM_AMIB_3)  || \
                                                  ((INSTANCE) == AXIM_AMIB_4)  || \
                                                  ((INSTANCE) == AXIM_AMIB_5)  || \
                                                  ((INSTANCE) == AXIM_AMIB_6)  || \
                                                  ((INSTANCE) == AXIM_AMIB_7)  || \
                                                  ((INSTANCE) == AXIM_AMIB_8)  || \
                                                  ((INSTANCE) == AXIM_AMIB_9)  || \
                                                  ((INSTANCE) == AXIM_AMIB_10))

/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)

/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

/******************************* DCMIPP Instances *****************************/
#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP)

/******************************* DLYB Instances *******************************/
#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1)   || \
                                        ((INSTANCE) == DLYB_SDMMC2))

/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0) || \
                                       ((INSTANCE) == GPDMA1_Channel1) || \
                                       ((INSTANCE) == GPDMA1_Channel2) || \
                                       ((INSTANCE) == GPDMA1_Channel3) || \
                                       ((INSTANCE) == GPDMA1_Channel4) || \
                                       ((INSTANCE) == GPDMA1_Channel5) || \
                                       ((INSTANCE) == GPDMA1_Channel6) || \
                                       ((INSTANCE) == GPDMA1_Channel7) || \
                                       ((INSTANCE) == GPDMA1_Channel8) || \
                                       ((INSTANCE) == GPDMA1_Channel9) || \
                                       ((INSTANCE) == GPDMA1_Channel10) || \
                                       ((INSTANCE) == GPDMA1_Channel11) || \
                                       ((INSTANCE) == GPDMA1_Channel12) || \
                                       ((INSTANCE) == GPDMA1_Channel13) || \
                                       ((INSTANCE) == GPDMA1_Channel14) || \
                                       ((INSTANCE) == GPDMA1_Channel15) || \
                                       ((INSTANCE) == HPDMA1_Channel0) || \
                                       ((INSTANCE) == HPDMA1_Channel1) || \
                                       ((INSTANCE) == HPDMA1_Channel2) || \
                                       ((INSTANCE) == HPDMA1_Channel3) || \
                                       ((INSTANCE) == HPDMA1_Channel4) || \
                                       ((INSTANCE) == HPDMA1_Channel5) || \
                                       ((INSTANCE) == HPDMA1_Channel6) || \
                                       ((INSTANCE) == HPDMA1_Channel7) || \
                                       ((INSTANCE) == HPDMA1_Channel8) || \
                                       ((INSTANCE) == HPDMA1_Channel9) || \
                                       ((INSTANCE) == HPDMA1_Channel10) || \
                                       ((INSTANCE) == HPDMA1_Channel11) || \
                                       ((INSTANCE) == HPDMA1_Channel12) || \
                                       ((INSTANCE) == HPDMA1_Channel13) || \
                                       ((INSTANCE) == HPDMA1_Channel14) || \
                                       ((INSTANCE) == HPDMA1_Channel15))

#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0) || \
                                      ((INSTANCE) == GPDMA1_Channel1) || \
                                      ((INSTANCE) == GPDMA1_Channel2) || \
                                      ((INSTANCE) == GPDMA1_Channel3) || \
                                      ((INSTANCE) == GPDMA1_Channel4) || \
                                      ((INSTANCE) == GPDMA1_Channel5) || \
                                      ((INSTANCE) == GPDMA1_Channel6) || \
                                      ((INSTANCE) == GPDMA1_Channel7) || \
                                      ((INSTANCE) == GPDMA1_Channel8) || \
                                      ((INSTANCE) == GPDMA1_Channel9) || \
                                      ((INSTANCE) == GPDMA1_Channel10) || \
                                      ((INSTANCE) == GPDMA1_Channel11) || \
                                      ((INSTANCE) == GPDMA1_Channel12) || \
                                      ((INSTANCE) == GPDMA1_Channel13) || \
                                      ((INSTANCE) == GPDMA1_Channel14) || \
                                      ((INSTANCE) == GPDMA1_Channel15))

#define IS_HPDMA_INSTANCE(INSTANCE)   (((INSTANCE) == HPDMA1_Channel0) || \
                                       ((INSTANCE) == HPDMA1_Channel1) || \
                                       ((INSTANCE) == HPDMA1_Channel2) || \
                                       ((INSTANCE) == HPDMA1_Channel3) || \
                                       ((INSTANCE) == HPDMA1_Channel4) || \
                                       ((INSTANCE) == HPDMA1_Channel5) || \
                                       ((INSTANCE) == HPDMA1_Channel6) || \
                                       ((INSTANCE) == HPDMA1_Channel7) || \
                                       ((INSTANCE) == HPDMA1_Channel8) || \
                                       ((INSTANCE) == HPDMA1_Channel9) || \
                                       ((INSTANCE) == HPDMA1_Channel10) || \
                                       ((INSTANCE) == HPDMA1_Channel11) || \
                                       ((INSTANCE) == HPDMA1_Channel12) || \
                                       ((INSTANCE) == HPDMA1_Channel13) || \
                                       ((INSTANCE) == HPDMA1_Channel14) || \
                                       ((INSTANCE) == HPDMA1_Channel15))

#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12) || \
                                                 ((INSTANCE) == GPDMA1_Channel13) || \
                                                 ((INSTANCE) == GPDMA1_Channel14) || \
                                                 ((INSTANCE) == GPDMA1_Channel15) || \
                                                 ((INSTANCE) == HPDMA1_Channel12) || \
                                                 ((INSTANCE) == HPDMA1_Channel13) || \
                                                 ((INSTANCE) == HPDMA1_Channel14) || \
                                                 ((INSTANCE) == HPDMA1_Channel15))

#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0)   || \
                                         ((INSTANCE) == GPDMA1_Channel15)  || \
                                         ((INSTANCE) == HPDMA1_Channel15))

/******************************* DMA2D Instances *******************************/
#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)

/******************************* DTS Instances *********************************/
#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

/******************************* FDCAN Instances *******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
                                         ((INSTANCE) == FDCAN2))

#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)

/******************************* GFXMMU Instance ******************************/
#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

/******************************* GFXTIM Instance ******************************/
#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM)

/******************************* GPIO Instances ********************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
                                        ((INSTANCE) == GPIOB) || \
                                        ((INSTANCE) == GPIOC) || \
                                        ((INSTANCE) == GPIOD) || \
                                        ((INSTANCE) == GPIOE) || \
                                        ((INSTANCE) == GPIOF) || \
                                        ((INSTANCE) == GPIOG) || \
                                        ((INSTANCE) == GPIOH) || \
                                        ((INSTANCE) == GPIOM) || \
                                        ((INSTANCE) == GPION) || \
                                        ((INSTANCE) == GPIOO) || \
                                        ((INSTANCE) == GPIOP))

/******************************* GPIO AF Instances ****************************/
/* All GPIO Banks support AF */
#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

/**************************** GPIO Lock Instances *****************************/
/* All GPIO Banks support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                       ((INSTANCE) == I2C2) || \
                                       ((INSTANCE) == I2C3))

/******************************** I3C Instances *******************************/
#define IS_I3C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I3C1)

/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

/******************************* JPEG Instances *******************************/
#define IS_JPEG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == JPEG)

/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
                                         ((INSTANCE) == LPTIM2) || \
                                         ((INSTANCE) == LPTIM3) || \
                                         ((INSTANCE) == LPTIM4) || \
                                         ((INSTANCE) == LPTIM5))

/****************** LPTIM Instances : DMA supported instances *****************/
#define IS_LPTIM_DMA_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1) || \
                                          ((INSTANCE) == LPTIM2) || \
                                          ((INSTANCE) == LPTIM3))

/************* LPTIM Instances : at least 1 capture/compare channel ***********/
#define IS_LPTIM_CC1_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1)  || \
                                          ((INSTANCE) == LPTIM2)  || \
                                          ((INSTANCE) == LPTIM3)  || \
                                          ((INSTANCE) == LPTIM4)  || \
                                          ((INSTANCE) == LPTIM5))

/************* LPTIM Instances : at least 2 capture/compare channel ***********/
#define IS_LPTIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1)  || \
                                          ((INSTANCE) == LPTIM2)  || \
                                          ((INSTANCE) == LPTIM3))

/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1) || \
                                                        ((INSTANCE) == LPTIM2) || \
                                                        ((INSTANCE) == LPTIM3))

/****************** LPTIM Instances : supporting Input Capture **************/
#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1) || \
                                                    ((INSTANCE) == LPTIM2) || \
                                                    ((INSTANCE) == LPTIM3))

/******************************* MCE Instances ********************************/
#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1) || \
                                       ((INSTANCE) == MCE2) || \
                                       ((INSTANCE) == MCE3))

/******************************* MDF/ADF Instances ****************************/
#define IS_MDF_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == ADF1_Filter0)

/****************************** MDIOS Instances *******************************/
#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

/******************************* PKA Instances ********************************/
#define IS_PKA_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == PKA)

/******************************* PSSI Instances *******************************/
#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

/**************************** RAMECC Instances ********************************/
#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RAMECC1_Monitor0)   || \
                                                   ((INSTANCE) == RAMECC1_Monitor1)   || \
                                                   ((INSTANCE) == RAMECC1_Monitor2)   || \
                                                   ((INSTANCE) == RAMECC1_Monitor3)   || \
                                                   ((INSTANCE) == RAMECC1_Monitor4)   || \
                                                   ((INSTANCE) == RAMECC2_Monitor1))

/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

/******************************* RTC Instances ********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
                                       ((INSTANCE) == SAI1_Block_B) || \
                                       ((INSTANCE) == SAI2_Block_A) || \
                                       ((INSTANCE) == SAI2_Block_B))

/******************************* SDMMC Instances ******************************/
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1) || \
                                         ((INSTANCE) == SDMMC2))

/******************************** SMBUS Instances *****************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                         ((INSTANCE) == I2C2) || \
                                         ((INSTANCE) == I2C3))

/****************************** SPDIFRX Instances *****************************/
#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
                                       ((INSTANCE) == SPI2) || \
                                       ((INSTANCE) == SPI3) || \
                                       ((INSTANCE) == SPI4) || \
                                       ((INSTANCE) == SPI5) || \
                                       ((INSTANCE) == SPI6))

#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
                                        ((INSTANCE) == SPI2) || \
                                        ((INSTANCE) == SPI3) || \
                                        ((INSTANCE) == SPI6))

#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4) || \
                                           ((INSTANCE) == SPI5))

/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
                                         ((INSTANCE) == SPI2) || \
                                         ((INSTANCE) == SPI3) || \
                                         ((INSTANCE) == SPI6))

/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM3)  || \
                                         ((INSTANCE) == TIM4)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM6)  || \
                                         ((INSTANCE) == TIM7)  || \
                                         ((INSTANCE) == TIM9)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM13) || \
                                         ((INSTANCE) == TIM14) || \
                                         ((INSTANCE) == TIM15) || \
                                         ((INSTANCE) == TIM16) || \
                                         ((INSTANCE) == TIM17))

/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
                                               ((INSTANCE) == TIM3)  || \
                                               ((INSTANCE) == TIM4)  || \
                                               ((INSTANCE) == TIM5))

/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)     ((INSTANCE) == TIM1)

/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))

/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                               ((INSTANCE) == TIM15) || \
                                               ((INSTANCE) == TIM16) || \
                                               ((INSTANCE) == TIM17))

/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM3)  || \
                                         ((INSTANCE) == TIM4)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM9)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM13) || \
                                         ((INSTANCE) == TIM14) || \
                                         ((INSTANCE) == TIM15) || \
                                         ((INSTANCE) == TIM16) || \
                                         ((INSTANCE) == TIM17))

/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM3)  || \
                                         ((INSTANCE) == TIM4)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM9)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM15))

/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM3)  || \
                                         ((INSTANCE) == TIM4)  || \
                                         ((INSTANCE) == TIM5))

/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM3)  || \
                                         ((INSTANCE) == TIM4)  || \
                                         ((INSTANCE) == TIM5))

/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)

/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)

/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM6)  || \
                                            ((INSTANCE) == TIM7)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))

/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))

/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))

/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TIM1) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4) ||          \
      ((CHANNEL) == TIM_CHANNEL_5) ||          \
      ((CHANNEL) == TIM_CHANNEL_6)))           \
     ||                                        \
     (((INSTANCE) == TIM2) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM3) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM4) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM5) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM9) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2)))           \
     ||                                        \
     (((INSTANCE) == TIM12) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2)))           \
     ||                                        \
     (((INSTANCE) == TIM13) && \
     (((CHANNEL) == TIM_CHANNEL_1)))           \
     ||                                        \
     (((INSTANCE) == TIM14) && \
     (((CHANNEL) == TIM_CHANNEL_1)))           \
     ||                                        \
     (((INSTANCE) == TIM15) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2)))           \
     ||                                        \
     (((INSTANCE) == TIM16) && \
     (((CHANNEL) == TIM_CHANNEL_1)))           \
     ||                                        \
     (((INSTANCE) == TIM17) && \
     (((CHANNEL) == TIM_CHANNEL_1))))

/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TIM1) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||           \
      ((CHANNEL) == TIM_CHANNEL_2) ||           \
      ((CHANNEL) == TIM_CHANNEL_3) ||           \
      ((CHANNEL) == TIM_CHANNEL_4)))            \
    ||                                          \
    (((INSTANCE) == TIM15) && \
     ((CHANNEL) == TIM_CHANNEL_1))              \
    ||                                          \
    (((INSTANCE) == TIM16) && \
     ((CHANNEL) == TIM_CHANNEL_1))              \
    ||                                          \
    (((INSTANCE) == TIM17) && \
     ((CHANNEL) == TIM_CHANNEL_1)))

/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                                    ((INSTANCE) == TIM2)  || \
                                                    ((INSTANCE) == TIM3)  || \
                                                    ((INSTANCE) == TIM4)  || \
                                                    ((INSTANCE) == TIM5)  || \
                                                    ((INSTANCE) == TIM9)  || \
                                                    ((INSTANCE) == TIM12) || \
                                                    ((INSTANCE) == TIM13) || \
                                                    ((INSTANCE) == TIM14) || \
                                                    ((INSTANCE) == TIM15) || \
                                                    ((INSTANCE) == TIM16) || \
                                                    ((INSTANCE) == TIM17))

/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                                        ((INSTANCE) == TIM2)  || \
                                                        ((INSTANCE) == TIM3)  || \
                                                        ((INSTANCE) == TIM4)  || \
                                                        ((INSTANCE) == TIM5))

/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                                        ((INSTANCE) == TIM2)  || \
                                                        ((INSTANCE) == TIM3)  || \
                                                        ((INSTANCE) == TIM4)  || \
                                                        ((INSTANCE) == TIM5))

/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                                        ((INSTANCE) == TIM2)  || \
                                                        ((INSTANCE) == TIM3)  || \
                                                        ((INSTANCE) == TIM4)  || \
                                                        ((INSTANCE) == TIM5)  || \
                                                        ((INSTANCE) == TIM9)  || \
                                                        ((INSTANCE) == TIM12) || \
                                                        ((INSTANCE) == TIM15))

/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)  ||  \
                                                        ((INSTANCE) == TIM2)  ||  \
                                                        ((INSTANCE) == TIM3)  ||  \
                                                        ((INSTANCE) == TIM4)  ||  \
                                                        ((INSTANCE) == TIM5)  ||  \
                                                        ((INSTANCE) == TIM9)  ||  \
                                                        ((INSTANCE) == TIM12) ||  \
                                                        ((INSTANCE) == TIM15))

/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                                     ((INSTANCE) == TIM15) || \
                                                     ((INSTANCE) == TIM16) || \
                                                     ((INSTANCE) == TIM17))

/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                                        ((INSTANCE) == TIM2)  || \
                                                        ((INSTANCE) == TIM3)  || \
                                                        ((INSTANCE) == TIM4)  || \
                                                        ((INSTANCE) == TIM5))

/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                                      ((INSTANCE) == TIM2)  || \
                                                      ((INSTANCE) == TIM3)  || \
                                                      ((INSTANCE) == TIM4)  || \
                                                      ((INSTANCE) == TIM5))

/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                                         ((INSTANCE) == TIM2)  || \
                                                         ((INSTANCE) == TIM3)  || \
                                                         ((INSTANCE) == TIM4)  || \
                                                         ((INSTANCE) == TIM5)  || \
                                                         ((INSTANCE) == TIM9)  || \
                                                         ((INSTANCE) == TIM12) || \
                                                         ((INSTANCE) == TIM15))

/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5))

/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5))

/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM6)  || \
                                            ((INSTANCE) == TIM7)  || \
                                            ((INSTANCE) == TIM9)  || \
                                            ((INSTANCE) == TIM12) || \
                                            ((INSTANCE) == TIM15))

/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM9)  || \
                                            ((INSTANCE) == TIM12) || \
                                            ((INSTANCE) == TIM15))

/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                                 ((INSTANCE) == TIM2)  || \
                                                 ((INSTANCE) == TIM3)  || \
                                                 ((INSTANCE) == TIM4)  || \
                                                 ((INSTANCE) == TIM5))

/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5))

/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                                       ((INSTANCE) == TIM15) || \
                                                       ((INSTANCE) == TIM16) || \
                                                       ((INSTANCE) == TIM17))

/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM3)  || \
                                         ((INSTANCE) == TIM9)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM15) || \
                                         ((INSTANCE) == TIM16) || \
                                         ((INSTANCE) == TIM17))

/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)

/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM4)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM9)  || \
                                            ((INSTANCE) == TIM12) || \
                                            ((INSTANCE) == TIM15))

/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)

/******************************* OTG FS HCD Instances *************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS) || ((INSTANCE) == USB_OTG_FS))

/******************************* OTG FS PCD Instances *************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS) || ((INSTANCE) == USB_OTG_FS))

/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                     ((INSTANCE) == USART2) || \
                                     ((INSTANCE) == USART3))

/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                    ((INSTANCE) == USART2) || \
                                    ((INSTANCE) == USART3) || \
                                    ((INSTANCE) == UART4)  || \
                                    ((INSTANCE) == UART5)  || \
                                    ((INSTANCE) == UART7)  || \
                                    ((INSTANCE) == UART8))

/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                         ((INSTANCE) == USART2)  || \
                                         ((INSTANCE) == USART3)  || \
                                         ((INSTANCE) == UART4)   || \
                                         ((INSTANCE) == UART5)   || \
                                         ((INSTANCE) == UART7)   || \
                                         ((INSTANCE) == UART8)   || \
                                         ((INSTANCE) == LPUART1))

/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                              ((INSTANCE) == USART2) || \
                                              ((INSTANCE) == USART3))

/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                                            ((INSTANCE) == USART2) || \
                                                            ((INSTANCE) == USART3) || \
                                                            ((INSTANCE) == UART4)  || \
                                                            ((INSTANCE) == UART5)  || \
                                                            ((INSTANCE) == UART7)  || \
                                                            ((INSTANCE) == UART8))

/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1)  || \
                                                      ((INSTANCE) == USART2)  || \
                                                      ((INSTANCE) == USART3)  || \
                                                      ((INSTANCE) == UART4)   || \
                                                      ((INSTANCE) == UART5)   || \
                                                      ((INSTANCE) == UART7)   || \
                                                      ((INSTANCE) == UART8)   || \
                                                      ((INSTANCE) == LPUART1))

/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1)  || \
                                                 ((INSTANCE) == USART2)  || \
                                                 ((INSTANCE) == USART3)  || \
                                                 ((INSTANCE) == UART4)   || \
                                                 ((INSTANCE) == UART5)   || \
                                                 ((INSTANCE) == UART7)   || \
                                                 ((INSTANCE) == UART8)   || \
                                                 ((INSTANCE) == LPUART1))

/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                           ((INSTANCE) == USART2)  || \
                                           ((INSTANCE) == USART3)  || \
                                           ((INSTANCE) == UART4)   || \
                                           ((INSTANCE) == UART5)   || \
                                           ((INSTANCE) == UART7)   || \
                                           ((INSTANCE) == UART8)   || \
                                           ((INSTANCE) == LPUART1))

/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
                                          ((INSTANCE) == USART2) || \
                                          ((INSTANCE) == USART3) || \
                                          ((INSTANCE) == UART4)  || \
                                          ((INSTANCE) == UART5)  || \
                                          ((INSTANCE) == UART7)  || \
                                          ((INSTANCE) == UART8))

/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1)  || \
                                                      ((INSTANCE) == USART2)  || \
                                                      ((INSTANCE) == USART3)  || \
                                                      ((INSTANCE) == UART4)   || \
                                                      ((INSTANCE) == UART5)   || \
                                                      ((INSTANCE) == UART7)   || \
                                                      ((INSTANCE) == UART8)   || \
                                                      ((INSTANCE) == LPUART1))

/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                    ((INSTANCE) == USART2) || \
                                    ((INSTANCE) == USART3) || \
                                    ((INSTANCE) == UART4)  || \
                                    ((INSTANCE) == UART5)  || \
                                    ((INSTANCE) == UART7)  || \
                                    ((INSTANCE) == UART8))

/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                         ((INSTANCE) == USART2) || \
                                         ((INSTANCE) == USART3))

/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)

/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)

/****************************** XSPI Instances ********************************/
#define IS_XSPI_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == XSPI1) || \
                                         ((INSTANCE) == XSPI2))


/** @} */ /* End of group STM32H7RSxx_Peripheral_Exported_macros */

/** @} */ /* End of group STM32H7S3xx */

/** @} */ /* End of group ST */

#ifdef __cplusplus
 }
#endif /* __cplusplus */

#endif /* STM32H7S3xx_H */
