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[Question] STM32F0 cotex-M0 i2c master init (attached file- code/clock images)

Question asked by k.j.001 on Oct 22, 2012
I am trying to make i2c driver with stm32f0 cotext M-0. I am a very newer. I am reading specification, RM0091 and following the instruction. I set STM32f0 i2c as a master and I followed the RM0091 (24.4.9 I2C master mode): 
############### [trial 1 - difference is (2-1) with trial 2] ########################
(1) config clock , gpio , I2C init (based on 24.4.5, RM0091) - until here seems ok
(2-1) master init (based on 24.4.9, RM0091) - config NBYTES, 10bitAddress(Disable), config slaveAddress, config master request, Generate Start => I used one by one the standard lib functions in stm32f0xx_i2c.c
(3) I2C write : write some test data to slave.
=========> [result1] in oscilloscope ; SCL clock pulses first (8 pulse) , then SDA clock pulses.(I assume this wrong) then SCL 9th clock pulse (assume ACK/NACK) then both goes high again.(this assume ok) : I think that SCL/SDA clock should pulse same timing after SDA start generation.


############### [trial 2 - difference is (2-2) with trial 1] ########################
so I searched this and that... then saw 'I2C_TransferHandling(..)' in 'updated' stm32f0xx_i2c.c
I2C_TransferHandling : it looks like all the combined functionality for the master init (except 10bitAddress(Disable/Enable) - I am using 7bit Address mode )
so my second try :
(1) same - clock, gpio, i2c int
(2-2) used 'I2C_TransferHandling' for master int and added 10bitAddressModeCmd(.., DISABLE);
(3) same- I2C write
================> [result2] in oscilloscope : SCL/SDA clock much more precise after Start generation , it looks it suppose to be with same timing. (SDA start pulse-> SCL low ->DATA pulse, Clock 8bits(pulses) in same timing-> SCL 9th(ACK/NACK) pulse... good until here! then... problem...SCL/SDA clock don't goes high again. it Stay low forever.... (I searched this and that again. I tried NO Clock Streatch.. but no differences) ... the reason I assume it cause Data line arbitration (I even put the debug code and check the arbitration register , YES. it is arbitration error.) but I don't know why... I know it is something missing in the master init when I used (2-2) trial with I2C_TransferHandling / 10bitAddressModeCmd(Disable) ... but I do not know WHAT is mising.. ????

´######################### Question ##########################################

 

DOSE ANYONE HAVE ANY IDEA ABOUT THIS?????

Question 1) [trial 1] - [result 1]  : why scl / sda clock pulses are not in the same timing???
Question 2) [trial 2] - [result 2] : why it cause SDA arbitration /SDA-SCL held low forever ???????

I have clock images for both result, if anyone can give advices, I will appreciate it.. Thank you /J.

 

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