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interupt TIM2 assenbler

Question asked by kowalski.robert on Nov 7, 2016

hello. I have a problem with interupt from timer TIM2 - not working; I don't have a syntax error.

stm8/

 #include "mapping.inc"
 #include "STM8S207K6.inc"

;**************************************************
 segment 'ram0'
;...............................deklaracje zmiennych na stronie RAM0 !!!

data_1       dc.b 1
data_2       dc.b 1
data_3       dc.b 1

;**************************************************
 segment 'ram1'
;...............................deklaracje zmiennych na stronie RAM1 !!!
data_4       dc.b 1

;**************************************************
 segment 'rom'
main.l
;..............................initialize SP
   ldw X,#stack_end
   ldw SP,X

;**************************************************
 #ifdef RAM0 
;..............................clear RAM0
ram0_start.b EQU $ram0_segment_start
ram0_end.b EQU $ram0_segment_end
   ldw X,#ram0_start
clear_ram0.l
   clr (X)
   incw X
   cpw X,#ram0_end 
   jrule clear_ram0
 #endif

;**************************************************
 #ifdef RAM1
;..............................clear RAM1
ram1_start.w EQU $ram1_segment_start
ram1_end.w EQU $ram1_segment_end 
   ldw X,#ram1_start
clear_ram1.l
   clr (X)
   incw X
   cpw X,#ram1_end 
   jrule clear_ram1
 #endif

;**************************************************
;..............................clear stack
stack_start.w EQU $stack_segment_start
stack_end.w EQU $stack_segment_end
   ldw X,#stack_start
clear_stack.l
   clr (X)
   incw X
   cpw X,#stack_end 
   jrule clear_stack

;**************************************************
;**************************************************
;**************************************************
CPU_registers_init
   CALLR   PB_port_init
   CALLR   PC_port_init
   CALLR   PD_port_init
   CALLR   TIM2_init
;   CALLR   TIM1_compare_interupt

  JP   main_loop

;---------------------------------Port PB floating inputs
.PB_port_init
   LD    A, #%00000000
   LD    PB_DDR, A
   LD    PB_CR1, A
   LD    PB_CR2, A
  RET

;---------------------------------Port PC output, push-pull
.PC_port_init
   LD    A, #%11111111
   LD    PC_DDR, A
   LD    PC_CR1, A
   CLR    A
   LD    PC_CR2, A
   LD    PC_ODR, A
  RET

;---------------------------------Port PD output, push-pull
.PD_port_init
   LD    A, #%11111111
   LD    PD_DDR, A
   LD    PD_CR1, A
   CLR    A
   LD    PD_CR2, A
   LD    PD_ODR, A
  RET

;---------------------------------TIM2 timer init
.TIM2_init
   MOV   TIM2_PSCR,#$03     ;timer 2 prescaler div by 32768
   MOV   TIM2_ARRH,#$C3     ;msb must be loaded first; autoreload value
   MOV   TIM2_ARRL,#$50     ;lsb autoreload value
   CLR   TIM2_IER
   BSET   TIM2_IER, #0            ;set bit 0 for update irq's on irq13
   CLR   TIM2_CR1
   BSET   TIM2_CR1, #0      ;set CEN bit to enable the timer
  RET

;**************************************************
;**************************************************
;**************************************************

main_loop
  RIM                        ;reset the cpu interupt mask
   
   LD   A, #$AA
   LD   data_1, A
   LD   A, #$BB
   LD   data_2, A
   LD   A, #$CC
   LD   data_3, A
   LD   A, #$DD
   LD   data_4, A
  
  JP main_loop
 RET

;...........................................................
;........................INTERRUPTS.........................
;...........................................................

; Timer 2 update interupt handler
   interrupt Timer2_Update_Interupt
Timer2_Update_Interupt
   BRES  TIM2_SR1,#0   ;reset interupt flag
   CLR  data_1
   CLR  data_2
   CLR  data_3
   CLR  data_4
  iret
   

;******************************************************************************
; not use interupt
;******************************************************************************
   interrupt Non_Handled_Interrupt
Non_Handled_Interrupt.l
  iret

;******************************************************************************
 segment 'vectit'
 dc.l {$82000000+main}         ; reset
 dc.l {$82000000+Non_Handled_Interrupt} ; trap
 dc.l {$82000000+Non_Handled_Interrupt} ; irq0  TLI External top level interrupt
 dc.l {$82000000+Non_Handled_Interrupt} ; irq1  AWU Auto wake up from halt
 dc.l {$82000000+Non_Handled_Interrupt} ; irq2  CLK Clock Controller
 dc.l {$82000000+Non_Handled_Interrupt} ; irq3  EXTIO Port A external
 dc.l {$82000000+Non_Handled_Interrupt} ; irq4  EXTI1 Port B
 dc.l {$82000000+Non_Handled_Interrupt} ; irq5  EXTI2 Port C
 dc.l {$82000000+Non_Handled_Interrupt} ; irq6  EXTI3 Port D
 dc.l {$82000000+Non_Handled_Interrupt} ; irq7  EXTI4 Port E external
 dc.l {$82000000+Non_Handled_Interrupt} ; irq8  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq9  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq10  SPI end of transfer
 dc.l {$82000000+Non_Handled_Interrupt} ; irq11  TIM1 Update/overflow/underflow/trigger/break
 dc.l {$82000000+Non_Handled_Interrupt} ; irq12  TIM1 Capture/Compare
 
; dc.l {$82000000+Non_Handled_Interrupt} ; irq13  irq13 TIM2 update/overflow
 dc.l {$82000000+Timer2_Update_Interupt}   ; irq13 TIM2 update/overflow
 
 dc.l {$82000000+Non_Handled_Interrupt} ; irq14  TIM2 capture / compare
 dc.l {$82000000+Non_Handled_Interrupt} ; irq15  TIM3 Update/ overflow
 dc.l {$82000000+Non_Handled_Interrupt} ; irq16  TIM3 Capture / Compare
 dc.l {$82000000+Non_Handled_Interrupt} ; irq17  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq18  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq19  I2C
 dc.l {$82000000+Non_Handled_Interrupt} ; irq20  Uart2 Tx Complete
 dc.l {$82000000+Non_Handled_Interrupt} ; irq21  Uart2 Receive Register Data Full
 dc.l {$82000000+Non_Handled_Interrupt} ; irq22  ADC1 end of conversion
 dc.l {$82000000+Non_Handled_Interrupt} ; irq23  TIM4 Update/Overflow
 dc.l {$82000000+Non_Handled_Interrupt} ; irq24  Flash EOP/WR_PG_DIS
 dc.l {$82000000+Non_Handled_Interrupt} ; irq25  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq26  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq27  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq28  reserved
 dc.l {$82000000+Non_Handled_Interrupt} ; irq29  reserved

 end
 
;***********************************************************

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