we have adopted stm8 in our application and get into production a year ago, which seemed ok, in reasonablly sum of quantity.
but recent two batch of chips, mainly stm8s208, also messed up with stm8s105, give us big headache, same problem-- the reset pin problem, which is pulsing from mcu inside when in application run without swim interface present and even with swim pin disabled in application, some are with 50us low time and some stays low longer, some appear regularly, some appear ocassionally, some are with internal clock trim register value.
some work is done trying to understand this:
1. the reset status regsiter under st link debugging mode shows 0x18, which indicates two sources: one is the ems reason, and the other is the swim reset reason. We tried to clear the flag by writing 0x18 to this register, but the register value changes to 0x10 rather than 0x00 as expected. why? when we do this, inside emc clean lab and the board is guranteed without ground bouncing or high freq coupling sort of basic troubles.
2. for these trouble maker chips, we observed they all suffered from another problem: the internal 16MHz clock accuracy problem. by default, all these chips should be factory tuned to be close to 1%, literaturely to be -3% to +1% at 25degC, but it seems some chip gives large variation with 18MHz observed. we spotted this problem is because we found large number of boards cannot communicate well with our 115200baud PCside host software.
3.for some chip, if we tune the clock trim register, bizzar thing can happen: for example, some chip starts to do comms if the trim reg value is 0x3, but with 0x4 value tried, this chip starts to reset itself!
4.from the manual, we only know there is another internal clock carliberation reg for st factory tune purpose, while the trim reg open to us, normal user, is on top that internal reg to work together for fianl 16MHz clock rate, no access for us, and not enough info for us to understand further, like, is there ways in our user site to tune the clock as factory doing? As for the emsf flag in reset status reg, only info from mannual is some crital clock related registers have bitfields need to be complementary to each other on power up, otherwise chip treat the scenario as if high emc intervene happening and reset circuitry will act to pull low reset pin, but which registers are these critical registers? we really want to know, we have big number of boards need to be fixed, and what is the root cause for this reset problem? It is not enough for us simply put it to bad luck that dud chips fall in our hands. If this is the case, how can we in the futuer to avoid these faulty chips? our customers are shouting at us as the viechle equipped with these chips give all kinds of horrible things in the field, some has broken wheel shaft!
5. another strange thing: if we put swim lines up and in debugging mode but let chip and board free fun, the very same chip who keeps reseting itself without swim lines in talking, will CEASE reseting! why?
6. In a short, feeling is that this reset pin problem is to do with some clock registers, especially that clock factury tunning register; maybe it is also to do with the swim dm module.
7. badly need some expertise coming out kindly to help; or maybe some one can tell me how to remotely access the st technical help team?