AnsweredAssumed Answered

SPL to CubeF4 conversion issues

Question asked by jacob.ariel on Mar 27, 2015
Latest reply on Mar 27, 2015 by jacob.ariel
I need to integrate an old code written using the Standard Peripheral Library to a new (big)project that's using CubeF4.
As easy as it sounds I can't find any commonality between the libs..
1. Is there any documentation to help with migration?
2. Is there a way to access the "old" SPL function / easily make them live side by side?
3. I can find implementation to basic functions, like:
The following SPL function TIM_ARRPreloadConfig() configures TIM_CR1_ARPE bit in CR1 register.
Yet I was unable to find where ARR is configured in the new HAL lib.

What do you suggest, how should I attack this?
(Please ignore if it’s an inappropriate offer, but) I am willing to pay for the conversion assistance.

Below is the code, there is also SPI and DMA init calls.     

    /// Init Timers for the DMA

    TIM_TimeBaseInitTypeDef timerInitStructure;
    TIM_BDTRInitTypeDef timer_BDTRInitStruct;

    /// Setup TIM4 Timer as master clock which is used as clock source
    /// for timers TIM1, TIM2, TIM3, TIM5 & TIM8. TIM4@84MHz. In this
    /// way all DMA<->SPI's are in sync
    /// All DMA and SPI TIM's must have same ARR register value in order
    /// for them to be in sync. 
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);                // enable TIM3

    TIM_TimeBaseStructInit(&timerInitStructure);                        // fill structure with default values
    timerInitStructure.TIM_Prescaler = (TIM_PRESCALER) - 0x0001;        // set TIM1 counting prescaler to 1 (PSC register)
    timerInitStructure.TIM_Period = TIM4_PERIOD;                        // reload value set to 1 -> 21MHz clock (ARR register)

    TIM_TimeBaseInit(TIM4, &timerInitStructure);                        // Init timer with structure
    TIM_UpdateRequestConfig(TIM4, TIM_UpdateSource_Regular);            // set update request source to generate interupt or DMA request (CR1->URS bit)
    TIM_ARRPreloadConfig(TIM4,ENABLE);                                  // set auto-reload preload to enable (CR1->ARPE)
    TIM_SelectOutputTrigger(TIM4, TIM_TRGOSource_Update);               // set master mode selection to update (CR2->MMS)
    TIM_GenerateEvent(TIM4, TIM_EventSource_Update);                    // set update generation (EGR->UG)
    TIM_Cmd(TIM4, ENABLE);                                             

    /// Setup TIM2 as slave timer clocked by TIM4. TIM2 triggers DMA
    /// which transfers channel selection data through SPI3.
    /// TIM2 CC4 with 4us is used for the CONV
    /// TIM2 CC4 with 4us is used as trigger for transmission of channel
    /// selection data with 50 us period

    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);                // enable TIM2

    timerInitStructure.TIM_Prescaler = (TIM_PRESCALER) - 0x0001;        // set TIM2 counting prescaler to 1 (PSC register)
    timerInitStructure.TIM_Period = TIM2_PERIOD;                        // 42MHz/1 = 42MHz -> count each 1/42MHz (ARR register)
    TIM_TimeBaseInit(TIM2, &timerInitStructure);

    TIM_SelectSlaveMode(TIM2,TIM_SlaveMode_External1);                  // Set slave mode to external clock mode TIM4 (SMCR->SMS)
    TIM_SelectInputTrigger(TIM2,TIM_TS_ITR3);                           // Set internal triger to TIM4 (SMCR->TS)
    TIM_UpdateRequestConfig(TIM2, TIM_UpdateSource_Regular);            // set update request source to generate interupt or DMA request (CR1->URS bit)
    TIM_ARRPreloadConfig(TIM2,ENABLE);                                  // set auto-reload preload to enable (CR1->ARPE)
    TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_OC4Ref);               // trigger output (TRGO) on CC4 (CR2->MMS)
    TIM_SetCompare4(TIM2,0x00A8);                                       // duty cycle for the PWM set to 168 = 4us (CCR4 register)
    TIM_OC4PreloadConfig(TIM2,TIM_OCPreload_Enable);                    // enable OC4PE preload mode (CCMR2->OC4PE)
    TIM_ForcedOC4Config(TIM2,TIM_OCMode_PWM1);                          // set PWM1 mod (CCMR2->OC4M)
    TIM_OC4PolarityConfig(TIM2,TIM_OCPolarity_High);                    // set pulse polarity to active high (CCER->CC4P)
    TIM2->CCER |= (TIM_CCER_CC4E);                                      // enable capture compare mode
    TIM_DMACmd(TIM2,TIM_DMA_CC4,ENABLE);                                // enable DMA request on capture compare CC4 event DIER->CC4DE
    TIM_GenerateEvent(TIM2, TIM_EventSource_Update);
    TIM_Cmd(TIM2, ENABLE);