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Question asked by plotnikov.natalia on Oct 26, 2014

I work on ST-Microcontroller  :STM8S003F3U6.

I try to use TIM1 as a trigger (TRGO) for ADC interrupt.

When I use the single pulse (TIM1_CR1_OPM=1)   mode (on TIM1 counter overflow) everything seems to work well,

but when I change TIM1_CR1_OPM to "0" for counter's continuous work, the ADC interrupt stops working.

TIM1 no longer launch ADC at the TIM1-counter overflow.


I need TIM1-counter work continuously and start ADC at every TIM1-counter overflow.

I don’t understand what am I doing wrong?

the relevant parts of my code:

//*******ADC + TIM1**  init  ******************************/








  ADC_CR1_ADON=0;         // power OFF ADC



  ADC_CR1_SPSEL=ADCPS;    // sampling rate


  ADC_CR2_ALIGN=1;        // right align


  ADC_CSR_CH=4;           // point to  channel




  ADC_CR2_EXTSEL=0;     //Internal TIM1 TRGO event


  ADC_CR2_EXTTRIG=1;    //Conversion on external event disabled




  ADC_CSR_EOCIE=1;         //end of conversion interrupt enable




  TIM1_PSCRH=0x00;         // set prescaler


  TIM1_PSCRL=0x10;         // 1MHz


  TIM1_ARRH=0x00;          //00 // set irq reriod






  TIM1_CR1_URS=TRUE;      //gen timer irq on overflow only 


  TIM1_IER_TIE=1;         //enable TRIG  irq




  TIM1_CR2_MMS=0x01;     //enable master mode




  TIM1_CR1_OPM=0;              // Counter is not stopped at update event



































/*                      MAIN                                                                            */




void main(void)






        TIM1_CR1_CEN=TRUE;        //enable Timer1 counter   




   /* Loops 'forever', taking input when interrupted. */


while (1)


   {  }





















/* Defines an interrupt handler for the ADC vector                                                            */






#pragma vector=ADC_VECTOR


__interrupt __root void ADCHandler(void)






 while (ADC_CSR_EOC==0) {}




                     ADC_CSR_EOC=0;   //End of conversion






  TIM1_SR1_UIF=0;            // rset pending irq