AnsweredAssumed Answered

TIM1->CCMR1 erratic operation

Question asked by bryson.paul on Jun 20, 2014
Someone, please help, I am really stumped.
Is there some secret process not mentioned in the ref manual for writing to the CCMR1 register?
For any single code sequence the behavior is repeatable even if wrong; but if I change up the code, the behavior changes.
I am trying to force the output pin by writing 0x50 and 0x40 to the CCMR1 register. Often I can see the pin go high momentarily but then go back low. Sometimes the value doesn't go into the register - reads back as 0x00. When I set the GPIOC->ODR bit, the pin goes high - it's not supposed to when the counter channel is enabled? Is it?  Earlier in the code I have the channel working properly in compare mode with TIM1->CCMR1=0x18.
At start up, I write, TIM1->BKR = 0x88. 
TIM1->CCER1=0x11

Should the SR1 bit be set for that channel? It isn't.

I have tried writing the register multiple times with delay between.
I have tried toggling the CC1E bit with no effect.
I have tried toggling the CC1P bit with no effect.
But writing to GPIOC->ODR DOES toggle the pin - but it shouldn't.

Any help would be greatly appreciated.

Registers1A.jpg

Outcomes