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C90LC SSD Flash Driver for SPC564B74 Problem

Question asked by ehcsur on Dec 18, 2014
Latest reply on Jan 19, 2015 by ehcsur
Hello,

since ST did not respond to any license key request, and it is not possible to contact support I will try it here:
I need a license key for C90LC SSD Flash Driver for Programming SPC564B74

Meanwhile I took the C90LC SSD JDP Flash Driver from a Freescale compatible device MPC564xB (where you don't need a fricking license key for any of their drivers).
Since then I have strange problems executing the FlashInit function through JTAG Nexus Interface. Everything works as expected, until leaving Debug mode for executing the function (BTW: which is not only horribly explained but differently done by the PE Micro Nexus Multilink Programmer).

If I do it the way described in AN4365 ( Qorivva MPC56xx Flash Programming Through Nexus/JTAG - Application Notes  ) the FlashInit won't be called and CPU will enter Debug mode instantly. In this case the CPUSCR returns: PC: 0xFFFFC004, IR: 0x7C0103A6, CTL: 0x0.
According to PC it's somewhere in the Boot Assist Module hence I assume something went wrong.

The Steps I have done:

- Setup MMU as described in 4.1
- cleared interrupt vectors
- Init SRAM as described in 4.2

- (5.2.2 Step 1) uploaded ssd_config structure to sram start at 0x40000000:
    _ssd_cfg.c90flRegBase = 0xC3F88000;
    _ssd_cfg.mainArrayBase = 0x00000000;
    _ssd_cfg.mainArraySize = 0;
    _ssd_cfg.pageSize = 0x0008;
    _ssd_cfg.shadowRowBase = 0xFFC000;
    _ssd_cfg.shadowRowSize = 0x4000;
    _ssd_cfg.lowBlockNum = 0;
    _ssd_cfg.highBlockNum = 0;
    _ssd_cfg.midBlockNum = 0;
    _ssd_cfg.BDMEnable = 1;
- uploaded C90LC_JDP_SSD FlashInit VLE c_array driver to 0x40000028
- (5.2.2 Step 2) setup r1 as stack pointer to 0x40001FFF
- (5.2.2 Step 3) setup r3 to point to ssd_config structure: 0x40000000
- (5.2.2 Step 4) setup CPUSCR with CTL: 0x00000002,
                                    IR: 0x1800D000,
                                    PC: 0x40000024,
                                   MSR: 0x00000002
- (5.2.2 Step 5) 2.8 Exit from Debug mode:
    - A) Clear OCR[DMDIS], OCR[DR] bits (by writing back previous read and
               both bits cleared value?).
         Note: OCR[MCLK] is referenced at 2.8 as you should leave the bit set,
               but it's not a valid bit of OCR rather it belongs to OSR and
               hence it's read only
    - B) Write CPUSCR (CTL, IR, PC, MSR) (Is this really necessary, since it's
               already done in 5.2.2 Step 4 ?)
    - C) Write OCMD with bits set GO, EX and RS=CPUSCR
         Note: According to this description I would assume that after this
               command DEBUG mode is left and CPU is running. In e200z4
               Reference Manual there it says:

               "The processor will leave the debug mode after the TAP
               controller Update-DR state is entered."

               So I assume something is wrong here and a write to CPUSCR is
               needed after that too. So I tried swapping B, and C.
               (that's what PE Micro Nexus Multilink is doing)

- (5.2.2 Step 6) Poll OnCE Status Register (OSR) for re-entering Debug Mode
- (5.2.2 Step 7) read the return value in r3


As I already said: If I do it that way the return value in r3 points still to the ssd_config structure, so FlashInit didn't execute?
CPUSCR is PC: 0xFFFFC004,
          IR: 0x7C0103A6,
         CTL: 0x0

If I do it the way PE Micro Nexus Multilink does (swapping 5.2.2 Step 5: B and C):
when Polling OnCE Status Register (5.2.2 Step 6) the first time I get 1000100001 (MCLK, HALT is set)
then every following time 0100011000 (ERR, STOP, DEBUG is set) and even Bit 9 which should be always 1 is not set.

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