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L3GD20 Power Down Mode Startup Timing

Question asked by greenwood.roy on Sep 15, 2016
I am trying to optimize the power consumption for bringing the L3GD20 out of Power Down mode, initialize a FIFO acquisition, acquire the data via I2C and then place the device back into Power Down mode. The register requirements to do this are well documented, however the datasheet and app notes are very sketchy on the required power on timing and the time to achieve FIFO data stability.
The first decision I am trying to make is whether to switch from Power Down to Sleep then Normal, or go directly from POwer Down to Normal. The power supply current specifications would indicate some potential power savings by transitioning through Sleep Mode, can anyone verify this.
The second decision relates to how long to wait after switching to Normal Mode before data becomes stable and can be acquired into the FIFO. Anyone know what the timing requirements are?

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