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STM8S103K3 - ADC takes longer than expected?

Question asked by bryson.paul on Mar 27, 2014
I am timing the ADC conversion from TRGO to EOC.  I calculate that the conversion should take 3.5us but I measure a minimum of 4.0us using an oscilloscope.
I have included the relevant code loop below.

Please does anyone know where the extra time is coming from?  
My application requires close coordination of the ADC with external signals. 

//////////////////////////////////////////////////////////
TRGO = TIM1 CH4 = (counter=0x01)
ADC clk = 4MHz
conversion = 14 clocks / 4Mhz = 3.5us
measured: 4.0us (minimum) between toggles


////////////////////////////////////////////////
while(!(GPIOC->IDR & 0x08)){}          //  wait for pwm sig high (counter=x)
for (tempi=0; tempi<5000;tempi++)
{
     while(GPIOC->IDR & 0x08){}          //  wait for pwm sig low (counter=0)
     GPIOB->ODR ^= 0x80;                      // toggle pin
     ADC1->CSR = 0x00;                       // clr EOC (@ top of loop to catch 1st pass)
     while(!(ADC1->CSR & 0x80)) {}          // wait for ADC completion
     GPIOB->ODR ^= 0x80;                       // toggle pin
     while(!(GPIOC->IDR & 0x08)){}          //  wait for pwm sig high (cntr=x)
}


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