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Entering Halt mode with the IWDG enabled causes reset for STM8s003F3P6 Chip

Question asked by hoeneveld.bill on Oct 21, 2013
Latest reply on Feb 10, 2014 by siega_brussatin.more
I've checked the Option Bytes and the OPT3 byte is zero so the WDG_HALT bit is 0 which means that the MCU should enter Halt Mode without causing a reset when the watchdog is enabled.
However a  HALT or WFI generates a reset. I refresh the watchdog counter prior to the halt instruction and it still generates a reset.  If I do not set up IWDG then no reset is generated and the program continues correctly when it comes out of halt by an interrupt.
I have set and reset the option byte for WDG_HALT  but it always generates a reset when the IWDG is enabled by software and halt is entered. 

What should I set up to overcome this?  Is this a known problem with the chip?

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