Interrupt Controller Type Register:
Read the Interrupt Controller Type Register to see the number of interrupt lines that the
The NVIC supports up to 240 dynamically reprioritizable interrupts...
● 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
When setting a position, the offset must be
aligned based on the number of exceptions in the table. This means that the minimal
alignment is 32 words that you can use for up to 16 interrupts. For more interrupts, you
must adjust the alignment by rounding up to the next power of two. For example, if you
require 21 interrupts, the alignment must be on a 64-word boundary because table size
is 37 words, next power of two is 64.
* - Offset: Vector Table base offset field.
* This value must be a multiple of 0x100.
SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
Vector Table Offset Register bit assignments:
Bits Field Function
[31:30] - Reserved
 TBLBASE Table base is in Code (0) or RAM (1)
[28:7] TBLOFF Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM
or CODE space.
[6:0] - Reserved.
Retrieving data ...