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STM8 Instruction Pipelining

Question asked by ivanov.artyom on Nov 16, 2011
Latest reply on Nov 20, 2011 by ivanov.artyom
Hello everybody!

I've just got acquainted with STM8-L family and I'm already really fascinated. I have some questions though. Could anybody please help me?

I'm currently reading the document called " CPU Programming Manual", the chapter containing information about the pipelining of the controller.

Let's look at one of the first pages. It shows an example of the pipelining. I've marked the assembler commands with different colours for a better view.

bcd3e40e368d.png
We can see a few commands here. The first item I had to deal with, was how exactly is the number of CPU cycles for each command determined. It is divided into two parts: decode cycles and execute cycles. Let's look at the first command, LDW, here is its description from the same document.

82e4f172b7ea.png

We can see, that this command takes 5 CPU cycles. And really, the first picture says it takes 4 cycles to decode and 1 to execute. 4 + 1 = 5, all clear.

Let's proceed to the next command, ADDW. Here's the decription.

2a4618a3f3db.png

It says that this command should take 2 cycles! And here comes the question: why does the first picture say it takes 2 cycles to decode and 2 to execute? 2 + 2 = 4, isn't it?..

If we look at the next command (which, by the way, seems to have a syntax mistake) and compare its description with the first picture, we will see that the number of cycles is equal: 3 + 1 = 4.

567d87c9cd14.png

So please, could anybody tell me - where am I (or the datasheet) mistaken? It seems I do not understand, how is the number of cycles determined for the first picture and how does it correspond to the number of cycles determined in the commands' description. Help me, please! :)

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