I have configured ARR register to 0x0000000A and Enable ARR interrupt interrupt not generate after 0x0000000A
but after 1 extra one pulse generate interrupt
I guess ST made this to work identically as the Update interrupt/signal works the "normal" timers, i.e. that the ARRM interrupt does not happen at "autoreload match" as the documentation says, but at the moment when CNT rolls over from the ARR value to zero.
Take it as one of the defficiencies in the documentation.
Of course it would be nice to hear ST's comment on the matter (and, when at it, it would be also nice to see finally some real numbers on the maximum input frequency of LPTIM in the datasheets).
Further findings, which IMO deserve being properly documented (I am playing with a 'L476 Disco, thus following pertains to RM0351 Rev.6):
- the same behaviour is for CMPM, i.e. it is set when the counter counts *away* from the CNT==CMP match
- both these symptoms are independent from whether the external input is synchronous (CFGR.COUNTMODE=1) or asynchronous (CFGR.CKSEL=1)
- while in the narrative there is a mention that there must be two clocks after CR.ENABLE is set,
- this is not mentioned in the CR register's ENABLE bit's description (i.e. in ch.34.7.5) and ought to be, as it's unusual
- the narrative should outline that the consequence of this is, that if set to external clock, at least two pulses must pass before a trigger (even the software one, by setting CR.CNTSTRT) is accepted - this should be mentioned because it is a surprising element, and it may well be that in a real-life application there is a desire to set up and trigger LPTIM before the external clock is available, so that it can start counting from the very first external edge -- and in that case, as clock source cannot be switched on the fly (because CFGR cannot be changed once CR.ENABLE is set), the application has to have some means to force the required clocks (eg. by switching to a different LPTIMx_IN1 pin in GPIO, which is shorted to another GPIO pin, using which the two clocks are generated; or similar workaround)
- similar consequence is, that if from disabled state both CR.ENABLE and CR.CNTSTRT are set at once, regardless of internal or external clock, CR.CNTSTRT gets ignored, i.e. even with internal clock, CR register has to be written twice (first with CR.ENABLE set alone, and then with both those bits set). This again is not quite usual, that's why it ought to be pointed out.
- in the Peripherals interconnect matrix chapter, while there's a LPTIM subchapter, it deals only with the triggers, and forgets to mention that COMP1/2_OUT can be used as inputs (through the option registers)
- only the LPTIM2 option register description contains footnote, what happens if both bits are set - why not also LPTIM1?
- Table 211. LPTIM1 external trigger connection for lptim_ext_trig0 says "GPIO" - but which GPIO? I guess it's LPTIMx_ETR, as there's no mention of its function anywhere in RM nor DS, but am I really supposed to guess?
- and I reiterate the request for publishing timing data in the DS - especially maximum input clock frequency - for the asynchronous external clock mode
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