I've been beating my head against the wall for the last couple of days trying to figure out why I cannot read registers at odd addresses through the LIS3DSH SPI interface with the nRF52832. Byte accesses to even addresses work fine, but byte accesses to odd addresses always return the value of the register at the even address one location lower. 16-bit accesses only work when the address is even. It seems like the LSB of the register address is always read by the LIS3DSH as a zero.
Communicating via the I2C bus works fine - bytes, words, even and odd alignment are all OK.
So, it looks to me like the LIS3DSH has a bug in the SPI interface. My best guess is that the last bit of the address is not correctly latched internally by the rising edge of SCL, and must be held static until the next falling edge of SCL (at which time the LIS3DSH starts to drive the data bus).
Here's my proof:
Shown below is a logic analyzer capture with showing a single byte read of the WHO_AM_I register (address 0x0F). The bottom 4 traces are a delayed (expanded) version of the top four. Here, I drive MOSI (SDI) to zero after the rising edge of the 8th clock in the "address" phase of the transfer. The hold time is shown to be about 460nsec. You can see that the data (MISO) returned during the next 8 clocks is 0x00 (corresponding to register 0x0E, INFO2).
In the second capture, I hold the last bit of the address until the falling edge of that same clock. Here, the data returned is correct for WHO_AM_I (0x3F).
The data sheet says the hold time is only 15 nsec, relative to the rising edge of SCL. It looks like you have to hold the 8th bit of the address (and only the 8th bit) until the falling edge of SCL.
So, is this a bug in the chip? I didn't see any mention of this in the errata sheet.
This is not a problem if the last bit of the address is held static through the data transfer. In my case, I'm now bit-banging the I/O ports, so I merely leave the MOSI (SDI) pin in its last state.
Unfortunately the built-in SPI interface of some micro's (like the nRF52832) drive the MOSI line low immediately after the last bit of the address is clocked out during read operations. This means you can't do individual byte reads of registers at odd addresses. The work-around would be to do a word-aligned 16-bit read and select the proper byte. Fortunately the 16-bit X, Y, and Z data values in the LIS3DSH are word aligned and 16-bit SPI reads with chips like the nRF52832 work fine.